From 5187c781844344195138f2ca4ffe51237f5fc262 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 16:18:04 -0600
Subject: [PATCH] Fixed forwarding bug in the BTB.

---
 src/ifu/bpred/bpred.sv | 2 +-
 src/ifu/bpred/btb.sv   | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index e7bf1be1..97101a3e 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -148,7 +148,7 @@ module bpred (
           .PCNextF, .PCF, .PCD, .PCE, .PCM,
           .PredPCF,
           .BTBPredInstrClassF,
-          .AnyWrongPredInstrClassE,
+          .PredictionInstrClassWrongM,
           .IEUAdrE, .IEUAdrM,
           .InstrClassD, .InstrClassE, .InstrClassM);
 
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 1dae8c89..a8f67efe 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -38,7 +38,7 @@ module btb #(parameter Depth = 10 ) (
   output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
   output logic [3:0] 	   BTBPredInstrClassF, // BTB's guess at instruction class
   // update
-  input logic 			   AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong
+  input logic 			   PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
   input logic [`XLEN-1:0]  IEUAdrE, // Branch/jump target address to insert into btb
   input logic [`XLEN-1:0]  IEUAdrM, // Branch/jump target address to insert into btb
   input logic [3:0] 	   InstrClassD, // Instruction class to insert into btb
@@ -74,7 +74,7 @@ module btb #(parameter Depth = 10 ) (
   assign MatchD = PCNextFIndex == PCDIndex;
   assign MatchE = PCNextFIndex == PCEIndex;
   assign MatchM = PCNextFIndex == PCMIndex;
-  assign MatchNextX = MatchF | MatchD | MatchE;
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
@@ -88,12 +88,12 @@ module btb #(parameter Depth = 10 ) (
   assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
 
 
-  assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
+  assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
 
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
-     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
+     .ce2(~StallM & ~FlushM), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
 
   flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);