From 5164129172417b5e9f64c2cd7fdba9b7ee2cc30f Mon Sep 17 00:00:00 2001
From: kwan <kwan@tera.eng.hmc.edu>
Date: Thu, 2 Dec 2021 10:32:35 -0800
Subject: [PATCH] .* resolved in ifu.sv

---
 wally-pipelined/src/ifu/ifu.sv | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 3f9bcf51..c0bfaaf8 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -141,7 +141,7 @@ module ifu (
        .STATUS_MPP,
        .PrivilegeModeW,
        .InstrAccessFaultF,
-       .PMPCFG_ARRAY_REGW, //bitfields?
+       .PMPCFG_ARRAY_REGW,
        .PMPADDR_ARRAY_REGW      
        );
 
@@ -158,7 +158,9 @@ module ifu (
   //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
-  icache icache(.*,
+  icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
+  .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
+
   .PCNextF(PCNextFPhys),
   .PCPF(PCPFmmu),
   .WalkerInstrPageFaultF,
@@ -206,7 +208,11 @@ module ifu (
   generate
     if (`BPRED_ENABLED == 1) begin : bpred
       // I am making the port connection explicit for now as I want to see them and they will be changing.
-      bpred bpred(.*,
+    
+      bpred bpred(.clk, .reset,
+    .StallF, .StallD, .StallE,
+    .FlushF, .FlushD, .FlushE,
+
     .PCNextF(PCNextF),
     .BPPredPCF(BPPredPCF),
     .SelBPPredF(SelBPPredF),
@@ -248,7 +254,8 @@ module ifu (
   flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  decompress decomp(.*);
+
+  decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
   assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
   // *** combine these with others in better way, including M, F