diff --git a/wally-pipelined/src/dmem/dcache.sv b/wally-pipelined/src/dmem/dcache.sv index 243c6975..fec70ef4 100644 --- a/wally-pipelined/src/dmem/dcache.sv +++ b/wally-pipelined/src/dmem/dcache.sv @@ -31,7 +31,7 @@ module dcache( input logic StallW, input logic FlushW, // Upper bits of physical address - input logic [`XLEN-1:12] UpperPAdrM, + input logic [`PA_BITS-1:12] UpperPAdrM, // Lower 12 bits of virtual address, since it's faster this way input logic [11:0] LowerVAdrM, // Write to the dcache @@ -41,7 +41,7 @@ module dcache( input logic [`XLEN-1:0] ReadDataW, input logic MemAckW, // Access requested from the ebu unit - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM, // High if the dcache is requesting a stall output logic DCacheStallW, @@ -56,7 +56,7 @@ module dcache( // Input signals to cache memory logic FlushMem; - logic [`XLEN-1:12] DCacheMemUpperPAdr; + logic [`PA_BITS-1:12] DCacheMemUpperPAdr; logic [11:0] DCacheMemLowerAdr; logic DCacheMemWriteEnable; logic [DCACHELINESIZE-1:0] DCacheMemWriteData; @@ -98,7 +98,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( // Input the address to read // The upper bits of the physical pc - input logic [`XLEN-1:12] DCacheMemUpperPAdr, + input logic [`PA_BITS-1:12] DCacheMemUpperPAdr, // The lower bits of the virtual pc input logic [11:0] DCacheMemLowerAdr, @@ -122,7 +122,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( input logic [`XLEN-1:0] ReadDataW, input logic MemAckW, // The read we request from main memory - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM ); @@ -144,7 +144,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( logic FetchState, BeginFetchState; logic [LOGWPL:0] FetchWordNum, NextFetchWordNum; - logic [`XLEN-1:0] LineAlignedPCPF; + logic [`PA_BITS-1:0] LineAlignedPCPF; flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState); flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum); diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index d05d592c..ba3617d0 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -40,7 +40,7 @@ module dmem ( input logic [`XLEN-1:0] WriteDataM, input logic [1:0] AtomicM, input logic CommitM, - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM, output logic [1:0] AtomicMaskedM, output logic DataMisalignedM, @@ -142,20 +142,20 @@ module dmem ( // Handle atomic load reserved / store conditional generate if (`A_SUPPORTED) begin // atomic instructions supported - logic [`XLEN-1:2] ReservationPAdrW; + logic [`PA_BITS-1:2] ReservationPAdrW; logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; assign lrM = MemReadM && AtomicM[0]; assign scM = MemRWM[0] && AtomicM[0]; - assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW; + assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc else ReservationValidM = ReservationValidW; // otherwise don't change valid end - flopenrc #(`XLEN-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`XLEN-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW); end else begin // Atomic operations not supported diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ea76556c..88e8f27a 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -47,7 +47,7 @@ module ahblite ( output logic [`XLEN-1:0] InstrRData, output logic InstrAckF, // Signals from Data Cache - input logic [`XLEN-1:0] MemPAdrM, + input logic [`PA_BITS-1:0] MemPAdrM, input logic MemReadM, MemWriteM, input logic [`XLEN-1:0] WriteDataM, input logic [1:0] MemSizeM, diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 29d77f09..ca0071b1 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -105,10 +105,19 @@ module ifu ( logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + logic [`PA_BITS-1:0] PCPFmmu; + + generate + if (`XLEN==32) + assign PCPF = PCPFmmu[31:0]; + else + assign PCPF = {8'b0, PCPFmmu}; + endgenerate + mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), - .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), + .PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), // *** is this the right way force these bits constant? should they be someething else? diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 3efc4cef..04deb694 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -57,7 +57,7 @@ module mmu #(parameter ENTRY_BITS = 3, input logic TLBFlush, // Physical address outputs - output logic [`XLEN-1:0] PhysicalAddress, + output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 86fe6f86..127dc5a5 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -78,7 +78,7 @@ module tlb #(parameter ENTRY_BITS = 3, input logic TLBFlush, // Physical address outputs - output logic [`XLEN-1:0] PhysicalAddress, + output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, @@ -202,11 +202,9 @@ module tlb #(parameter ENTRY_BITS = 3, // Output the hit physical address if translation is currently on. generate if (`XLEN == 32) begin - // *** If we want rv32 to use the full 34 bit physical address space, this - // must be changed - mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], Translate, PhysicalAddress); + mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress); end else begin - mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, Translate, PhysicalAddress); + mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); end endgenerate diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 2535eef3..c2dfd437 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -135,7 +135,8 @@ module wallypipelinedhart ( logic MemReadM, MemWriteM; logic [1:0] AtomicMaskedM; logic [2:0] Funct3M; - logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; + logic [`XLEN-1:0] MemAdrM, WriteDataM; + logic [`PA_BITS-1:0] MemPAdrM; logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] InstrPAdrF; logic [`XLEN-1:0] InstrRData;