From 500e6ff43083fc57cc654734beeaddecbd1bd2a6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 2 Dec 2021 18:09:43 -0600
Subject: [PATCH] Fixed buildroot to work with the fpga's merge.

---
 .../config/buildroot/wally-config.vh          |  6 ++--
 wally-pipelined/regression/wally-buildroot.do |  2 +-
 wally-pipelined/testbench/testbench-linux.sv  | 31 ++++++++++---------
 3 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh
index f00eda30..d2b532b2 100644
--- a/wally-pipelined/config/buildroot/wally-config.vh
+++ b/wally-pipelined/config/buildroot/wally-config.vh
@@ -86,9 +86,9 @@
 `define TIM_SUPPORTED 1'b1
 `define TIM_BASE       56'h80000000
 `define TIM_RANGE      56'h07FFFFFF
-`define EXT_SUPPORTED 1'b0
-`define EXT_BASE       56'h80000000
-`define EXT_RANGE      56'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
 `define CLINT_SUPPORTED 1'b1
 `define CLINT_BASE  56'h02000000
 `define CLINT_RANGE 56'h0000FFFF
diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do
index 13c5433f..7fc87452 100644
--- a/wally-pipelined/regression/wally-buildroot.do
+++ b/wally-pipelined/regression/wally-buildroot.do
@@ -25,7 +25,7 @@ vlib work-buildroot
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-vlog -lint +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
 
 
 # start and run simulation
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index d8e1bc36..2aaacee8 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -55,6 +55,8 @@ module testbench();
   logic [`AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
   logic             HCLK, HRESETn;
+  logic             HREADY;
+  logic 	    HSELEXT;
   logic [31:0]      HADDR;
   logic [`AHBW-1:0] HWDATA;
   logic             HWRITE;
@@ -68,19 +70,20 @@ module testbench();
   logic             UARTSin, UARTSout;
 
   logic SDCCLK;
-  tri1 SDCCmd;
-  tri1 [3:0] SDCDat;
-
-  assign SDCmd = 1'bz;
-  assign SDCDat = 4'bz;
+  logic      SDCCmdIn;
+  logic      SDCCmdOut;
+  logic      SDCCmdOE;
+  logic [3:0] SDCDatIn;
   
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;
-  wallypipelinedsoc dut(.clk, .reset_ext, .reset,
-                        .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR,
-                        .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
-                        .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
-                        .UARTSin, .UARTSout);
+  wallypipelinedsoc dut(.clk, .reset_ext,
+                        .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, 
+			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, 
+			.HTRANS, .HMASTLOCK, 
+			.GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout,
+			.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
 
   // Write Back stage signals not needed by Wally itself 
   parameter nop = 'h13;
@@ -311,16 +314,16 @@ module testbench();
     ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
     ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
     if (CHECKPOINT==0) begin // normal
-      $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
+      $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.dtim.RAM);
       traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
       traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
       InstrCountW = '0;
     end else begin // checkpoint
       $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
       checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
-      //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM);
+      //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.dtim.RAM);
       ramFile = $fopen({checkpointDir,"ram.bin"}, "rb");
-      readResult = $fread(dut.uncore.dtim.RAM,ramFile);
+      readResult = $fread(dut.uncore.dtim.dtim.RAM,ramFile);
       $fclose(ramFile);
       traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
       traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
@@ -676,7 +679,7 @@ module testbench();
           PAdr = BaseAdr + (VPN[i] << 3);
           // dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
           // by 3 (the PTE size) to get the requested 64-bit PTE.
-          PTE = dut.uncore.dtim.RAM[PAdr >> 3];
+          PTE = dut.uncore.dtim.dtim.RAM[PAdr >> 3];
           PTE_R = PTE[1];
           PTE_X = PTE[3];
           if (PTE_R || PTE_X) begin