From 4f1a85ca7ce658af67f95479a9aa72dae5cf1681 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Jul 2021 17:35:00 -0400 Subject: [PATCH] Eliminate reserved bits from TLB RAM --- wally-pipelined/src/mmu/tlbram.sv | 10 +++++----- wally-pipelined/src/mmu/tlbramline.sv | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index 92c36553..71d47c23 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -36,13 +36,13 @@ module tlbram #(parameter TLB_ENTRIES = 8) ( output logic [TLB_ENTRIES-1:0] PTE_Gs ); - logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0]; - logic [`XLEN-1:0] PageTableEntry; + logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0]; + logic [`PPN_BITS+9:0] PageTableEntry; - // Generate a flop for every entry in the RAM - tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE, RamRead, PTE_Gs); - + // RAM implemented with array of flops and AND/OR read logic + tlbramline #(`PPN_BITS+10) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE[`PPN_BITS+9:0], RamRead, PTE_Gs); assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE + // Rename the bits read from the TLB RAM assign PTEAccessBits = PageTableEntry[7:0]; assign PPN = PageTableEntry[`PPN_BITS+9:10]; endmodule diff --git a/wally-pipelined/src/mmu/tlbramline.sv b/wally-pipelined/src/mmu/tlbramline.sv index 089f9366..d6d2523c 100644 --- a/wally-pipelined/src/mmu/tlbramline.sv +++ b/wally-pipelined/src/mmu/tlbramline.sv @@ -34,7 +34,7 @@ module tlbramline #(parameter WIDTH) logic [WIDTH-1:0] line; - flopenr #(`XLEN) pteflop(clk, reset, we, d, line); + flopenr #(WIDTH) pteflop(clk, reset, we, d, line); assign q = re ? line : 0; assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching endmodule \ No newline at end of file