From 4e765ee1c5998ce42a08c1166a4647b80a3314f3 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 3 Jun 2021 10:03:09 -0400 Subject: [PATCH] expanded GPIO testing and caught small GPIO bug --- wally-pipelined/regression/wave-dos/peripheral-waves.do | 8 +++++++- wally-pipelined/src/uncore/gpio.sv | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do index a27caf29..5c9f3870 100644 --- a/wally-pipelined/regression/wave-dos/peripheral-waves.do +++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do @@ -41,15 +41,21 @@ add wave -hex /testbench/dut/hart/ifu/InstrM add wave -hex /testbench/dut/hart/ieu/c/InstrValidM add wave /testbench/InstrMName add wave /testbench/dut/uncore/dtim/memwrite +add wave -hex /testbench/dut/hart/MemPAdrM +add wave -hex /testbench/dut/hart/WriteDataM add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA +add wave -hex /testbench/dut/uncore/HRDATA +add wave -hex /testbench/dut/hart/ebu/ReadDataM add wave -divider add wave -hex /testbench/PCW add wave -hex /testbench/InstrW add wave -hex /testbench/dut/hart/ieu/c/InstrValidW add wave /testbench/InstrWName -add wave /testbench/dut/hart/ieu/dp/RegWriteW +add wave -hex /testbench/dut/hart/ReadDataW add wave -hex /testbench/dut/hart/ieu/dp/ResultW +add wave -hex /testbench/dut/hart/ieu/dp/RegWriteW +add wave -hex /testbench/dut/hart/ieu/dp/WriteDataW add wave -hex /testbench/dut/hart/ieu/dp/RdW add wave -divider add wave -hex /testbench/dut/hart/priv/csr/TrapM diff --git a/wally-pipelined/src/uncore/gpio.sv b/wally-pipelined/src/uncore/gpio.sv index 887ff74f..bddec8e6 100644 --- a/wally-pipelined/src/uncore/gpio.sv +++ b/wally-pipelined/src/uncore/gpio.sv @@ -165,6 +165,6 @@ module gpio ( assign GPIOPinsOut = output_val; assign GPIOPinsEn = output_en; - assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ip),(high_ip & high_ie),(low_ip & low_ie)}; + assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)}; endmodule