From 3fbccbf1199757bece241e9495321e159e286abd Mon Sep 17 00:00:00 2001 From: cturek Date: Tue, 22 Nov 2022 22:22:26 +0000 Subject: [PATCH 1/2] Updated testbench/wave for fdivsqrt new start signals --- pipelined/regression/wave-fpu.do | 2 +- pipelined/testbench/testbench-fp.sv | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index a07aae6c..87545e31 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -8,7 +8,7 @@ add wave -noupdate /testbenchfp/Z add wave -noupdate /testbenchfp/Res add wave -noupdate /testbenchfp/Ans add wave -noupdate /testbenchfp/DivStart -add wave -noupdate /testbenchfp/DivBusy +add wave -noupdate /testbenchfp/FDivBusyE add wave -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/state add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 228bc88f..0d310089 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -82,7 +82,7 @@ module testbenchfp; logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [`DIVb:0] Quot; logic CvtResDenormUfE; - logic DivStart, DivBusy; + logic DivStart, FDivBusyE; logic reset = 1'b0; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; logic [`DURLEN-1:0] Dur; @@ -717,9 +717,9 @@ module testbenchfp; end if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), - .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), - .MDUE(1'b0), .W64E(1'b0), - .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), + .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), + .FDivStartE(DivStart), .IDivStartE(1'b0), .MDUE(1'b0), .W64E(1'b0), + .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp), .QmM(Quot), .DivDone); end @@ -879,7 +879,7 @@ always @(negedge clk) begin // check if result is correct // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) - // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin + // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; @@ -911,7 +911,7 @@ always @(negedge clk) begin $stop; end - if(~(DivBusy|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector + if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file From 7140642c93dd05f2c690da2551cf88b5f6ff0bdf Mon Sep 17 00:00:00 2001 From: cturek Date: Tue, 22 Nov 2022 22:22:59 +0000 Subject: [PATCH 2/2] Almost done with Int division --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 30 +++++++++---------- 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 9bb9117c..4d7eb312 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -85,7 +85,7 @@ module fdivsqrt( .FDivBusyE); fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, - .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), + .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .ForwardedSrcAE, .MDUE, .n, .ALTB, .m, .BZero, .As, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 174a5321..a7da0145 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,6 +38,7 @@ module fdivsqrtpostproc( input logic Firstun, input logic SqrtM, input logic SpecialCaseM, + input logic [`XLEN-1:0] ForwardedSrcAE, input logic RemOp, MDUE, ALTB, BZero, As, input logic [`DIVBLEN:0] n, m, output logic [`DIVb:0] QmM, @@ -52,7 +53,7 @@ module fdivsqrtpostproc( logic [`DIVBLEN:0] NormShift; logic [`DIVb:0] IntQuot, NormQuot; logic [`DIVb+3:0] IntRem, NormRem; - logic [`DIVb:0] PreResult, Result; + logic [`DIVb+3:0] PreResult, Result; // check for early termination on an exact result. If the result is not exact, the sticky should be set aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); @@ -84,32 +85,31 @@ module fdivsqrtpostproc( if (NegSticky) begin NormQuot = FirstUM; NormRem = W + RemD; - PostInc = 0; + PostInc = 0; end else begin NormQuot = FirstU; NormRem = W; - PostInc = 0; + PostInc = 0; end else if (NegSticky | weq0) begin NormQuot = FirstU; NormRem = W; - PostInc = 0; + PostInc = 0; end else begin NormQuot = FirstU; NormRem = W - RemD; - PostInc = 1; + PostInc = 1; end -/* always_comb if(ALTB) begin IntQuot = '0; - IntRem = ForwardedSrcAE; + IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE}; end else if (BZero) begin IntQuot = '1; - IntRem = ForwardedSrcAE; - end else if (EarlyTerm) begin + IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE}; + end else if (WZero) begin if (weq0) begin IntQuot = FirstU; IntRem = '0; @@ -121,22 +121,20 @@ module fdivsqrtpostproc( IntQuot = NormQuot; IntRem = NormRem; end - */ - /* always_comb if (RemOp) begin - NormShift = m + (`DIVBLEN)'(`DIVa); + NormShift = (m + (`DIVBLEN)'(`DIVa)); PreResult = IntRem; end else begin - NormShift = DIVb - (j << `LOGR); - PreResult = IntQuot; + NormShift = ((`DIVBLEN)'(`DIVb) - (n << `LOGR)); + PreResult = {3'b000, IntQuot}; end - */ + // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted - // assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp); + assign Result = ($signed(PreResult) >>> NormShift) + {{(`DIVb+3){1'b0}}, (PostInc & ~RemOp)}; assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;