diff --git a/riscv-coremark/coremark/core_list_join.c b/riscv-coremark/coremark/core_list_join.c
index b42c1234..e5dba39e 100644
--- a/riscv-coremark/coremark/core_list_join.c
+++ b/riscv-coremark/coremark/core_list_join.c
@@ -158,19 +158,22 @@ ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) {
 	list_head *finder, *remover;
 	list_data info;
 	ee_s16 i;
-
+	ee_printf("entered corebenchlist \n");
 	info.idx=finder_idx;
 	/* find <find_num> values in the list, and change the list each time (reverse and cache if value found) */
 	for (i=0; i<find_num; i++) {
+		ee_printf("for loop \n");
 		info.data16= (i & 0xff) ;
 		this_find=core_list_find(list,&info);
 		list=core_list_reverse(list);
 		if (this_find==NULL) {
 			missed++;
 			retval+=(list->next->info->data16 >> 8) & 1;
+			ee_printf("if statement \n");
 		}
 		else {
 			found++;
+			ee_printf("else statement \n");
 			if (this_find->info->data16 & 0x1) /* use found value */
 				retval+=(this_find->info->data16 >> 9) & 1;
 			/* and cache next item at the head of the list (if any) */
@@ -421,13 +424,20 @@ list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modifi
 	Found item, or NULL if not found.
 */
 list_head *core_list_find(list_head *list,list_data *info) {
+	ee_printf("entered core_list_find \n");
 	if (info->idx>=0) {
-		while (list && (list->info->idx != info->idx))
+		ee_printf("find if \n");
+		while (list && (list->info->idx != info->idx)){
 			list=list->next;
+			ee_printf("find while if \n");}
+		ee_printf("core_list_find end \n");
 		return list;
 	} else {
-		while (list && ((list->info->data16 & 0xff) != info->data16))
+		ee_printf("find else");
+		while (list && ((list->info->data16 & 0xff) != info->data16)){
 			list=list->next;
+			ee_printf("find while else \n");}
+		ee_printf("core list find end \n");
 		return list;
 	}
 }
@@ -446,6 +456,7 @@ list_head *core_list_find(list_head *list,list_data *info) {
 */
 
 list_head *core_list_reverse(list_head *list) {
+	ee_printf("entered core_list_reverse");
 	list_head *next=NULL, *tmp;
 	while (list) {
 		tmp=list->next;
@@ -453,6 +464,7 @@ list_head *core_list_reverse(list_head *list) {
 		next=list;
 		list=tmp;
 	}
+	ee_printf("core_list_reverse done");
 	return next;
 }
 /* Function: core_list_mergesort
@@ -481,20 +493,27 @@ list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res)
     ee_s32 insize, nmerges, psize, qsize, i;
 
     insize = 1;
-
+	char bufftwo[200];
     while (1) {
         p = list;
         list = NULL;
         tail = NULL;
 
         nmerges = 0;  /* count number of merges we do in this pass */
-
+		ehitoa(nmerges, bufftwo, 10);
+		ee_printf(" nmerges default value = %s done \n", bufftwo);
         while (p) {
             nmerges++;  /* there exists a merge to be done */
+			ehitoa(nmerges, bufftwo, 10);
+			ee_printf(" current nmerges = %s done \n", bufftwo);
             /* step `insize' places along from p */
             q = p;
             psize = 0;
+			ehitoa(insize, bufftwo, 10);
+			ee_printf(" insize = %s done \n", bufftwo);
             for (i = 0; i < insize; i++) {
+				ehitoa(i, bufftwo, 10);
+				ee_printf(" i = %s done \n", bufftwo);
                 psize++;
 			    q = q->next;
                 if (!q) break;
@@ -502,29 +521,37 @@ list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res)
 
             /* if q hasn't fallen off end, we have two lists to merge */
             qsize = insize;
+			ehitoa(qsize, bufftwo, 10);
+			ee_printf(" qsize = %s done \n", bufftwo);
 
             /* now we have two lists; merge them */
             while (psize > 0 || (qsize > 0 && q)) {
 
 				/* decide whether next element of merge comes from p or q */
 				if (psize == 0) {
+					ee_printf("if \n");
 				    /* p is empty; e must come from q. */
 				    e = q; q = q->next; qsize--;
 				} else if (qsize == 0 || !q) {
+					ee_printf("else if \n");
 				    /* q is empty; e must come from p. */
 				    e = p; p = p->next; psize--;
 				} else if (cmp(p->info,q->info,res) <= 0) {
+					ee_printf("else if 2 \n");
 				    /* First element of p is lower (or same); e must come from p. */
 				    e = p; p = p->next; psize--;
 				} else {
+					ee_printf("else \n");
 				    /* First element of q is lower; e must come from q. */
 				    e = q; q = q->next; qsize--;
 				}
 
 		        /* add the next element to the merged list */
 				if (tail) {
+					ee_printf("tail if \n");
 				    tail->next = e;
 				} else {
+					ee_printf("tail else \n");
 				    list = e;
 				}
 				tail = e;
@@ -542,6 +569,8 @@ list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res)
 
         /* Otherwise repeat, merging lists twice the size */
         insize *= 2;
+		ehitoa(insize, bufftwo, 10);
+		ee_printf(" insize2 = %s done \n", bufftwo);
     }
 #if COMPILER_REQUIRES_SORT_RETURN
 	return list;
diff --git a/riscv-coremark/coremark/core_main.c b/riscv-coremark/coremark/core_main.c
index e8a8439c..b2149a18 100644
--- a/riscv-coremark/coremark/core_main.c
+++ b/riscv-coremark/coremark/core_main.c
@@ -286,17 +286,17 @@ MAIN_RETURN_TYPE main(int argc, char *argv[]) {
 			results[i].err=0;
 			if ((results[i].execs & ID_LIST) && 
 				(results[i].crclist!=list_known_crc[known_id])) {
-				sendstring("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n,i,results[i].crclist,list_known_crc[known_id]");
+				ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n,i,results[i].crclist,list_known_crc[known_id]");
 				results[i].err++;
 			}
 			if ((results[i].execs & ID_MATRIX) &&
 				(results[i].crcmatrix!=matrix_known_crc[known_id])) {
-				sendstring("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n,i,results[i].crcmatrix,matrix_known_crc[known_id]");
+				ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n,i,results[i].crcmatrix,matrix_known_crc[known_id]");
 				results[i].err++;
 			}
 			if ((results[i].execs & ID_STATE) &&
 				(results[i].crcstate!=state_known_crc[known_id])) {
-				sendstring("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n,i,results[i].crcstate,state_known_crc[known_id]");
+				ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n,i,results[i].crcstate,state_known_crc[known_id]");
 				results[i].err++;
 			}
 			total_errors+=results[i].err;
@@ -305,64 +305,64 @@ MAIN_RETURN_TYPE main(int argc, char *argv[]) {
 	total_errors+=check_data_types();
 	/* and report results */
 	//ee_printf("CoreMark Size    : %lu\n", (long unsigned) results[0].size);
-	sendstring("CoreMark Size    : %lu\n, (long unsigned) results[0].size");
-	sendstring("Total ticks      : %lu\n, (long unsigned) total_time");
+	ee_printf("CoreMark Size    : %lu\n, (long unsigned) results[0].size");
+	ee_printf("Total ticks      : %lu\n, (long unsigned) total_time");
 #if HAS_FLOAT
-	sendstring("Total time (secs): %f\n,time_in_secs(total_time)");
+	ee_printf("Total time (secs): %f\n,time_in_secs(total_time)");
 	if (time_in_secs(total_time) > 0)
-		sendstring("Iterations/Sec   : %f\n,default_num_contexts*results[0].iterations/time_in_secs(total_time)");
+		ee_printf("Iterations/Sec   : %f\n,default_num_contexts*results[0].iterations/time_in_secs(total_time)");
 #else 
-	sendstring("Total time (secs): %d\n,time_in_secs(total_time)");
+	ee_printf("Total time (secs): %d\n,time_in_secs(total_time)");
 	if (time_in_secs(total_time) > 0)
-		sendstring("Iterations/Sec   : %d\n,default_num_contexts*results[0].iterations/time_in_secs(total_time)");
+		ee_printf("Iterations/Sec   : %d\n,default_num_contexts*results[0].iterations/time_in_secs(total_time)");
 #endif
 	if (time_in_secs(total_time) < 10) {
-		sendstring("ERROR! Must execute for at least 10 secs for a valid result!\n");
+		ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n");
 		total_errors++;
 	}
 
-	sendstring("Iterations       : %lu\n, (long unsigned) default_num_contexts*results[0].iterations");
-	sendstring("Compiler version : %s\n,COMPILER_VERSION");
-	sendstring("Compiler flags   : %s\n,COMPILER_FLAGS");
+	ee_printf("Iterations       : %lu\n, (long unsigned) default_num_contexts*results[0].iterations");
+	ee_printf("Compiler version : %s\n,COMPILER_VERSION");
+	ee_printf("Compiler flags   : %s\n,COMPILER_FLAGS");
 #if (MULTITHREAD>1)
-	sendstring("Parallel %s : %d\n,PARALLEL_METHOD,default_num_contexts");
+	ee_printf("Parallel %s : %d\n,PARALLEL_METHOD,default_num_contexts");
 #endif
-	sendstring("Memory location  : %s\n,MEM_LOCATION");
+	ee_printf("Memory location  : %s\n,MEM_LOCATION");
 	/* output for verification */
-	sendstring("seedcrc          : 0x%04x\n,seedcrc");
+	ee_printf("seedcrc          : 0x%04x\n,seedcrc");
 	if (results[0].execs & ID_LIST)
 		for (i=0 ; i<default_num_contexts; i++) 
-			sendstring("[%d]crclist       : 0x%04x\n,i,results[i].crclist");
+			ee_printf("[%d]crclist       : 0x%04x\n,i,results[i].crclist");
 	if (results[0].execs & ID_MATRIX) 
 		for (i=0 ; i<default_num_contexts; i++) 
-			sendstring("[%d]crcmatrix     : 0x%04x\n,i,results[i].crcmatrix");
+			ee_printf("[%d]crcmatrix     : 0x%04x\n,i,results[i].crcmatrix");
 	if (results[0].execs & ID_STATE)
 		for (i=0 ; i<default_num_contexts; i++) 
-			sendstring("[%d]crcstate      : 0x%04x\n,i,results[i].crcstate");
+			ee_printf("[%d]crcstate      : 0x%04x\n,i,results[i].crcstate");
 	for (i=0 ; i<default_num_contexts; i++) 
-		sendstring("[%d]crcfinal      : 0x%04x\n,i,results[i].crc");
+		ee_printf("[%d]crcfinal      : 0x%04x\n,i,results[i].crc");
 	if (total_errors==0) {
-		sendstring("Correct operation validated. See README.md for run and reporting rules.\n");
+		ee_printf("Correct operation validated. See README.md for run and reporting rules.\n");
 #if HAS_FLOAT
 		if (known_id==3) {
-			sendstring("CoreMark 1.0 : %f / %s %s,default_num_contexts*results[0].iterations/time_in_secs(total_time),COMPILER_VERSION,COMPILER_FLAGS");
+			ee_printf("CoreMark 1.0 : %f / %s %s,default_num_contexts*results[0].iterations/time_in_secs(total_time),COMPILER_VERSION,COMPILER_FLAGS");
 #if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
-			sendstring(" / %s,MEM_LOCATION");
+			ee_printf(" / %s,MEM_LOCATION");
 #else
-			sendstring(" / %s,mem_name[MEM_METHOD]");
+			ee_printf(" / %s,mem_name[MEM_METHOD]");
 #endif
 
 #if (MULTITHREAD>1)
-			sendstring(" / %d:%s,default_num_contexts,PARALLEL_METHOD");
+			ee_printf(" / %d:%s,default_num_contexts,PARALLEL_METHOD");
 #endif
-			sendstring("\n");
+			ee_printf("\n");
 		}
 #endif
 	}
 	if (total_errors>0)
-		sendstring("Errors detected\n");
+		ee_printf("Errors detected\n");
 	if (total_errors<0)
-		sendstring("Cannot validate operation for these seed values, please compare with results on a known platform.\n");
+		ee_printf("Cannot validate operation for these seed values, please compare with results on a known platform.\n");
 
 #if (MEM_METHOD==MEM_MALLOC)
 	for (i=0 ; i<MULTITHREAD; i++) 
diff --git a/riscv-coremark/trace b/riscv-coremark/trace
new file mode 100644
index 00000000..7c76d0bf
--- /dev/null
+++ b/riscv-coremark/trace
@@ -0,0 +1,48 @@
+Imperas riscvOVPsimPlus
+
+
+riscvOVPsimPlus (64-Bit) v20210329.0 Open Virtual Platform simulator from www.IMPERAS.com.
+Copyright (c) 2005-2021 Imperas Software Ltd.  Contains Imperas Proprietary Information.
+Licensed Software, All Rights Reserved.
+Visit www.IMPERAS.com for multicore debug, verification and analysis solutions.
+
+riscvOVPsimPlus started: Wed May 12 17:55:33 2021
+
+
+Info (GDBT_PORT) Host: Tera.Eng.HMC.Edu, Port: 55460
+Info (DBC_LGDB) Starting Debugger /cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscv-none-embed-gdb
+Info (GDBT_WAIT) Waiting for remote debugger to connect...
+Info (OR_OF) Target 'riscvOVPsim/cpu' has object file read from 'coremark.bare.riscv'
+Info (OR_PH) Program Headers:
+Info (OR_PH) Type           Offset             VirtAddr           PhysAddr
+Info (OR_PH)                FileSiz            MemSiz             Flags  Align
+Info (OR_PD) LOAD           0x0000000000001000 0x0000000080000000 0x0000000080000000
+Info (OR_PD)                0x0000000000000204 0x0000000000000204 R-E    1000
+Info (OR_PD) LOAD           0x0000000000002000 0x0000000080001000 0x0000000080001000
+Info (OR_PD)                0x00000000000047e0 0x0000000000004ff0 RWE    1000
+Info (GDBT_CONNECTED) Client connected
+Info (GDBT_GON) Client disappeared 'riscvOVPsim/cpu'
+Info 
+Info ---------------------------------------------------
+Info CPU 'riscvOVPsim/cpu' STATISTICS
+Info   Type                  : riscv (RV64GC)
+Info   Nominal MIPS          : 100
+Info   Final program counter : 0x80003558
+Info   Simulated instructions: 1,455,608
+Info   Simulated MIPS        : 0.0
+Info ---------------------------------------------------
+Info 
+Info ---------------------------------------------------
+Info SIMULATION TIME STATISTICS
+Info   Simulated time        : 0.02 seconds
+Info   User time             : 99.23 seconds
+Info   System time           : 254.08 seconds
+Info   Elapsed time          : 1107.49 seconds
+Info ---------------------------------------------------
+
+riscvOVPsimPlus finished: Wed May 12 18:14:04 2021
+
+
+riscvOVPsimPlus (64-Bit) v20210329.0 Open Virtual Platform simulator from www.IMPERAS.com.
+Visit www.IMPERAS.com for multicore debug, verification and analysis solutions.
+
diff --git a/wally-pipelined/regression/sim-wally-batch-muldiv b/wally-pipelined/regression/sim-wally-batch-muldiv
index c9db7ed1..2c8089ef 100755
--- a/wally-pipelined/regression/sim-wally-batch-muldiv
+++ b/wally-pipelined/regression/sim-wally-batch-muldiv
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do ../config/rv64imc rv64imc
+do wally-pipelined-batch-muldiv.do ../config/rv64imc rv64imc
 !
diff --git a/wally-pipelined/regression/sim-wally-muldiv b/wally-pipelined/regression/sim-wally-muldiv
new file mode 100755
index 00000000..5eea3381
--- /dev/null
+++ b/wally-pipelined/regression/sim-wally-muldiv
@@ -0,0 +1 @@
+vsim -do wally-pipelined-muldiv.do
diff --git a/wally-pipelined/regression/udiv.c b/wally-pipelined/regression/udiv.c
new file mode 100644
index 00000000..2ebb7355
--- /dev/null
+++ b/wally-pipelined/regression/udiv.c
@@ -0,0 +1,22 @@
+#include <stdio.h>
+#include <math.h>
+#include <inttypes.h>
+
+int main() {
+
+  uint64_t N;
+  uint64_t D;
+  uint64_t Q;
+
+  D = 0xdf7f3844121bcc23;
+  N = 0x10fd3dedadea5195;
+  Q = N/D;
+
+  printf("N = %" PRIx64 "\n", N);
+  printf("D = %" PRIx64 "\n", D);
+  printf("Q = %" PRIx64 "\n", Q);
+  printf("R = %" PRIx64 "\n", N%D);  
+
+
+
+}
diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do
deleted file mode 100644
index 5a309b78..00000000
--- a/wally-pipelined/regression/wally-coremark.do
+++ /dev/null
@@ -1,115 +0,0 @@
-# wally-coremark.do 
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# Use this wally-coremark.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-coremark.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-coremark.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# default to config/coremark, but allow this to be overridden at the command line.  For example:
-vlog +incdir+../config/coremark ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt +acc work.testbench -o workopt 
-vsim workopt
-
-view wave
-
--- display input and output signals as hexidecimal values
-# Diplays All Signals recursively
-add wave /testbench/clk
-add wave /testbench/reset
-add wave -divider
-#add wave /testbench/dut/hart/ebu/IReadF
-#add wave /testbench/dut/hart/DataStall
-#add wave /testbench/dut/hart/InstrStall
-#add wave /testbench/dut/hart/StallF
-#add wave /testbench/dut/hart/StallD
-#add wave /testbench/dut/hart/FlushD
-#add wave /testbench/dut/hart/FlushE
-#add wave /testbench/dut/hart/FlushM
-#add wave /testbench/dut/hart/FlushW
-
-add wave -divider Fetch
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/InstrF
-add wave /testbench/InstrFName
-add wave -divider Decode
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
-add wave /testbench/InstrDName
-add wave -divider Execute
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
-add wave /testbench/InstrEName
-add wave -divider Memory
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
-add wave /testbench/InstrMName
-add wave -divider Write
-add wave -hex /testbench/PCW
-add wave -hex /testbench/InstrW
-add wave /testbench/InstrWName
-#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
-add wave -divider Regfile_signals
-#add wave /testbench/dut/uncore/dtim/memwrite
-#add wave -hex /testbench/dut/uncore/HADDR
-#add wave -hex /testbench/dut/uncore/HWDATA
-#add wave -divider
-#add wave -hex /testbench/PCW
-#add wave /testbench/InstrWName
-#add wave /testbench/dut/hart/ieu/dp/RegWriteW
-#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-#add wave -hex /testbench/dut/hart/ieu/dp/RdW
-add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
-add wave -divider Regfile_itself
-add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
-add wave -divider RAM
-add wave -hex -r /testbench/dut/uncore/dtim/RAM
-add wave -divider Misc
-add wave -divider
-#add wave -hex -r /testbench/*
-
--- Set Wave Output Items 
-TreeUpdate [SetDefaultTree]
-WaveRestoreZoom {0 ps} {100 ps}
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 120
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-set DefaultRadix hexadecimal
-
--- Run the Simulation 
-#run 7402000
-#run 10500
-run -all
-#quit
diff --git a/wally-pipelined/regression/wally-pipelined-batch-muldiv.do b/wally-pipelined/regression/wally-pipelined-batch-muldiv.do
index 5e1410b9..47d9d812 100644
--- a/wally-pipelined/regression/wally-pipelined-batch-muldiv.do
+++ b/wally-pipelined/regression/wally-pipelined-batch-muldiv.do
@@ -30,9 +30,9 @@ vlib work_$2
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined-batch.do ../config/rv32ic rv32ic
 switch $argc {
-    0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
-    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv  ../src/*/*.sv -suppress 2583}
-    2 {vlog -work work_$2 +incdir+$1 ../testbench/testbench-imperas.sv  ../src/*/*.sv -suppress 2583}
+    0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1 ../testbench/testbench-imperas-div.sv  ../src/*/*.sv -suppress 2583}
+    2 {vlog -work work_$2 +incdir+$1 ../testbench/testbench-imperas-div.sv  ../src/*/*.sv -suppress 2583}
 }
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-muldiv.do b/wally-pipelined/regression/wally-pipelined-muldiv.do
index b897e027..8c55956b 100644
--- a/wally-pipelined/regression/wally-pipelined-muldiv.do
+++ b/wally-pipelined/regression/wally-pipelined-muldiv.do
@@ -30,15 +30,14 @@ vlib work
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined.do ../config/rv32ic
 switch $argc {
-    0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
-    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+    0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1 ../testbench/testbench-imperas-div.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
 }
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 vopt +acc work.testbench -o workopt 
 vsim workopt
 
-
 view wave
 
 -- display input and output signals as hexidecimal values
@@ -47,8 +46,8 @@ do ./wave-dos/ahb-muldiv.do
 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
 WaveRestoreZoom {0 ps} {100 ps}
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 140
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 240
 configure wave -justifyvalue left
 configure wave -signalnamewidth 0
 configure wave -snapdistance 10
diff --git a/wally-pipelined/regression/wave-dos/ahb-muldiv.do b/wally-pipelined/regression/wave-dos/ahb-muldiv.do
index 68d2a213..dedf0ba5 100644
--- a/wally-pipelined/regression/wave-dos/ahb-muldiv.do
+++ b/wally-pipelined/regression/wave-dos/ahb-muldiv.do
@@ -6,12 +6,13 @@ add wave /testbench/clk
 add wave /testbench/reset
 add wave -divider
 
+# new
 #add wave /testbench/dut/hart/ebu/IReadF
-add wave -noupdate -divider -height 32 "Stalls"
 add wave /testbench/dut/hart/DataStall
-add wave /testbench/dut/hart/InstrStall
+add wave /testbench/dut/hart/ICacheStallF
 add wave /testbench/dut/hart/StallF
 add wave /testbench/dut/hart/StallD
+
 add wave /testbench/dut/hart/StallE
 add wave /testbench/dut/hart/StallM
 add wave /testbench/dut/hart/StallW
@@ -28,27 +29,15 @@ add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
 add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/NEXT_STATE
 add wave -hex /testbench/dut/hart/mdu/genblk1/div/*
 
-
-
 add wave -noupdate -divider -height 32 "RF"
 add wave -hex /testbench/dut/hart/ieu/dp/regf/*
 add wave -hex /testbench/dut/hart/ieu/dp/regf/rf
 
-
 add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCF
 add wave -hex /testbench/dut/hart/ifu/PCD
 add wave -hex /testbench/dut/hart/ifu/InstrD
-
 add wave /testbench/InstrDName
-add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD
-add wave -hex /testbench/dut/hart/ifu/ic/AlignedInstrD
-add wave -divider
-add wave -hex /testbench/dut/hart/ifu/ic/InstrPAdrF
-add wave /testbench/dut/hart/ifu/ic/DelayF
-add wave /testbench/dut/hart/ifu/ic/DelaySideF
-add wave /testbench/dut/hart/ifu/ic/DelayD
-add wave -hex /testbench/dut/hart/ifu/ic/MisalignedHalfInstrD
 add wave -divider
 
 add wave -hex /testbench/dut/hart/ifu/PCE
@@ -79,7 +68,6 @@ add wave -hex /testbench/dut/hart/ebu/HRDATA
 add wave -hex /testbench/dut/hart/ebu/HWRITE
 add wave -hex /testbench/dut/hart/ebu/HWDATA
 add wave -hex /testbench/dut/hart/ebu/CaptureDataM
-add wave -hex /testbench/dut/hart/ebu/InstrStall
 add wave -divider
 
 add wave -hex /testbench/dut/uncore/dtim/*
@@ -97,17 +85,15 @@ add wave -divider
 add wave -hex /testbench/dut/uncore/dtim/*
 add wave -divider
 
-add wave -hex -r /testbench/*
-
 # appearance
 TreeUpdate [SetDefaultTree]
 WaveRestoreZoom {0 ps} {100 ps}
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 150
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 250
 configure wave -justifyvalue left
 configure wave -signalnamewidth 0
 configure wave -snapdistance 10
 configure wave -datasetprefix 0
 configure wave -rowmargin 4
 configure wave -childrowmargin 2
-set DefaultRadix hexadecimal
\ No newline at end of file
+set DefaultRadix hexadecimal
diff --git a/wally-pipelined/regression/wave-dos/ahb-waves.do b/wally-pipelined/regression/wave-dos/ahb-waves.do
index 48b89b6b..add1ab22 100644
--- a/wally-pipelined/regression/wave-dos/ahb-waves.do
+++ b/wally-pipelined/regression/wave-dos/ahb-waves.do
@@ -86,4 +86,4 @@ configure wave -snapdistance 10
 configure wave -datasetprefix 0
 configure wave -rowmargin 4
 configure wave -childrowmargin 2
-set DefaultRadix hexadecimal
\ No newline at end of file
+set DefaultRadix hexadecimal
diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv
index 4040fdc3..f1145780 100755
--- a/wally-pipelined/src/muldiv/div.sv
+++ b/wally-pipelined/src/muldiv/div.sv
@@ -29,16 +29,17 @@
 /* verilator lint_off COMBDLY */
 /* verilator lint_off IMPLICIT */
 
+`include "wally-config.vh"
 
-module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);
+module div (Qf, remf, done, divBusy, div0, N, D, clk, reset, start);
 
    input logic [63:0]  N, D;
    input logic 	       clk;
    input logic 	       reset;
    input logic 	       start;
    
-   output logic [63:0] Q;
-   output logic [63:0] rem0;
+   output logic [63:0] Qf;
+   output logic [63:0] remf;
    output logic        div0;
    output logic        done;
    output logic        divBusy;   
@@ -51,10 +52,11 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);
    logic [5:0] 	       P, NumIter, RemShift;
    logic [63:0]        op1, op2, op1shift, Rem5;
    logic [64:0]        Qd, Rd, Qd2, Rd2;
+   logic [63:0]        Q, rem0;
    logic [3:0] 	       quotient;
    logic 	       otfzero; 
    logic 	       shiftResult;
-   logic           enablev, state0v, donev, divdonev, oftzerov, divBusyv, ulp;
+   logic 	       enablev, state0v, donev, divdonev, oftzerov, divBusyv, ulp;
 
    // Divider goes the distance to 37 cycles
    // (thanks the evil divisor for D = 0x1) 
@@ -112,9 +114,6 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);
    // shifting N right by v+s so that (m+v+s) mod k = 0.  And,
    // the quotient has to be aligned to the integer position.
 
-   // Used a Brent-Kung for no reason (just wanted prefix -- might
-   // have gotten away with a RCA)
-   
    // Actual divider unit FIXME: r16 (jes)
    divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, 
 		  enable, otfzero, shiftResult);
@@ -131,6 +130,10 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);
    // n ln(r)
    shifter_r64 p4 (rem0, Rem5, RemShift);
 
+   // RISC-V has exceptions for divide by 0 (Table 6.1 of SPEC)
+   mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf);
+   mux2 #(64) exc2 (rem0, op1, div0, remf);   
+
 endmodule // int32div
 
 module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, 
@@ -1562,5 +1565,50 @@ module shifter_r32 (Z, A, Shift);
    
 endmodule // shifter_r32
 
+module shift_right #(parameter WIDTH=8) 
+   (input logic [`XLEN-1:0]         A,
+    input logic [$clog2(`XLEN)-1:0] Shift,
+    output logic [`XLEN-1:0] 	    Z);
+   
+   logic [`XLEN-1:0] 							 stage [$clog2(`XLEN):0];
+   genvar 								 i;
+   
+   assign stage[0] = A;   
+   generate
+      for (i=0;i<$clog2(`XLEN);i=i+1)
+	begin : genbit
+	   mux2 #(`XLEN) mux_inst (stage[i], 
+				   {{(`XLEN/(2**(i+1))){1'b0}}, stage[i][`XLEN-1:`XLEN/(2**(i+1))]}, 
+				   Shift[$clog2(`XLEN)-i-1], 
+				   stage[i+1]);
+	end
+   endgenerate
+   assign Z = stage[$clog2(`XLEN)];   
+
+endmodule // shift_right
+
+module shift_left #(parameter WIDTH=8) 
+   (input logic [`XLEN-1:0]         A,
+    input logic [$clog2(`XLEN)-1:0] Shift,
+    output logic [`XLEN-1:0] 	    Z);
+   
+   logic [`XLEN-1:0] 							stage [$clog2(`XLEN):0];
+   genvar 								i;
+   
+   assign stage[0] = A;   
+   generate
+      for (i=0;i<$clog2(`XLEN);i=i+1)
+	begin : genbit
+	   mux2 #(`XLEN) mux_inst (stage[i], 
+				   {stage[i][`XLEN-1-`XLEN/(2**(i+1)):0], {(`XLEN/(2**(i+1))){1'b0}}}, 
+				   Shift[$clog2(`XLEN)-i-1], 
+				   stage[i+1]);
+	end
+   endgenerate
+   assign Z = stage[$clog2(`XLEN)];   
+
+endmodule // shift_right
+
 /* verilator lint_on COMBDLY */
 /* verilator lint_on IMPLICIT */
+
diff --git a/wally-pipelined/src/muldiv/div/div b/wally-pipelined/src/muldiv/div/div
index 35202318..e0bbf726 100755
Binary files a/wally-pipelined/src/muldiv/div/div and b/wally-pipelined/src/muldiv/div/div differ
diff --git a/wally-pipelined/src/muldiv/div/div.c b/wally-pipelined/src/muldiv/div/div.c
index e7605375..53bbc2a8 100644
--- a/wally-pipelined/src/muldiv/div/div.c
+++ b/wally-pipelined/src/muldiv/div/div.c
@@ -7,19 +7,30 @@ int main() {
   uint64_t N;
   uint64_t D;
   uint64_t Q;
+  double val;
+  uint64_t val2;
 
-  //N = 0xc9649f05a8e1a8bb;
-  //D = 0x82f6747f707af2c0;
-  //N = 0x10fd3dedadea5195;
-  //D = 0xdf7f3844121bcc23;
-  N = 0x4;
-  D = 0xbfffffffffffffff;
-  Q = N/D;
+  int exponent;
+  int base;
+
+  base = 2;
+  exponent = 32;
+  val2 = 1;
+  while (exponent != 0) {
+    val2 *= base;
+    exponent --;
+  }
+  
+  val = pow(2.0, 64) - 1;
+  N = 0xdf7f3844121bcc23;
+  D = 0x10fd3dedadea5195;
 
   printf("N = %" PRIx64 "\n", N);
   printf("D = %" PRIx64 "\n", D);
   printf("Q = %" PRIx64 "\n", Q);
-  printf("R = %" PRIx64 "\n", N%D);  
+  printf("R = %" PRIx64 "\n", N%D);
+
+  printf("val = %" PRIx64 "\n", val2-1);  
 
 
 
diff --git a/wally-pipelined/src/muldiv/div/div64.out b/wally-pipelined/src/muldiv/div/div64.out
index 4c731592..6bfa9dd9 100644
--- a/wally-pipelined/src/muldiv/div/div64.out
+++ b/wally-pipelined/src/muldiv/div/div64.out
@@ -1,67 +1,107 @@
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
-10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
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+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0
diff --git a/wally-pipelined/src/muldiv/div/divide4x64.sv b/wally-pipelined/src/muldiv/div/divide4x64.sv
index 2f56f0eb..4b474c65 100755
--- a/wally-pipelined/src/muldiv/div/divide4x64.sv
+++ b/wally-pipelined/src/muldiv/div/divide4x64.sv
@@ -1,12 +1,12 @@
-module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
+module int64div (Qf, done, divdone, remf, div0, N, D, clk, reset, start);
 
    input logic [63:0]  N, D;
    input logic 	       clk;
    input logic 	       reset;
    input logic 	       start;
    
-   output logic [63:0] Q;
-   output logic [63:0] rem0;
+   output logic [63:0] Qf;
+   output logic [63:0] remf;
    output logic        div0;
    output logic        done;
    output logic        divdone;   
@@ -18,6 +18,7 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
    logic [5:0] 	       P, NumIter, RemShift;
    logic [63:0]        op1, op2, op1shift, Rem5;
    logic [64:0]        Qd, Rd, Qd2, Rd2;
+   logic [63:0]        Q, rem0;
    logic [3:0] 	       quotient;
    logic 	       otfzero; 
    logic 	       shiftResult;  
@@ -80,9 +81,6 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
    // shifting N right by v+s so that (m+v+s) mod k = 0.  And,
    // the quotient has to be aligned to the integer position.
 
-   // Used a Brent-Kung for no reason (just wanted prefix -- might
-   // have gotten away with a RCA)
-   
    // Actual divider unit FIXME: r16 (jes)
    divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, 
 		  enable, otfzero, shiftResult);
@@ -96,9 +94,13 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
    assign Rem5 = Rd2[64:1];  
    
    // Adjust remainder by m (no need to adjust by
-   // n ln(r)
+   // n lg(r)
    shifter_r64 p4 (rem0, Rem5, RemShift);
 
+   // RISC-V has exceptions for divide by 0 (see Table 6.1 of spec)
+   mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf);
+   mux2 #(64) exc2 (rem0, op1, div0, remf);
+
 endmodule // int32div
 
 module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, 
@@ -252,7 +254,7 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
    endgenerate
    assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0};     
 
-endmodule // adder
+endmodule // csa
 
 module flopenr #(parameter WIDTH = 8) 
    (input logic clk, reset, en,
diff --git a/wally-pipelined/src/muldiv/div/imperas-riscv-tests b/wally-pipelined/src/muldiv/div/imperas-riscv-tests
new file mode 160000
index 00000000..c171bf19
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/imperas-riscv-tests
@@ -0,0 +1 @@
+Subproject commit c171bf1999a3cf7e8cd26511dfcf794d1498e5a1
diff --git a/wally-pipelined/src/muldiv/div/int64div.do b/wally-pipelined/src/muldiv/div/int64div.do
index 4e01c687..dc83d046 100755
--- a/wally-pipelined/src/muldiv/div/int64div.do
+++ b/wally-pipelined/src/muldiv/div/int64div.do
@@ -70,6 +70,8 @@ add wave -hex /tb/dut/N
 add wave -hex /tb/dut/D
 add wave -hex /tb/dut/reset
 add wave -hex /tb/dut/start
+add wave -hex /tb/dut/Qf
+add wave -hex /tb/dut/remf
 add wave -hex /tb/dut/Q
 add wave -hex /tb/dut/rem0
 add wave -hex /tb/dut/div0
@@ -99,8 +101,8 @@ add wave -hex -r /tb/dut/p3/*
 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
 WaveRestoreZoom {0 ps} {75 ns}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 200
 configure wave -justifyvalue left
 configure wave -signalnamewidth 0
 configure wave -snapdistance 10
@@ -109,6 +111,6 @@ configure wave -rowmargin 4
 configure wave -childrowmargin 2
 
 -- Run the Simulation
-run 338ns
+run 538ns
 
 
diff --git a/wally-pipelined/src/muldiv/div/shift.sv b/wally-pipelined/src/muldiv/div/shift.sv
new file mode 100644
index 00000000..412cee32
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift.sv
@@ -0,0 +1,151 @@
+module shifter_l64 (Z, A, Shift);
+
+   input logic [63:0]  A;
+   input logic [5:0]   Shift;
+   
+   logic [63:0]        stage1;
+   logic [63:0]        stage2;
+   logic [63:0]        stage3;
+   logic [63:0]        stage4;
+   logic [63:0]        stage5;   
+   logic [31:0]        thirtytwozeros = 32'h0;
+   logic [15:0]        sixteenzeros = 16'h0;
+   logic [ 7:0]        eightzeros = 8'h0;
+   logic [ 3:0]        fourzeros = 4'h0;
+   logic [ 1:0]        twozeros = 2'b00;
+   logic 	       onezero = 1'b0;   
+   
+   output logic [63:0] Z;      
+   
+   mux2 #(64) mx01(A,      {A[31:0], thirtytwozeros}, Shift[5], stage1);   
+   mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2);
+   mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3);
+   mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4);
+   mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5);
+   mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z);
+
+endmodule // shifter_l64
+
+module shifter_r64 (Z, A, Shift);
+
+   input logic [63:0]  A;
+   input logic [5:0]   Shift;
+   
+   logic [63:0]        stage1;
+   logic [63:0]        stage2;
+   logic [63:0]        stage3;
+   logic [63:0]        stage4;
+   logic [63:0]        stage5;   		  
+   logic [31:0]        thirtytwozeros = 32'h0;		  
+   logic [15:0]        sixteenzeros = 16'h0;
+   logic [ 7:0]        eightzeros = 8'h0;
+   logic [ 3:0]        fourzeros = 4'h0;
+   logic [ 1:0]        twozeros = 2'b00;
+   logic 	       onezero = 1'b0;   
+   
+   output logic [63:0] Z;
+   
+   mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1);		  
+   mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2);
+   mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3);
+   mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4);
+   mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5);
+   mux2 #(64) mx06(stage5, {onezero, stage5[63:1]},  Shift[0], Z);
+   
+endmodule // shifter_r64
+
+module shifter_l32 (Z, A, Shift);
+
+   input logic [31:0]  A;
+   input logic [4:0]   Shift;
+   
+   logic [31:0]        stage1;
+   logic [31:0]        stage2;
+   logic [31:0]        stage3;
+   logic [31:0]        stage4;
+   logic [15:0]        sixteenzeros = 16'h0;
+   logic [ 7:0]        eightzeros = 8'h0;
+   logic [ 3:0]        fourzeros = 4'h0;
+   logic [ 1:0]        twozeros = 2'b00;
+   logic 	       onezero = 1'b0;   
+   
+   output logic [31:0] Z;      
+
+   mux2 #(32) mx01(A,      {A[15:0], sixteenzeros},    Shift[4], stage1);
+   mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2);
+   mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros},  Shift[2], stage3);
+   mux2 #(32) mx04(stage3, {stage3[29:0], twozeros},   Shift[1], stage4);
+   mux2 #(32) mx05(stage4, {stage4[30:0], onezero},    Shift[0], Z);
+
+endmodule // shifter_l32
+
+module shifter_r32 (Z, A, Shift);
+
+   input logic [31:0]  A;
+   input logic [4:0]   Shift;
+   
+   logic [31:0]        stage1;
+   logic [31:0]        stage2;
+   logic [31:0]        stage3;
+   logic [31:0]        stage4;
+   logic [15:0]        sixteenzeros = 16'h0;
+   logic [ 7:0]        eightzeros = 8'h0;
+   logic [ 3:0]        fourzeros = 4'h0;
+   logic [ 1:0]        twozeros = 2'b00;
+   logic 	       onezero = 1'b0;   
+   
+   output logic [31:0] Z;
+   
+   mux2 #(32) mx01(A,      {sixteenzeros, A[31:16]},   Shift[4], stage1);
+   mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2);
+   mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]},  Shift[2], stage3);
+   mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]},   Shift[1], stage4);
+   mux2 #(32) mx05(stage4, {onezero, stage4[31:1]},    Shift[0], Z);
+   
+endmodule // shifter_r32
+
+`define XLEN 32
+module shift_right #(parameter WIDTH=8) (input logic [`XLEN-1:0]         A,
+					 input logic [$clog2(`XLEN)-1:0] Shift,
+					 output logic [`XLEN-1:0] 	 Z);
+   
+   logic [`XLEN-1:0] 							 stage [$clog2(`XLEN):0];
+   genvar 								 i;
+   
+   assign stage[0] = A;   
+   generate
+      for (i=0;i<$clog2(`XLEN);i=i+1)
+	begin : genbit
+	   mux2 #(`XLEN) mux_inst (stage[i], 
+				   {{(`XLEN/(2**(i+1))){1'b0}}, stage[i][`XLEN-1:`XLEN/(2**(i+1))]}, 
+				   Shift[$clog2(`XLEN)-i-1], 
+				   stage[i+1]);
+	end
+   endgenerate
+   assign Z = stage[$clog2(`XLEN)];   
+
+endmodule // shift_right
+
+module shift_left #(parameter WIDTH=8) (input logic [`XLEN-1:0]         A,
+					input logic [$clog2(`XLEN)-1:0] Shift,
+					output logic [`XLEN-1:0] 	Z);
+   
+   logic [`XLEN-1:0] 							stage [$clog2(`XLEN):0];
+   genvar 								i;
+   
+   assign stage[0] = A;   
+   generate
+      for (i=0;i<$clog2(`XLEN);i=i+1)
+	begin : genbit
+	   mux2 #(`XLEN) mux_inst (stage[i], 
+				   {stage[i][`XLEN-1-`XLEN/(2**(i+1)):0], {(`XLEN/(2**(i+1))){1'b0}}}, 
+				   Shift[$clog2(`XLEN)-i-1], 
+				   stage[i+1]);
+	end
+   endgenerate
+   assign Z = stage[$clog2(`XLEN)];   
+
+endmodule // shift_right
+
+
+
diff --git a/wally-pipelined/src/muldiv/div/shift_left.do b/wally-pipelined/src/muldiv/div/shift_left.do
new file mode 100755
index 00000000..0b0ce985
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift_left.do
@@ -0,0 +1,55 @@
+# Copyright 1991-2016 Mentor Graphics Corporation
+# 
+# Modification by Oklahoma State University
+# Use with Testbench 
+# James Stine, 2008
+# Go Cowboys!!!!!!
+#
+# All Rights Reserved.
+#
+# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
+# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
+# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+
+# Use this run.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do run.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do run.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+vlog mux_div.sv shift.sv shift_left_tb.sv
+
+# start and run simulation
+vsim -voptargs=+acc work.stimulus
+
+view wave
+
+-- display input and output signals as hexidecimal values
+# Diplays All Signals recursively
+add wave -hex -r /stimulus/*
+
+-- Set Wave Output Items 
+TreeUpdate [SetDefaultTree]
+WaveRestoreZoom {0 ps} {75 ns}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+
+-- Run the Simulation 
+run 800ns
+quit
diff --git a/wally-pipelined/src/muldiv/div/shift_left.out b/wally-pipelined/src/muldiv/div/shift_left.out
new file mode 100644
index 00000000..67fedc18
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift_left.out
@@ -0,0 +1,79 @@
+12153524 01 || 242a6a48 242a6a48 | 1
+8484d609 03 || 2426b048 2426b048 | 1
+06b97b0d 0d || 2f61a000 2f61a000 | 1
+b2c28465 12 || 11940000 11940000 | 1
+00f3e301 0d || 7c602000 7c602000 | 1
+3b23f176 1d || c0000000 c0000000 | 1
+76d457ed 0c || 457ed000 457ed000 | 1
+7cfde9f9 06 || 3f7a7e40 3f7a7e40 | 1
+e2f784c5 0a || de131400 de131400 | 1
+72aff7e5 17 || f2800000 f2800000 | 1
+8932d612 0f || 6b090000 6b090000 | 1
+793069f2 0e || 1a7c8000 1a7c8000 | 1
+f4007ae8 05 || 800f5d00 800f5d00 | 1
+2e58495c 1d || 80000000 80000000 | 1
+96ab582d 05 || d56b05a0 d56b05a0 | 1
+b1ef6263 0a || bd898c00 bd898c00 | 1
+c03b2280 00 || c03b2280 c03b2280 | 1
+557845aa 1d || 40000000 40000000 | 1
+cb203e96 13 || f4b00000 f4b00000 | 1
+86bc380d 13 || c0680000 c0680000 | 1
+359fdd6b 15 || ad600000 ad600000 | 1
+81174a02 0e || d2808000 d2808000 | 1
+0effe91d 0f || f48e8000 f48e8000 | 1
+11844923 0a || 11248c00 11248c00 | 1
+e5730aca 1c || a0000000 a0000000 | 1
+7968bdf2 0a || a2f7c800 a2f7c800 | 1
+20c4b341 18 || 41000000 41000000 | 1
+3c20f378 09 || 41e6f000 41e6f000 | 1
+75c50deb 16 || 7ac00000 7ac00000 | 1
+634bf9c6 0e || fe718000 fe718000 | 1
+de7502bc 0a || d40af000 d40af000 | 1
+85d79a0b 11 || 34160000 34160000 | 1
+42f24185 0f || 20c28000 20c28000 | 1
+9dcc603b 1a || ec000000 ec000000 | 1
+bf23327e 15 || 4fc00000 4fc00000 | 1
+78d99bf1 19 || e2000000 e2000000 | 1
+31230762 0c || 30762000 30762000 | 1
+4fa1559f 0f || aacf8000 aacf8000 | 1
+7c6da9f8 17 || fc000000 fc000000 | 1
+cfc4569f 1c || f0000000 f0000000 | 1
+adcbc05b 09 || 9780b600 9780b600 | 1
+a4ae3249 10 || 32490000 32490000 | 1
+ebfec0d7 11 || 81ae0000 81ae0000 | 1
+4b212f96 0c || 12f96000 12f96000 | 1
+e12ccec2 08 || 2ccec200 2ccec200 | 1
+bb825a77 1d || e0000000 e0000000 | 1
+090cdb12 1e || 80000000 80000000 | 1
+36e5816d 19 || da000000 da000000 | 1
+0fd28f1f 13 || 78f80000 78f80000 | 1
+42d92f85 18 || 85000000 85000000 | 1
+2dda595b 09 || b4b2b600 b4b2b600 | 1
+9ff2ae3f 0a || cab8fc00 cab8fc00 | 1
+2c156358 06 || 0558d600 0558d600 | 1
+c71a0c8e 1c || e0000000 e0000000 | 1
+7d3599fa 06 || 4d667e80 4d667e80 | 1
+39961773 03 || ccb0bb98 ccb0bb98 | 1
+9799a82f 13 || 41780000 41780000 | 1
+afd8565f 04 || fd8565f0 fd8565f0 | 1
+7bf8fdf7 0b || c7efb800 c7efb800 | 1
+f3091ae6 1a || 98000000 98000000 | 1
+14cfc129 0d || f8252000 f8252000 | 1
+ed536cda 05 || aa6d9b40 aa6d9b40 | 1
+da8ae2b5 1f || 80000000 80000000 | 1
+3cf11979 04 || cf119790 cf119790 | 1
+e8740cd0 0a || d0334000 d0334000 | 1
+55f6adab 0e || ab6ac000 ab6ac000 | 1
+6e5daddc 1a || 70000000 70000000 | 1
+fedf72fd 03 || f6fb97e8 f6fb97e8 | 1
+2b0eed56 0e || bb558000 bb558000 | 1
+b3d97667 0a || 65d99c00 65d99c00 | 1
+5b6fb9b6 18 || b6000000 b6000000 | 1
+3cd18779 18 || 79000000 79000000 | 1
+4a74bf94 13 || fca00000 fca00000 | 1
+823f2c04 19 || 08000000 08000000 | 1
+6dcb69db 0d || 6d3b6000 6d3b6000 | 1
+6cb0b7d9 0d || 16fb2000 16fb2000 | 1
+bb45e276 0a || 1789d800 1789d800 | 1
+5b172db6 15 || b6c00000 b6c00000 | 1
+a3071a46 04 || 3071a460 3071a460 | 1
diff --git a/wally-pipelined/src/muldiv/div/shift_left_tb.sv b/wally-pipelined/src/muldiv/div/shift_left_tb.sv
new file mode 100644
index 00000000..2d5d3dad
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift_left_tb.sv
@@ -0,0 +1,71 @@
+//
+// File name : tb
+// Title     : test
+// project   : HW3
+// Library   : test
+// Purpose   : definition of modules for testbench 
+// notes :   
+//
+// Copyright Oklahoma State University
+//
+
+// Top level stimulus module
+
+`timescale 1ns/1ps
+
+`define XLEN 32
+module stimulus;
+
+   logic [`XLEN-1:0]         A;   
+   logic [$clog2(`XLEN)-1:0] Shift;   
+   logic [`XLEN-1:0] 	     Z;
+   logic [`XLEN-1:0] 	     Z_corr;      
+
+   //logic [63:0]       A;
+   //logic [5:0] 	      Shift;
+   //logic [63:0]       Z;
+   //logic [63:0]       Z_corr;
+   //logic [63:0]       Z_orig;
+
+   
+   logic 	 clk;   
+
+   integer 	 handle3;
+   integer 	 desc3;
+   integer 	 i;   
+   
+   // instatiate part to test
+   shift_left dut1 (A, Shift, Z);
+   assign Z_corr = (A << Shift);   
+
+   initial 
+     begin	
+	clk = 1'b1;
+	forever #5 clk = ~clk;
+     end
+   
+   initial
+     begin
+	handle3 = $fopen("shift_left.out");
+	desc3 = handle3;	
+     end
+   
+   initial
+     begin
+	for (i=0; i < 256; i=i+1)
+	  begin
+	     // Put vectors before beginning of clk
+	     @(posedge clk)
+	       begin
+		  A = $random;
+		  Shift = $random;
+	       end
+	     @(negedge clk)
+	       begin
+		  $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
+	       end
+	  end // for (i=0; i < 256; i=i+1)
+	$finish;// 	
+     end // initial begin   
+   
+endmodule // stimulus
diff --git a/wally-pipelined/src/muldiv/div/shift_right.do b/wally-pipelined/src/muldiv/div/shift_right.do
new file mode 100755
index 00000000..a41b7bfa
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift_right.do
@@ -0,0 +1,55 @@
+# Copyright 1991-2016 Mentor Graphics Corporation
+# 
+# Modification by Oklahoma State University
+# Use with Testbench 
+# James Stine, 2008
+# Go Cowboys!!!!!!
+#
+# All Rights Reserved.
+#
+# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
+# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
+# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+
+# Use this run.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do run.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do run.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+vlog mux_div.sv shift.sv shift_right_tb.sv
+
+# start and run simulation
+vsim -voptargs=+acc work.stimulus
+
+view wave
+
+-- display input and output signals as hexidecimal values
+# Diplays All Signals recursively
+add wave -hex -r /stimulus/*
+
+-- Set Wave Output Items 
+TreeUpdate [SetDefaultTree]
+WaveRestoreZoom {0 ps} {75 ns}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+
+-- Run the Simulation 
+run 800ns
+quit
diff --git a/wally-pipelined/src/muldiv/div/shift_right.out b/wally-pipelined/src/muldiv/div/shift_right.out
new file mode 100644
index 00000000..42202ab5
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift_right.out
@@ -0,0 +1,24 @@
+12153524 01 || 090a9a92 090a9a92 | 1
+8484d609 03 || 10909ac1 10909ac1 | 1
+06b97b0d 0d || 000035cb 000035cb | 1
+b2c28465 12 || 00002cb0 00002cb0 | 1
+00f3e301 0d || 0000079f 0000079f | 1
+3b23f176 1d || 00000001 00000001 | 1
+76d457ed 0c || 00076d45 00076d45 | 1
+7cfde9f9 06 || 01f3f7a7 01f3f7a7 | 1
+e2f784c5 0a || 0038bde1 0038bde1 | 1
+72aff7e5 17 || 000000e5 000000e5 | 1
+8932d612 0f || 00011265 00011265 | 1
+793069f2 0e || 0001e4c1 0001e4c1 | 1
+f4007ae8 05 || 07a003d7 07a003d7 | 1
+2e58495c 1d || 00000001 00000001 | 1
+96ab582d 05 || 04b55ac1 04b55ac1 | 1
+b1ef6263 0a || 002c7bd8 002c7bd8 | 1
+c03b2280 00 || c03b2280 c03b2280 | 1
+557845aa 1d || 00000002 00000002 | 1
+cb203e96 13 || 00001964 00001964 | 1
+86bc380d 13 || 000010d7 000010d7 | 1
+359fdd6b 15 || 000001ac 000001ac | 1
+81174a02 0e || 0002045d 0002045d | 1
+0effe91d 0f || 00001dff 00001dff | 1
+11844923 0a || 00046112 00046112 | 1
diff --git a/wally-pipelined/src/muldiv/div/shift_right_tb.sv b/wally-pipelined/src/muldiv/div/shift_right_tb.sv
new file mode 100755
index 00000000..b3527748
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shift_right_tb.sv
@@ -0,0 +1,64 @@
+//
+// File name : tb
+// Title     : test
+// project   : HW3
+// Library   : test
+// Purpose   : definition of modules for testbench 
+// notes :   
+//
+// Copyright Oklahoma State University
+//
+
+// Top level stimulus module
+
+`timescale 1ns/1ps
+
+`define XLEN 32
+module stimulus;
+
+   logic [`XLEN-1:0]         A;   
+   logic [$clog2(`XLEN)-1:0] Shift;   
+   logic [`XLEN-1:0] 	     Z;
+   logic [`XLEN-1:0] 	     Z_corr;      
+
+   logic 	 clk;   
+
+   integer 	 handle3;
+   integer 	 desc3;
+   integer 	 i;   
+   
+   // instatiate part to test
+   shift_right dut1 (A, Shift, Z);
+   assign Z_corr = (A >> Shift);   
+
+   initial 
+     begin	
+	clk = 1'b1;
+	forever #5 clk = ~clk;
+     end
+   
+   initial
+     begin
+	handle3 = $fopen("shift_right.out");
+	desc3 = handle3;	
+	#250 $finish;		
+     end
+   
+   initial
+     begin
+	for (i=0; i < 128; i=i+1)
+	  begin
+	     // Put vectors before beginning of clk
+	     @(posedge clk)
+	       begin
+		  A = $random;
+		  Shift = $random;
+	       end
+	     @(negedge clk)
+	       begin
+		  $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
+	       end
+	  end // @(negedge clk)
+     end // for (j=0; j < 32; j=j+1)
+   
+endmodule // stimulus
diff --git a/wally-pipelined/src/muldiv/div/shifter.sv b/wally-pipelined/src/muldiv/div/shifter.sv
new file mode 100644
index 00000000..779a02a4
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/shifter.sv
@@ -0,0 +1,18 @@
+module shifter_right(input logic signed [63:0] a,
+		     input logic [ 5:0] 	shamt,
+		     output logic signed [63:0] y);
+
+
+   y = a >> shamt;
+
+endmodule // shifter_right
+
+module shifter_left(input logic signed [63:0] a,
+		    input logic [ 5:0] 	       shamt,
+		    output logic signed [63:0] y);
+
+
+   y = a << shamt;
+
+endmodule // shifter_right
+
diff --git a/wally-pipelined/src/muldiv/div/test_int64div.sv b/wally-pipelined/src/muldiv/div/test_int64div.sv
index 995c26ff..8e7f4cc2 100644
--- a/wally-pipelined/src/muldiv/div/test_int64div.sv
+++ b/wally-pipelined/src/muldiv/div/test_int64div.sv
@@ -60,8 +60,8 @@ module tb;
 	#0  start = 1'b0;	
 	#0  reset = 1'b1;
 	#22 reset = 1'b0;	
-	#25 N = 64'h10fd_3ded_adea_5195;
-	#0  D = 64'hdf7f_3844_121b_cc23;	
+	#25 N = 64'hffff_ffff_ffff_ffff;
+	#0  D = 64'h0000_0000_0000_0000;
 	#0  start = 1'b1;
 	#50 start = 1'b0;	
 
diff --git a/wally-pipelined/src/muldiv/div/udiv b/wally-pipelined/src/muldiv/div/udiv
new file mode 100755
index 00000000..8b1ac689
Binary files /dev/null and b/wally-pipelined/src/muldiv/div/udiv differ
diff --git a/wally-pipelined/src/muldiv/div/udiv.c b/wally-pipelined/src/muldiv/div/udiv.c
new file mode 100644
index 00000000..c2756569
--- /dev/null
+++ b/wally-pipelined/src/muldiv/div/udiv.c
@@ -0,0 +1,24 @@
+#include <stdio.h>
+#include <math.h>
+#include <inttypes.h>
+
+int main() {
+
+  uint64_t N;
+  uint64_t D;
+  uint64_t Q;
+
+  D = 0xdf7f3844121bcc23;
+  N = 0x10fd3dedadea5195;
+  N = 0xffffffffffffffff;
+  D = 0x0000000000000000;
+  Q = N/D;
+
+  printf("N = %" PRIx64 "\n", N);
+  printf("D = %" PRIx64 "\n", D);
+  printf("Q = %" PRIx64 "\n", Q);
+  printf("R = %" PRIx64 "\n", N%D);  
+
+
+
+}
diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv
index 8d661992..0df7e5d7 100644
--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@@ -47,44 +47,52 @@ module muldiv (
 	 logic [`XLEN-1:0] MulDivResultE, MulDivResultM;
 	 logic [`XLEN-1:0] PrelimResultE;
 	 logic [`XLEN-1:0] QuotE, RemE;
-	 logic [`XLEN*2-1:0] ProdE;
-	 
+	 //logic [`XLEN-1:0] Q, R;	 
+	 logic [`XLEN*2-1:0] ProdE; 
+
+	 logic 		     enable_q;	 
+	 logic [2:0] 	     Funct3E_Q;
+	 logic 		     div0error;
+	 logic [`XLEN-1:0]   N, D;
+
+	 logic 		     gclk;
 	 logic 		     DivStartE;
-	 logic 		     startDivideE;
-
-	logic 		     enable_q, gclk;
-
-	logic [2:0] 	     Funct3E_Q;
-    logic            div0error;
-
-
+	 logic 		     startDivideE;   	 
+	 
 	 // Multiplier
 	 mul mul(.*);
 	 // Divide
 
 	// *** replace this clock gater
-	always @(negedge clk) begin
-	  enable_q <= ~StallM;
-	end
-	assign gclk = enable_q & clk;
-	
-	 div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, SrcAE, SrcBE, gclk, reset, startDivideE);
+	 always @(negedge clk) begin
+	    enable_q <= ~StallM;
+	 end
+	 assign gclk = enable_q & clk;
+
+	 // capture the Numerator/Denominator	 
+	 flopenrc #(`XLEN) reg_num (.d(SrcAE), .q(N),
+				    .en(startDivideE), .clear(DivDoneE),
+				    .reset(reset),  .clk(~gclk));
+	 flopenrc #(`XLEN) reg_den (.d(SrcBE), .q(D),
+				    .en(startDivideE), .clear(DivDoneE),
+				    .reset(reset),  .clk(~gclk));	 
+	 
+	 div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, N, D, gclk, reset, startDivideE);
 
 	 // Added for debugging of start signal for divide
 	 assign startDivideE = MulDivE&DivStartE&~DivBusyE;
-
-	// capture the start control signals since they are not held constant.
-	flopenrc #(3) funct3ereg (.d(Funct3E),
-			       .q(Funct3E_Q),
-			       .en(DivStartE),
-			       .clear(DivDoneE),
-			       .reset(reset),
-			       .clk(clk));
-	
-
+	 
+	 // capture the start control signals since they are not held constant.
+	 flopenrc #(3) funct3ereg (.d(Funct3E),
+				   .q(Funct3E_Q),
+				   .en(DivStartE),
+				   .clear(DivDoneE),
+				   .reset(reset),
+				   .clk(clk));
+	 
 	 // Select result
 	 always_comb
-//           case (DivDoneE ? Funct3E_Q : Funct3E)
+	   //           case (DivDoneE ? Funct3E_Q : Funct3E)
            case (Funct3E)	   
              3'b000: PrelimResultE = ProdE[`XLEN-1:0];
              3'b001: PrelimResultE = ProdE[`XLEN*2-1:`XLEN];
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index cfb87df4..488fd600 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -67,13 +67,13 @@ module testbench();
     "rv64m/I-MULH-01", "3000",
     "rv64m/I-MULHSU-01", "3000",
     "rv64m/I-MULHU-01", "3000",
-    "rv64m/I-MULW-01", "3000"
+    "rv64m/I-MULW-01", "3000",
     //"rv64m/I-DIV-01", "3000",
-    //"rv64m/I-DIVU-01", "3000"
+    "rv64m/I-DIVU-01", "3000",
     //"rv64m/I-DIVUW-01", "3000",
     //"rv64m/I-DIVW-01", "3000",
     //"rv64m/I-REM-01", "3000",
-    //"rv64m/I-REMU-01", "3000",
+    "rv64m/I-REMU-01", "3000"
     //"rv64m/I-REMUW-01", "3000",
     //"rv64m/I-REMW-01", "3000"
   };