From 4d14c714a744a2892543ec063f31c17fed208501 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 4 Mar 2021 13:01:41 -0600 Subject: [PATCH] Fixed forwarding around the 2 bit predictor. --- wally-pipelined/src/ifu/BTBPredictor.sv | 3 +-- wally-pipelined/src/ifu/twoBitPredictor.sv | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv index 4a78353f..85cb586c 100644 --- a/wally-pipelined/src/ifu/BTBPredictor.sv +++ b/wally-pipelined/src/ifu/BTBPredictor.sv @@ -80,9 +80,8 @@ module BTBPredictor assign Valid = ValidBits[LookUpPCIndexQ]; // the BTB contains the target address. - // *** future version may contain the instruction class, a tag or partial tag, - // and other indirection branch data. // Another optimization may be using a PC relative address. + // *** need to add forwarding. SRAM2P1R1W #(Depth, `XLEN+4) memory(.clk(clk), .reset(reset), diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv index 704d7fb0..f01f48dc 100644 --- a/wally-pipelined/src/ifu/twoBitPredictor.sv +++ b/wally-pipelined/src/ifu/twoBitPredictor.sv @@ -31,7 +31,7 @@ module twoBitPredictor #(parameter int Depth = 10 ) (input logic clk, - input logic reset, + input logic reset, input logic [`XLEN-1:0] LookUpPC, output logic [1:0] Prediction, // update @@ -42,6 +42,8 @@ module twoBitPredictor logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex; logic [1:0] PredictionMemory; + logic DoForwarding, DoForwardingF; + logic [1:0] UpdatePredictionF; // hashing function for indexing the PC @@ -63,6 +65,20 @@ module twoBitPredictor .BitWEN1(2'b11)); // need to forward when updating to the same address as reading. - assign Prediction = (UpdatePC == LookUpPC) ? UpdatePrediction : PredictionMemory; + // first we compare to see if the update and lookup addreses are the same + assign DoForwarding = UpdatePCIndex == LookUpPCIndex; + + // register the update value and the forwarding signal into the Fetch stage + flopr #(1) DoForwardingReg(.clk(clk), + .reset(reset), + .d(DoForwarding), + .q(DoForwardingF)); + + flopr #(2) UpdatePredictionReg(.clk(clk), + .reset(reset), + .d(UpdatePrediction), + .q(UpdatePredictionF)); + + assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory; endmodule