diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
index 38efe8fd..219d9b4e 100644
--- a/pipelined/src/ifu/bpred.sv
+++ b/pipelined/src/ifu/bpred.sv
@@ -108,7 +108,7 @@ module bpred (
     speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
-      .BranchInstrW(InstrClassW[0]), .PCSrcE);
+      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
 
   end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv
index eaa21c2f..36c9086b 100644
--- a/pipelined/src/ifu/speculativegshare.sv
+++ b/pipelined/src/ifu/speculativegshare.sv
@@ -40,7 +40,8 @@ module speculativegshare
    output logic            DirPredictionWrongE,
    // update
    input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
+   input logic [3:0]       WrongPredInstrClassD, 
    input logic             PCSrcE
    );
 
@@ -53,7 +54,8 @@ module speculativegshare
   logic [k-1:0]            GHRF;
   logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
   logic [k-1:0]            GHRNextF;
-  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
+  logic [k:-1] 			   GHRNextD, OldGHRD;
+  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE, IndexM;
   
@@ -118,8 +120,11 @@ module speculativegshare
 
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
   
-  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
-  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
+  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
+  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
+				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-2:-1] : // shift left
+				OldGHRD;
 
   assign GHRNextE = FlushE ? GHRNextM : GHRD;
   flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);