From ec65c078e2c464e7a73ad5d8e946c3e13914ac44 Mon Sep 17 00:00:00 2001 From: Abe Date: Fri, 16 Jul 2021 19:13:18 -0400 Subject: [PATCH 1/4] Updated location to find compiler for coremark --- riscv-coremark/build-coremark.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv-coremark/build-coremark.sh b/riscv-coremark/build-coremark.sh index e2975352..bdd10072 100755 --- a/riscv-coremark/build-coremark.sh +++ b/riscv-coremark/build-coremark.sh @@ -4,7 +4,8 @@ set -e BASEDIR=$PWD CM_FOLDER=coremark -RISCV=/home/ehedenberg/riscvcompiler +#RISCV=/home/ehedenberg/riscvcompiler +RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im" cd $BASEDIR/$CM_FOLDER From 3b10ea978589ec7aced8aa073adc542c6ed10d8a Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 20 Jul 2021 00:22:07 -0400 Subject: [PATCH 2/4] major fixes to CSR checking --- wally-pipelined/testbench/testbench-linux.sv | 98 ++++++++++++-------- 1 file changed, 57 insertions(+), 41 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 9b92183a..7038f1f0 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ module testbench(); - parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0459700; // # of instructions at which to turn on waves in graphical sim + parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0675000; // # of instructions at which to turn on waves in graphical sim parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can) /////////////////////////////////////////////////////////////////////////////// @@ -103,6 +103,7 @@ module testbench(); logic [99:0] StartCSRexpected[63:0]; string StartCSRname[99:0]; integer data_file_csr, scan_file_csr; + logic IllegalInstrFaultd; // ----------- // Error Macro @@ -158,16 +159,11 @@ module testbench(); // ------------------------------------- always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin - $display("!!!!!! illegal instruction !!!!!!!!!!"); - $display("(as a reminder, MCAUSE and MEPC are set by this)"); - $display("at %0t ps, PCM %x, instr %0d, dut.hart.lsu.dcache.MemPAdrM %x", $time, dut.hart.ifu.PCM, instrs, dut.hart.lsu.dcache.MemPAdrM); - `ERROR + // This is sometimes okay if the source code intentionally causes it. + $display("Warning: illegal instruction exception at %0t ps, InstrNum %0d, PCM %x, InstrM %s", $time, instrs, dut.hart.ifu.PCM, PCtextM); end if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin - $display("!!!!!! illegal (physical) memory access !!!!!!!!!!"); - $display("(as a reminder, MCAUSE and MEPC are set by this)"); - $display("at %0t ps, PCM %x, instr %0d, dut.hart.lsu.dcache.MemPAdrM %x", $time, dut.hart.ifu.PCM, instrs, dut.hart.lsu.dcache.MemPAdrM); - `ERROR + $display("Warning: illegal physical memory access exception at %0t ps, InstrNum %0d, PCM %x, InstrM %s", $time, instrs, dut.hart.ifu.PCM, PCtextM); end end @@ -524,50 +520,70 @@ module testbench(); end end + // ------------------- + // Additional Hardware + // ------------------- + always @(posedge clk) + IllegalInstrFaultd = dut.hart.priv.IllegalInstrFaultM; + // -------------- // Checker Macros // -------------- - string MSTATUSstring = "MSTATUS"; // string variables seem to compare more reliably than string literals (they gave me a lot of hassle), but *** there's probably a better way to do this + // String variables seem to compare more reliably than string literals (they gave me a lot of hassle), + // but *** there's probably a better way to do this. + // You can't just use the "__name" variables though because you need to declare variables before using them. + string MSTATUSstring = "MSTATUS"; string MIPstring = "MIP"; + string MEPCstring = "MEPC"; + string MCAUSEstring = "MCAUSE"; + string MTVALstring = "MTVAL"; string SEPCstring = "SEPC"; string SCAUSEstring = "SCAUSE"; string SSTATUSstring = "SSTATUS"; + + logic [63:0] expectedCSR; + string expectedCSRname; `define CHECK_CSR2(CSR, PATH) \ - logic [63:0] expected``CSR``; \ - string CSR; \ string ``CSR``name = `"CSR`"; \ - string expected``CSR``name; \ always @(``PATH``.``CSR``_REGW) begin \ - // MIP is not checked because QEMU bodges it (MTIP in particular), and even if QEMU reported it correctly, the timing would still be off \ - if ($time > 1 && (``CSR``name != MIPstring)) begin \ - // This is some feeble hackery designed to control the order in which CSRs are checked \ - // when multiple change at the same time. \ - if (``CSR``name == SEPCstring) #1; \ - if (``CSR``name == SCAUSEstring) #2; \ - if (``CSR``name == SSTATUSstring) #3; \ - scan_file_csr = $fscanf(data_file_csr, "%s\n", expected``CSR``name); \ - scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \ - if(expected``CSR``name.icompare(``CSR``name)) begin \ - $display("%0t ps, PCM %x %s, instr %0d: %s changed, expected %s", $time, dut.hart.ifu.PCM, PCtextM, instrs, `"CSR`", expected``CSR``name); \ + if (instrs == 0 && ~reset) begin \ + for(integer j=0; j Date: Tue, 20 Jul 2021 05:40:39 -0400 Subject: [PATCH 3/4] testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) --- wally-pipelined/testbench/testbench-linux.sv | 52 +++++++------------- 1 file changed, 18 insertions(+), 34 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 7038f1f0..c5711cce 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -154,6 +154,12 @@ module testbench(); clk <= 1; # 5; clk <= 0; # 5; end + // ------------------- + // Additional Hardware + // ------------------- + always @(posedge clk) + IllegalInstrFaultd = dut.hart.priv.IllegalInstrFaultM; + // ------------------------------------- // Special warnings for important faults // ------------------------------------- @@ -181,8 +187,11 @@ module testbench(); // Hack to compensate for QEMU's incorrect MSTATUS end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,16) == "mstatus") begin force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'ha00000000; - end else - release dut.hart.ieu.dp.regf.wd3; + end else release dut.hart.ieu.dp.regf.wd3; + // Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature) + if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin + force dut.hart.ieu.dp.WriteDataW = 0; + end else release dut.hart.ieu.dp.WriteDataW; end end @@ -200,7 +209,6 @@ module testbench(); lastPC2 <= lastPC; // If PCD isn't going to be flushed if (~PCDwrong || lastPC == PCDexpected) begin - // Stop if we've reached the end if($feof(data_file_PCF)) begin $display("no more PC data to read... CONGRATULATIONS!!!"); @@ -249,29 +257,7 @@ module testbench(); // Check if PCD is going to be flushed due to a branch or jump if (`BPRED_ENABLED) begin - PCDwrong = dut.hart.hzu.FlushD; //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET. - end else begin - casex (lastInstrDExpected[31:0]) - 32'b00000000001000000000000001110011, // URET - 32'b00010000001000000000000001110011, // SRET - 32'b00110000001000000000000001110011, // MRET - 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL - 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR - 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B - 32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ - 32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ - 32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J - PCDwrong = 1; - 32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK: - 32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR* - PCDwrong = 0; // tbh don't really know what should happen here - 32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, * - 32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR - 32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL - PCDwrong = 1; - default: - PCDwrong = 0; - endcase + PCDwrong = dut.hart.hzu.FlushD || (PCtextE.substr(0,3) == "mret"); //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET. end // Check PCD, InstrD @@ -354,9 +340,8 @@ module testbench(); end `SCAN_PC(data_file_PCM, scan_file_PCM, trashString, trashString, InstrMExpected, PCMexpected); `SCAN_PC(data_file_PCW, scan_file_PCW, trashString, trashString, InstrWExpected, PCWexpected); - // If repeated instr + // If repeated or instruction, we want to skip over it (indicates an interrupt) if (PCMexpected == PCWexpected) begin - // Increment file pointers past the repeated instruction. `SCAN_PC(data_file_PCM, scan_file_PCM, trashString, trashString, InstrMExpected, PCMexpected); `SCAN_PC(data_file_PCW, scan_file_PCW, trashString, trashString, InstrWExpected, PCWexpected); end @@ -365,6 +350,11 @@ module testbench(); `ERROR end end + // Skip over faulting instructions because they do not make it to the W stage. + if (IllegalInstrFaultd) begin + `SCAN_PC(data_file_PCM, scan_file_PCM, trashString, trashString, InstrMExpected, PCMexpected); + `SCAN_PC(data_file_PCW, scan_file_PCW, trashString, trashString, InstrWExpected, PCWexpected); + end end @@ -520,12 +510,6 @@ module testbench(); end end - // ------------------- - // Additional Hardware - // ------------------- - always @(posedge clk) - IllegalInstrFaultd = dut.hart.priv.IllegalInstrFaultM; - // -------------- // Checker Macros // -------------- From 6b72b1f85901c56f883bfdc3d3067cc10063207a Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 20 Jul 2021 13:37:52 -0400 Subject: [PATCH 4/4] ignore mhpmcounters because QEMU doesn't implement them --- wally-pipelined/testbench/testbench-linux.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index c5711cce..7e688413 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ module testbench(); - parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0675000; // # of instructions at which to turn on waves in graphical sim + parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0900000; // # of instructions at which to turn on waves in graphical sim parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can) /////////////////////////////////////////////////////////////////////////////// @@ -191,6 +191,9 @@ module testbench(); // Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature) if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin force dut.hart.ieu.dp.WriteDataW = 0; + // Hack to compensate for QEMU's correct but different mhpmcounter's (these too are optional) + end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,20) == "mhpmcounter") begin + force dut.hart.ieu.dp.WriteDataW = 0; end else release dut.hart.ieu.dp.WriteDataW; end end