From 4b8cbd9fa0205fecd4a663bf91d6e5e9f9478cc3 Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 16 Dec 2022 19:02:11 +0000 Subject: [PATCH] Added integer support for initC --- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index ed70bb18..8b9b8499 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -92,7 +92,7 @@ module fdivsqrtiter( // C register/initialization mux // Initialize C to -1 for sqrt and -R for division logic [1:0] initCUpper; - assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10; + assign initCUpper = (SqrtE & ~(MDUE)) ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10; assign initC = {initCUpper, {`DIVb{1'b0}}}; mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, IFDivStartE, CMux); flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, CMux, C[0]);