From 98d4929c57f793bfc4f02b8b8832eed775d0711e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 1 Nov 2022 15:23:24 -0500 Subject: [PATCH 01/23] Reduced complexity of logic supressing cache operations. --- pipelined/src/cache/cache.sv | 12 +++--------- pipelined/src/cache/cachefsm.sv | 22 ++++++---------------- pipelined/src/ifu/ifu.sv | 11 +++++------ pipelined/src/lsu/lsu.sv | 21 +++++++++++++++------ pipelined/src/lsu/lsuvirtmen.sv | 5 ++++- 5 files changed, 33 insertions(+), 38 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 67101ad8..16d2d2da 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -35,8 +35,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic reset, // cpu side input logic CPUBusy, - input logic [1:0] RW, - input logic [1:0] Atomic, + input logic [1:0] CacheRW, + input logic [1:0] CacheAtomic, input logic FlushCache, input logic InvalidateCache, input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. @@ -49,9 +49,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE output logic CacheMiss, output logic CacheAccess, // lsu control - input logic IgnoreRequestTLB, - input logic TrapM, - input logic Cacheable, input logic SelHPTW, // Bus fsm interface output logic [1:0] CacheBusRW, @@ -102,7 +99,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic ResetOrFlushAdr, ResetOrFlushWay; logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; - logic [1:0] CacheRW, CacheAtomic; logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; logic SelBusBuffer; @@ -209,10 +205,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - assign CacheRW = Cacheable ? RW : 2'b00; - assign CacheAtomic = Cacheable ? Atomic : 2'b00; cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .TrapM, + .CacheRW, .CacheAtomic, .CPUBusy, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 36e9e087..ff5183b7 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -40,9 +40,6 @@ module cachefsm input logic InvalidateCache, // hazard inputs input logic CPUBusy, - // interlock fsm - input logic IgnoreRequestTLB, - input logic TrapM, // Bus inputs input logic CacheBusAck, // dcache internals @@ -96,17 +93,12 @@ module cachefsm STATE_FLUSH_WRITE_BACK} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; - logic IgnoreRequest; - assign IgnoreRequest = IgnoreRequestTLB | TrapM; - // if the command is used in the READY state then the cache needs to be able to supress - // using both IgnoreRequestTLB and DCacheTrapM. Otherwise we can just use IgnoreRequestTLB. - - assign DoFlush = FlushCache & ~TrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. + assign DoFlush = FlushCache; assign AMO = CacheAtomic[1] & (&CacheRW); - assign DoAMO = AMO & ~IgnoreRequest; - assign DoRead = CacheRW[1] & ~IgnoreRequest; - assign DoWrite = CacheRW[0] & ~IgnoreRequest; + assign DoAMO = AMO; + assign DoRead = CacheRW[1]; + assign DoWrite = CacheRW[0]; assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit & ~InvalidateCache; assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; @@ -129,7 +121,7 @@ module cachefsm always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY; + STATE_READY: if(InvalidateCache) NextState = STATE_READY; else if(DoFlush) NextState = STATE_FLUSH; // Delayed LRU update. Cannot check if victim line is dirty on this cycle. // To optimize do the fetch first, then eviction if necessary. @@ -204,9 +196,7 @@ module cachefsm // assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | // (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? - assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. - // use the raw requests as we don't want TrapM in the critical path - (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed + assign SelAdr = (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed (CurrState == STATE_READY & (DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_EVICT_DIRTY) | diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 86ad9bfb..8f632acb 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -212,26 +212,25 @@ module ifu ( logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; - logic [1:0] CacheBusRW, BusRW; - + logic [1:0] CacheBusRW, BusRW, CacheRWF; //assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; assign BusRW = ~IgnoreRequest & ~CacheableF & ~SelIROM ? IFURWF : '0; + assign CacheRWF = ~IgnoreRequest & CacheableF & ~SelIROM ? IFURWF : '0; cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM, + icache(.clk, .reset, .CPUBusy, .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, .ReadDataWord(ICacheInstrF), - .Cacheable(CacheableF), .SelHPTW('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .ByteMask('0), .WordCount('0), .SelBusWord('0), .FinalWriteData('0), - .RW(IFURWF), - .Atomic('0), .FlushCache('0), + .CacheRW(CacheRWF), + .CacheAtomic('0), .FlushCache('0), .NextAdr(PCNextFSpill[11:0]), .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index fc74aff7..d469e672 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -212,6 +212,8 @@ module lsu ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. assign DTIMAdr = MemRWM[0] ? IEUAdrExtM[`PA_BITS-1:0] : IEUAdrExtE[`PA_BITS-1:0]; // zero extend or contract to PA_BITS assign DTIMMemRWM = SelDTIM & ~IgnoreRequest ? LSURWM : '0; + // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. + // **** create config to support DTIM with floating point. dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), .Adr(DTIMAdr), .TrapM, .WriteDataM(LSUWriteDataM), @@ -237,18 +239,23 @@ module lsu ( logic [1:0] CacheBusRW, BusRW; localparam integer LLENPOVERAHBW = `LLEN / `AHBW; logic CacheableOrFlushCacheM; - + logic [1:0] CacheRWM, CacheAtomicM; + logic CacheFlushM; + assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; - + assign CacheRWM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; + assign CacheAtomicM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSUAtomicM : '0; + assign CacheFlushM = ~TrapM & FlushDCacheM; + cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM), - .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), + .clk, .reset, .CPUBusy, .SelBusWord, .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), - .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableOrFlushCacheM), .SelHPTW, + .FinalWriteData(LSUWriteDataM), .SelHPTW, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), - .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), + .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); @@ -264,6 +271,8 @@ module lsu ( // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times. // DTIMReadDataWordM should be increased to LLEN. + // *** DTIMReadDataWordM should be LLEN + // pma should generate expection for LLEN read to periph. mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}), .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM)); diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 01da1824..6530d12d 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -74,7 +74,10 @@ module lsuvirtmem( logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF; logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM; logic SelHPTWAdr; - + + /// **** move to HPTW + // **** rename to walker mux? + // move all the muxes to walkermux and instantiate these in lsu under virtmem_supported. assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM; From 42c0a10d0739a39863bf03f165d77283322eb512 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 7 Nov 2022 15:03:43 -0600 Subject: [PATCH 02/23] Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap. --- pipelined/src/cache/cache.sv | 7 ++-- pipelined/src/cache/cachefsm.sv | 42 ++++++++++------------- pipelined/src/cache/cacheway.sv | 13 +++---- pipelined/src/ebu/ahbcacheinterface.sv | 3 +- pipelined/src/ebu/ahbinterface.sv | 3 +- pipelined/src/ebu/buscachefsm.sv | 5 +-- pipelined/src/ebu/busfsm.sv | 7 ++-- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/ifu/ifu.sv | 18 +++++----- pipelined/src/ifu/spillsupport.sv | 8 ++--- pipelined/src/lsu/dtim.sv | 16 ++++----- pipelined/src/lsu/lsu.sv | 25 +++++++------- pipelined/src/lsu/lsuvirtmen.sv | 10 +++--- pipelined/src/mmu/hptw.sv | 14 +++++++- pipelined/src/wally/wallypipelinedcore.sv | 4 +-- 15 files changed, 96 insertions(+), 81 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 16d2d2da..dfd64684 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -34,6 +34,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic clk, input logic reset, // cpu side + input logic Flush, input logic CPUBusy, input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, @@ -125,11 +126,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .CacheWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, - .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, + .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush, .Invalidate(InvalidateCache)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn); + .clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~Flush)); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; @@ -206,7 +207,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .CacheRW, .CacheAtomic, .CPUBusy, + .Flush, .CacheRW, .CacheAtomic, .CPUBusy, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index ff5183b7..edbf6f99 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -34,6 +34,7 @@ module cachefsm (input logic clk, input logic reset, // inputs from IEU + input logic Flush, input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, input logic FlushCache, @@ -75,9 +76,8 @@ module cachefsm logic resetDelay; logic AMO; - logic DoAMO, DoRead, DoWrite, DoFlush; - logic DoAnyUpdateHit, DoAnyHit; - logic DoAnyMiss; + logic AnyUpdateHit, AnyHit; + logic AnyMiss; logic FlushFlag, FlushWayAndNotAdrFlag; typedef enum logic [3:0] {STATE_READY, // hit states @@ -94,19 +94,15 @@ module cachefsm (* mark_debug = "true" *) statetype CurrState, NextState; - assign DoFlush = FlushCache; assign AMO = CacheAtomic[1] & (&CacheRW); - assign DoAMO = AMO; - assign DoRead = CacheRW[1]; - assign DoWrite = CacheRW[0]; - assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit & ~InvalidateCache; - assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; - assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit); + assign AnyMiss = (AMO | CacheRW[1] | CacheRW[0]) & ~CacheHit & ~InvalidateCache; + assign AnyUpdateHit = (AMO | CacheRW[0]) & CacheHit; + assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. - assign CacheAccess = (DoAMO | DoRead | DoWrite) & CurrState == STATE_READY; + assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; assign CacheMiss = CacheAccess & ~CacheHit; // special case on reset. When the fsm first exists reset the @@ -115,18 +111,18 @@ module cachefsm flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); always_ff @(posedge clk) - if (reset) CurrState <= #1 STATE_READY; + if (reset | Flush) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; always_comb begin NextState = STATE_READY; case (CurrState) STATE_READY: if(InvalidateCache) NextState = STATE_READY; - else if(DoFlush) NextState = STATE_FLUSH; + else if(FlushCache) NextState = STATE_FLUSH; // Delayed LRU update. Cannot check if victim line is dirty on this cycle. // To optimize do the fetch first, then eviction if necessary. - else if(DoAnyMiss & ~VictimDirty) NextState = STATE_MISS_FETCH_WDV; - else if(DoAnyMiss & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + else if(AnyMiss & ~VictimDirty) NextState = STATE_MISS_FETCH_WDV; + else if(AnyMiss & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_READY; STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; else NextState = STATE_MISS_FETCH_WDV; @@ -155,7 +151,7 @@ module cachefsm // com back to CPU assign CacheCommitted = CurrState != STATE_READY; - assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) | + assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. @@ -165,16 +161,16 @@ module cachefsm (CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag) & CacheBusAck); // write enables internal to cache assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; - assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) | + assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | (CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0])); assign ClearValid = '0; assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | (CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck); - assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | + assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_MISS_WRITE_CACHE_LINE); // Flush and eviction controls assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | - (CurrState == STATE_READY & DoAnyMiss & VictimDirty); + (CurrState == STATE_READY & AnyMiss & VictimDirty); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK); assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; @@ -185,11 +181,11 @@ module cachefsm assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls - assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss & ~VictimDirty) | + assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~VictimDirty) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) | (CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck); -// assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss; - assign CacheBusRW[0] = (CurrState == STATE_READY & DoAnyMiss & VictimDirty) | +// assign CacheBusRW[1] = CurrState == STATE_READY & AnyMiss; + assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & VictimDirty) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); @@ -197,7 +193,7 @@ module cachefsm // (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed - (CurrState == STATE_READY & (DoAnyMiss)) | + (CurrState == STATE_READY & (AnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 422ae98d..4776aeaf 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -48,6 +48,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, + input logic Flush, // input logic [(`XLEN-1)/8:0] ByteMask, input logic [LINELEN/8-1:0] LineByteMask, @@ -86,7 +87,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce, .addr(RAdr), .dout(ReadTag), .bwe('1), - .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay)); + .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~Flush)); // AND portion of distributed tag multiplexer mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); @@ -109,7 +110,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), - .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); + .we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end // AND portion of distributed read multiplexers @@ -123,8 +124,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, always_ff @(posedge clk) begin // Valid bit array, if (reset | Invalidate) ValidBits <= #1 '0; if(ce) begin Valid <= #1 ValidBits[RAdr]; - if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; - else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; + if (SetValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b1; + else if (ClearValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b0; end end @@ -138,8 +139,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; if(ce) begin Dirty <= #1 DirtyBits[RAdr]; - if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; - else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0; + if (SetDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b1; + else if (ClearDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b0; end end end else assign Dirty = 1'b0; diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 5652cd02..4600edcd 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -56,6 +56,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE input logic Cacheable, // lsu/ifu interface + input logic Flush, input logic [`PA_BITS-1:0] PAdr, input logic [1:0] BusRW, input logic CPUBusy, @@ -83,7 +84,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( - .HCLK, .HRESETn, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, + .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, .CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index be2fbba5..9955cca5 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -47,6 +47,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter output logic [`XLEN/8-1:0] HWSTRB, // lsu/ifu interface + input logic Flush, input logic [1:0] BusRW, input logic [`XLEN/8-1:0] ByteMask, input logic [`XLEN-1:0] WriteData, @@ -71,7 +72,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter assign HWSTRB = '0; end - busfsm busfsm(.HCLK, .HRESETn, .BusRW, + busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, .HTRANS, .HWRITE); endmodule diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index da8c0e25..6965c673 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -38,6 +38,7 @@ module buscachefsm #(parameter integer WordCountThreshold, input logic HRESETn, // IEU interface + input logic Flush, input logic [1:0] BusRW, input logic CPUBusy, output logic BusCommitted, @@ -77,7 +78,7 @@ module buscachefsm #(parameter integer WordCountThreshold, logic CacheAccess; always_ff @(posedge HCLK) - if (~HRESETn) CurrState <= #1 ADR_PHASE; + if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; else CurrState <= #1 NextState; always_comb begin @@ -135,7 +136,7 @@ module buscachefsm #(parameter integer WordCountThreshold, assign BusCommitted = CurrState != ADR_PHASE; // AHB bus interface - assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) | + assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) | (CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 336c3b4e..8203fa74 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -36,6 +36,7 @@ module busfsm input logic HRESETn, // IEU interface + input logic Flush, input logic [1:0] BusRW, input logic CPUBusy, output logic BusCommitted, @@ -55,8 +56,8 @@ module busfsm (* mark_debug = "true" *) busstatetype CurrState, NextState; always_ff @(posedge HCLK) - if (~HRESETn) CurrState <= #1 ADR_PHASE; - else CurrState <= #1 NextState; + if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; + else CurrState <= #1 NextState; always_comb begin case(CurrState) @@ -76,7 +77,7 @@ module busfsm assign BusCommitted = CurrState != ADR_PHASE; - assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW) ? AHB_NONSEQ : AHB_IDLE; + assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE; assign HWRITE = BusRW[0]; assign CaptureEn = CurrState == DATA_PHASE; diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0ca3c5bc..39700ed0 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -70,7 +70,7 @@ module hazard( // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE? - assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); + assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM) | (FDivBusyE & ~TrapM & ~IntPendingM); assign #1 StallF = StallFCause | StallD; assign #1 StallD = StallDCause | StallE; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 8f632acb..93804877 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -34,7 +34,7 @@ module ifu ( input logic clk, reset, input logic StallF, StallD, StallE, StallM, - input logic FlushF, FlushD, FlushE, FlushM, + input logic FlushF, FlushD, FlushE, FlushM, FlushW, // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, @@ -130,7 +130,7 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport - spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF), + spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF), .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport @@ -194,7 +194,7 @@ module ifu ( assign CommittedF = CacheCommittedF | BusCommittedF; logic IgnoreRequest; - assign IgnoreRequest = ITLBMissF | TrapM; + assign IgnoreRequest = ITLBMissF | FlushD; // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (`IROM_SUPPORTED) begin : irom @@ -215,12 +215,12 @@ module ifu ( logic [1:0] CacheBusRW, BusRW, CacheRWF; //assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; - assign BusRW = ~IgnoreRequest & ~CacheableF & ~SelIROM ? IFURWF : '0; - assign CacheRWF = ~IgnoreRequest & CacheableF & ~SelIROM ? IFURWF : '0; + assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; + assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .CPUBusy, + icache(.clk, .reset, .Flush(FlushW), .CPUBusy, .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, @@ -237,7 +237,7 @@ module ifu ( ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, - .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), + .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .WordCount(), .Cacheable(CacheableF), .SelBusWord(), .CacheBusAck(ICacheBusAck), @@ -252,11 +252,11 @@ module ifu ( logic CaptureEn; logic [31:0] FetchBuffer; logic [1:0] BusRW; - assign BusRW = ~IgnoreRequest & ~SelIROM ? IFURWF : '0; + assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0; // assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM}; assign IFUHSIZE = 3'b010; - ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), + ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushW), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 56bd3a78..b247c2d3 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -35,7 +35,7 @@ module spillsupport #(parameter CACHE_ENABLED) (input logic clk, input logic reset, - input logic StallF, + input logic StallF, Flush, input logic [`XLEN-1:0] PCF, input logic [`XLEN-3:0] PCPlusUpperF, input logic [`XLEN-1:0] PCNextF, @@ -61,7 +61,7 @@ module spillsupport #(parameter CACHE_ENABLED) mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); - mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF), + mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill)); mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); @@ -69,7 +69,7 @@ module spillsupport #(parameter CACHE_ENABLED) assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF)); always_ff @(posedge clk) - if (reset) CurrState <= #1 STATE_READY; + if (reset | Flush) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; always_comb begin @@ -89,7 +89,7 @@ module spillsupport #(parameter CACHE_ENABLED) assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16]; flopenr #(16) SpillInstrReg(.clk(clk), - .en(SpillSaveF), + .en(SpillSaveF & ~Flush), .reset(reset), .d(SavedInstr), .q(SpillDataLine0)); diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 45ada1c6..8f991883 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -30,13 +30,13 @@ `include "wally-config.vh" module dtim( - input logic clk, reset, ce, - input logic [1:0] MemRWM, - input logic [`PA_BITS-1:0] Adr, - input logic TrapM, - input logic [`LLEN-1:0] WriteDataM, - input logic [`LLEN/8-1:0] ByteMaskM, - output logic [`LLEN-1:0] ReadDataWordM + input logic clk, reset, ce, + input logic [1:0] MemRWM, + input logic [`PA_BITS-1:0] Adr, + input logic FlushW, + input logic [`LLEN-1:0] WriteDataM, + input logic [`LLEN/8-1:0] ByteMaskM, + output logic [`LLEN-1:0] ReadDataWordM ); logic we; @@ -44,7 +44,7 @@ module dtim( localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8); localparam OFFSET = $clog2(`LLEN/8); - assign we = MemRWM[0] & ~TrapM; // have to ignore write if Trap. + assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. sram1p1rw #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index d469e672..5be7c931 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -47,7 +47,6 @@ module lsu ( input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, - input logic TrapM, input logic FlushDCacheM, output logic CommittedM, output logic SquashSCW, @@ -131,7 +130,7 @@ module lsu ( if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, - .TrapM, .DCacheStallM, .SATP_REGW, .PCF, + .FlushW, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .IMWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, @@ -203,7 +202,7 @@ module lsu ( logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; logic [`LLEN-1:0] ReadDataWordMuxM, DTIMReadDataWordM, DCacheReadDataWordM; logic IgnoreRequest; - assign IgnoreRequest = IgnoreRequestTLB | TrapM; + assign IgnoreRequest = IgnoreRequestTLB | FlushW; if (`DTIM_SUPPORTED) begin : dtim logic [`PA_BITS-1:0] DTIMAdr; @@ -211,12 +210,12 @@ module lsu ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. assign DTIMAdr = MemRWM[0] ? IEUAdrExtM[`PA_BITS-1:0] : IEUAdrExtE[`PA_BITS-1:0]; // zero extend or contract to PA_BITS - assign DTIMMemRWM = SelDTIM & ~IgnoreRequest ? LSURWM : '0; + assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0; // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** create config to support DTIM with floating point. dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), .Adr(DTIMAdr), - .TrapM, .WriteDataM(LSUWriteDataM), + .FlushW, .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); end else begin end @@ -242,15 +241,15 @@ module lsu ( logic [1:0] CacheRWM, CacheAtomicM; logic CacheFlushM; - assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; + assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; - assign CacheRWM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; - assign CacheAtomicM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSUAtomicM : '0; - assign CacheFlushM = ~TrapM & FlushDCacheM; + assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; + assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0; + assign CacheFlushM = FlushDCacheM; cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusWord, .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .CPUBusy, .SelBusWord, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .FinalWriteData(LSUWriteDataM), .SelHPTW, @@ -260,7 +259,7 @@ module lsu ( .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( - .HCLK(clk), .HRESETn(~reset), + .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .WordCount, .SelBusWord, @@ -303,13 +302,13 @@ module lsu ( logic CaptureEn; logic [1:0] BusRW; logic [`XLEN-1:0] FetchBuffer; - assign BusRW = ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; + assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; // assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{SelDTIM, SelDTIM}; assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; - ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), + ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 6530d12d..d1476db8 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -39,7 +39,7 @@ module lsuvirtmem( output logic DTLBWriteM, input logic InstrDAPageFaultF, input logic DataDAPageFaultM, - input logic TrapM, + input logic FlushW, input logic DCacheStallM, input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -80,11 +80,13 @@ module lsuvirtmem( // move all the muxes to walkermux and instantiate these in lsu under virtmem_supported. assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); - assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM; - assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM; + //assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM; + assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF; + //assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM; + assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM; hptw hptw( - .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, + .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .FlushW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), // *** should it be HPTWReadDataM diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index e2b2573e..52f7e868 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -37,6 +37,7 @@ module hptw input logic [`XLEN-1:0] PCF, // addresses to translate input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate input logic [1:0] MemRWM, AtomicM, + input logic FlushW, // system status input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [1:0] STATUS_MPP, @@ -217,7 +218,14 @@ module hptw end // Page Table Walker FSM - flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + // there is a bug here. Each memory access needs to be potentially flushed if the PMA/P checkers + // generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation. + // I think the solution is to do 1 of the following + // 1. Allow the HPTW to generate exceptions and stop walking immediately. + // 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back + // to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but + // rather than physical address of the translated instruction/data. So we must generate the exception. + flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; @@ -250,3 +258,7 @@ module hptw assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss); endmodule + +// another idea. We keep gating the control by ~TrapM, but this adds considerable length to the critical path. +// should we do this differently? For example TLBMiss is gated by ~TrapM and then drives HPTWStall, which drives LSUStallM, which drives +// the hazard unit to issue stall and flush controlls. ~TrapM already suppresses these in the hazard unit. diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 277ca426..bce17875 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -170,7 +170,7 @@ module wallypipelinedcore ( ifu ifu( .clk, .reset, .StallF, .StallD, .StallE, .StallM, - .FlushF, .FlushD, .FlushE, .FlushM, + .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, // Fetch .HRDATA, .PCF, .IFUHADDR, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, @@ -249,7 +249,7 @@ module wallypipelinedcore ( .FlushW, // CPU interface .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), - .AtomicM, .TrapM, + .AtomicM, .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, .FpLoadStoreM, From e7c25f9562c4be9c8c02b1c2434516535b3f26cf Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 9 Nov 2022 18:41:26 +0000 Subject: [PATCH 03/23] Fixed asign and bsign --- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 756c5cc9..b3d81705 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -67,8 +67,8 @@ module fdivsqrtpreproc ( // ***can probably merge X LZC with conversion // cout the number of leading zeros - assign As = ForwardedSrcAE[`XLEN-1] & Funct3E[0]; - assign Bs = ForwardedSrcBE[`XLEN-1] & Funct3E[0]; + assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0]; + assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0]; assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE; From d5c5450f8d6a7215e6c3be48820e9a97e23e5aa6 Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 9 Nov 2022 18:42:00 +0000 Subject: [PATCH 04/23] Reoredered tests for arch32m --- pipelined/testbench/tests.vh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 633ecb81..8ba3ed2f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1403,12 +1403,12 @@ string imperas32f[] = '{ `RISCVARCHTEST, "rv32i_m/M/src/div-01.S", "rv32i_m/M/src/divu-01.S", + "rv32i_m/M/src/rem-01.S", + "rv32i_m/M/src/remu-01.S", "rv32i_m/M/src/mul-01.S", "rv32i_m/M/src/mulh-01.S", "rv32i_m/M/src/mulhsu-01.S", - "rv32i_m/M/src/mulhu-01.S", - "rv32i_m/M/src/rem-01.S", - "rv32i_m/M/src/remu-01.S" + "rv32i_m/M/src/mulhu-01.S" }; string arch32f[] = '{ From 3653d6b3edfba1b28ced74375bdb7cd45a02880e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Nov 2022 17:43:06 -0600 Subject: [PATCH 05/23] Renamed CACHE_EVICT to CACHE_WRITEBACK. --- pipelined/src/ebu/buscachefsm.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 6965c673..52bd4535 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -64,7 +64,7 @@ module buscachefsm #(parameter integer WordCountThreshold, DATA_PHASE, MEM3, CACHE_FETCH, - CACHE_EVICT} busstatetype; + CACHE_WRITEBACK} busstatetype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; @@ -84,21 +84,21 @@ module buscachefsm #(parameter integer WordCountThreshold, always_comb begin case(CurrState) ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; - else if (HREADY & CacheBusRW[0]) NextState = CACHE_EVICT; + else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; else NextState = ADR_PHASE; DATA_PHASE: if(HREADY) NextState = MEM3; else NextState = DATA_PHASE; MEM3: if(CPUBusy) NextState = MEM3; else NextState = ADR_PHASE; - CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_EVICT; + CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_FETCH; - CACHE_EVICT: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_EVICT; + CACHE_WRITEBACK: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; - else NextState = CACHE_EVICT; + else NextState = CACHE_WRITEBACK; default: NextState = ADR_PHASE; endcase end @@ -121,18 +121,18 @@ module buscachefsm #(parameter integer WordCountThreshold, assign NextWordCount = WordCount + 1'b1; assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0]; - assign WordCntEn = ((NextState == CACHE_EVICT | NextState == CACHE_FETCH) & HREADY) | + assign WordCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) | (NextState == ADR_PHASE & |CacheBusRW & HREADY); assign WordCntReset = NextState == ADR_PHASE; assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY); - assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_EVICT; + assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) | //(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH) | - (CurrState == CACHE_EVICT); + (CurrState == CACHE_WRITEBACK); assign BusCommitted = CurrState != ADR_PHASE; // AHB bus interface @@ -140,7 +140,7 @@ module buscachefsm #(parameter integer WordCountThreshold, (CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; - assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_EVICT & |WordCount); + assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |WordCount); assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |WordCount)) ? LocalBurstType : 3'b0; always_comb begin @@ -157,7 +157,7 @@ module buscachefsm #(parameter integer WordCountThreshold, assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); assign SelBusWord = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | (CurrState == DATA_PHASE & BusRW[0]) | - (CurrState == CACHE_EVICT) | + (CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_FETCH); endmodule From 31d5eabd77138c4888943958704db0eec67c29f9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Nov 2022 17:52:50 -0600 Subject: [PATCH 06/23] Renamed Word to Beat for ahbcacheinterface. --- pipelined/src/cache/cache.sv | 6 +-- pipelined/src/ebu/ahbcacheinterface.sv | 26 +++++----- pipelined/src/ebu/buscachefsm.sv | 68 +++++++++++++------------- pipelined/src/ifu/ifu.sv | 5 +- pipelined/src/lsu/lsu.sv | 18 +++---- 5 files changed, 62 insertions(+), 61 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index dfd64684..0761728b 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -54,8 +54,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Bus fsm interface output logic [1:0] CacheBusRW, input logic CacheBusAck, - input logic SelBusWord, - input logic [LOGBWPL-1:0] WordCount, + input logic SelBusBeat, + input logic [LOGBWPL-1:0] BeatCount, input logic [LINELEN-1:0] FetchBuffer, output logic [`PA_BITS-1:0] CacheBusAdr, output logic [WORDLEN-1:0] ReadDataWord); @@ -143,7 +143,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // like to fix this. if(DCACHE) mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), - .d1(WordCount), .s(SelBusWord), + .d1(BeatCount), .s(SelBusBeat), .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 4600edcd..9b7b8f4b 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) +module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) ( input logic HCLK, HRESETn, @@ -46,7 +46,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE output logic [1:0] HTRANS, output logic HWRITE, output logic [`PA_BITS-1:0] HADDR, - output logic [LOGWPL-1:0] WordCount, + output logic [LOGWPL-1:0] BeatCount, // cache interface input logic [`PA_BITS-1:0] CacheBusAdr, @@ -61,30 +61,30 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE input logic [1:0] BusRW, input logic CPUBusy, input logic [2:0] Funct3, - output logic SelBusWord, + output logic SelBusBeat, output logic BusStall, output logic BusCommitted); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; + localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalHADDR; - logic [LOGWPL-1:0] WordCountDelayed; + logic [LOGWPL-1:0] BeatCountDelayed; logic CaptureEn; genvar index; - for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer - logic [WORDSPERLINE-1:0] CaptureWord; - assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed); - flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA), + for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer + logic [BEATSPERLINE-1:0] CaptureBeat; + assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); + flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); end mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR; mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); - buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( - .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, - .CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed, + buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( + .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, + .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 52bd4535..cddd7487 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -32,7 +32,7 @@ `define BURST_EN 1 // HCLK and clk must be the same clock! -module buscachefsm #(parameter integer WordCountThreshold, +module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOGWPL, parameter logic CACHE_ENABLED ) (input logic HCLK, input logic HRESETn, @@ -50,8 +50,8 @@ module buscachefsm #(parameter integer WordCountThreshold, output logic CacheBusAck, // lsu interface - output logic [LOGWPL-1:0] WordCount, WordCountDelayed, - output logic SelBusWord, + output logic [LOGWPL-1:0] BeatCount, BeatCountDelayed, + output logic SelBusBeat, // BUS interface input logic HREADY, @@ -70,11 +70,11 @@ module buscachefsm #(parameter integer WordCountThreshold, (* mark_debug = "true" *) busstatetype CurrState, NextState; - logic [LOGWPL-1:0] NextWordCount; - logic FinalWordCount; + logic [LOGWPL-1:0] NextBeatCount; + logic FinalBeatCount; logic [2:0] LocalBurstType; - logic WordCntEn; - logic WordCntReset; + logic BeatCntEn; + logic BeatCntReset; logic CacheAccess; always_ff @(posedge HCLK) @@ -91,13 +91,13 @@ module buscachefsm #(parameter integer WordCountThreshold, else NextState = DATA_PHASE; MEM3: if(CPUBusy) NextState = MEM3; else NextState = ADR_PHASE; - CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; - else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; + CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; + else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; + else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_FETCH; - CACHE_WRITEBACK: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; - else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; + CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; + else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; + else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_WRITEBACK; default: NextState = ADR_PHASE; endcase @@ -105,25 +105,25 @@ module buscachefsm #(parameter integer WordCountThreshold, // IEU, LSU, and IFU controls flopenr #(LOGWPL) - WordCountReg(.clk(HCLK), - .reset(~HRESETn | WordCntReset), - .en(WordCntEn), - .d(NextWordCount), - .q(WordCount)); + BeatCountReg(.clk(HCLK), + .reset(~HRESETn | BeatCntReset), + .en(BeatCntEn), + .d(NextBeatCount), + .q(BeatCount)); // Used to store data from data phase of AHB. flopenr #(LOGWPL) - WordCountDelayedReg(.clk(HCLK), - .reset(~HRESETn | WordCntReset), - .en(WordCntEn), - .d(WordCount), - .q(WordCountDelayed)); - assign NextWordCount = WordCount + 1'b1; + BeatCountDelayedReg(.clk(HCLK), + .reset(~HRESETn | BeatCntReset), + .en(BeatCntEn), + .d(BeatCount), + .q(BeatCountDelayed)); + assign NextBeatCount = BeatCount + 1'b1; - assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0]; - assign WordCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) | + assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[LOGWPL-1:0]; + assign BeatCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) | (NextState == ADR_PHASE & |CacheBusRW & HREADY); - assign WordCntReset = NextState == ADR_PHASE; + assign BeatCntReset = NextState == ADR_PHASE; assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY); assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; @@ -137,14 +137,14 @@ module buscachefsm #(parameter integer WordCountThreshold, // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) | - (CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request + (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; - assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |WordCount); - assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |WordCount)) ? LocalBurstType : 3'b0; + assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |BeatCount); + assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin - case(WordCountThreshold) + case(BeatCountThreshold) 0: LocalBurstType = 3'b000; 3: LocalBurstType = 3'b011; // INCR4 7: LocalBurstType = 3'b101; // INCR8 @@ -154,8 +154,8 @@ module buscachefsm #(parameter integer WordCountThreshold, end // communication to cache - assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); - assign SelBusWord = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | + assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount); + assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | (CurrState == DATA_PHASE & BusRW[0]) | (CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_FETCH); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 93804877..41578437 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -205,6 +205,7 @@ module ifu ( assign IFURWF = 2'b10; end if (`BUS) begin : bus + // **** must fix words per line vs beats per line as in lsu. localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; if(`ICACHE) begin : icache @@ -227,7 +228,7 @@ module ifu ( .ReadDataWord(ICacheInstrF), .SelHPTW('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteMask('0), .WordCount('0), .SelBusWord('0), + .ByteMask('0), .BeatCount('0), .SelBusBeat('0), .FinalWriteData('0), .CacheRW(CacheRWF), .CacheAtomic('0), .FlushCache('0), @@ -239,7 +240,7 @@ module ifu ( .HRDATA, .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), - .WordCount(), .Cacheable(CacheableF), .SelBusWord(), + .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .CacheBusAck(ICacheBusAck), .FetchBuffer, .PAdr(PCPF), .BusRW, .CPUBusy, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5be7c931..b7eb3cd0 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -222,17 +222,17 @@ module lsu ( if (`BUS) begin : bus localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1; localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1; - localparam integer AHBWWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; - localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(AHBWWORDSPERLINE) : 1; + localparam integer BEATSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; + localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(BEATSPERLINE) : 1; if(`DCACHE) begin : dcache localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; - logic [AHBWLOGBWPL-1:0] WordCount; + logic [AHBWLOGBWPL-1:0] BeatCount; logic DCacheBusAck; - logic SelBusWord; + logic SelBusBeat; logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; @@ -249,20 +249,20 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusWord, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), - .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), + .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .FinalWriteData(LSUWriteDataM), .SelHPTW, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( + ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), - .WordCount, .SelBusWord, + .BeatCount, .SelBusBeat, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, @@ -284,7 +284,7 @@ module lsu ( for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; end - assign DCacheReadDataWordAHB = AHBWordSets[WordCount[$clog2(LLENPOVERAHBW)-1:0]]; + assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); From 7311eca5ff958c80040348c37611009ee6947492 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Nov 2022 15:48:06 -0600 Subject: [PATCH 07/23] Wavefile update. --- pipelined/regression/wave.do | 345 ++++++++++++++++++----------------- 1 file changed, 177 insertions(+), 168 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 8b58d3f6..56f6972b 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -5,51 +5,50 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate /testbench/dut/core/hzu/FirstUnstalledD -add wave -noupdate /testbench/dut/core/hzu/FirstUnstalledE -add wave -noupdate /testbench/dut/core/hzu/FirstUnstalledM -add wave -noupdate /testbench/dut/core/hzu/FirstUnstalledW -add wave -noupdate /testbench/dut/core/fpu/fpu/XDenormE -add wave -noupdate /testbench/dut/core/fpu/fpu/ZDenormE -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/core/PCF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/core/PCE +add wave -noupdate -expand -group PCS /testbench/dut/core/PCM +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -67,9 +66,9 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW -add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -group {WriteBack stage} /testbench/PCW +add wave -noupdate -group {WriteBack stage} /testbench/InstrW +add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW @@ -133,12 +132,6 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/if add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/core/PCF -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/core/PCE -add wave -noupdate -group PCS /testbench/dut/core/PCM -add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F @@ -157,29 +150,29 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group alu /testbench/dut/core/ieu/dp/alu/A -add wave -noupdate -expand -group alu /testbench/dut/core/ieu/dp/alu/B -add wave -noupdate -expand -group alu /testbench/dut/core/ieu/dp/alu/Result -add wave -noupdate -expand -group alu /testbench/dut/core/ieu/dp/alu/ALUControl -add wave -noupdate -expand -group alu -divider internals -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/Rs1D -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/Rs2D -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/Rs2E -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RdE -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RdW -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/MemReadE -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RegWriteM -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RegWriteW -add wave -noupdate -expand -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -expand -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE -add wave -noupdate -expand -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/dp/IFResultM -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -expand -group Forward /testbench/dut/core/ieu/fw/RdW +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl +add wave -noupdate -group alu -divider internals +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW +add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE +add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE +add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD +add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/ForwardAE +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE @@ -226,9 +219,7 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM @@ -349,10 +340,8 @@ add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelBusWord -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM @@ -401,10 +390,14 @@ add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VI add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissOrDAFaultNoTrapM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissOrDAFaultNoTrapF add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress @@ -440,12 +433,13 @@ add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY -add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uncore/uart/uart/u/LSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate @@ -481,74 +475,87 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF -add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF +add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState +add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 +add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/WordCntEn +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/WordCntReset +add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/Flush +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} @@ -580,30 +587,32 @@ add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/rxfifotimeout add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/rxtimeoutcnt add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/THRE add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/THRE_IP -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/ITLBMissOrDAFaultF -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/DTLBMissOrDAFaultM add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/intrID add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/INTR add wave -noupdate /testbench/dut/uncore/uncore/uart/uart/u/rxfifotimeout -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD1E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD2E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD3E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/MDUE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/W64E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/DivStartE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/DivDoneM -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/X -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/Y -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/Z -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/DivStartE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/DivDoneM +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf add wave -noupdate /testbench/dut/core/fpu/fpu/XE add wave -noupdate /testbench/dut/core/fpu/fpu/YE add wave -noupdate /testbench/dut/core/fpu/fpu/ZE +add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWRW +add wave -noupdate /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate /testbench/dut/core/hzu/IntPendingM +add wave -noupdate /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/CacheBusRW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {775 ns} 0} {{Cursor 3} {190821 ns} 1} {{Cursor 4} {378225 ns} 1} +WaveRestoreCursors {{Cursor 2} {135727 ns} 0} {{Cursor 3} {241584 ns} 1} {{Cursor 4} {378225 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -619,4 +628,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {700 ns} {866 ns} +WaveRestoreZoom {135589 ns} {135925 ns} From c2e3bad3f56aad99d844aa616de7f3ecd89756bd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Nov 2022 16:13:31 -0600 Subject: [PATCH 08/23] Fixed name change in hptw. --- pipelined/src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index b06814c8..67a4f238 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -108,7 +108,7 @@ module hptw ( assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops - flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoFlushW, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) + flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheStallM; flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache From ff410cd849f3f1374a53b6c8a511e97d877d0cd5 Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 11 Nov 2022 00:23:25 +0000 Subject: [PATCH 09/23] Added integer step counter to fsm --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 3f9c7e8a..65ea6cc5 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -74,7 +74,7 @@ module fdivsqrt( fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, - .XNaNE, .YNaNE, + .XNaNE, .YNaNE, .MDUE, .n, .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6..94a19ed3 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -42,7 +42,9 @@ module fdivsqrtfsm( input logic SqrtE, input logic StallE, input logic StallM, - input logic WZero, + input logic WZero, + input logic MDUE, + input logic [`DIVBLEN:0] n, output logic DivDone, output logic DivBusy, output logic SpecialCaseM @@ -93,7 +95,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */ From 90697ef8880c748b6bd844461e4e2ecf4407a70f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Nov 2022 14:30:32 -0600 Subject: [PATCH 10/23] Moved all remaining bus logic from the LSU into ahbcacheinterface. --- pipelined/src/ebu/ahbcacheinterface.sv | 40 ++++++++++++++++++++++---- pipelined/src/ifu/ifu.sv | 6 ++-- pipelined/src/lsu/lsu.sv | 30 ++----------------- 3 files changed, 41 insertions(+), 35 deletions(-) diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 9b7b8f4b..530cdb42 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -40,16 +40,21 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE // bus interface input logic HREADY, - input logic [`XLEN-1:0] HRDATA, + input logic [`AHBW-1:0] HRDATA, output logic [2:0] HSIZE, output logic [2:0] HBURST, output logic [1:0] HTRANS, output logic HWRITE, output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`AHBW/8-1:0] HWSTRB, output logic [LOGWPL-1:0] BeatCount, // cache interface input logic [`PA_BITS-1:0] CacheBusAdr, + input logic [`LLEN-1:0] CacheReadDataWordM, + input logic [`LLEN-1:0] WriteDataM, + input logic CacheableOrFlushCacheM, input logic [1:0] CacheBusRW, output logic CacheBusAck, output logic [LINELEN-1:0] FetchBuffer, @@ -65,23 +70,48 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE output logic BusStall, output logic BusCommitted); + localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu. + localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalHADDR; logic [LOGWPL-1:0] BeatCountDelayed; logic CaptureEn; + logic [`AHBW-1:0] PreHWDATA; genvar index; for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); + flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW])); end mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR; + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); + + // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. + logic [`AHBW-1:0] CacheReadDataWordAHB; + if(LLENPOVERAHBW > 1) begin + logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + genvar index; + for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux + assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; + end + assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; + mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), + .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); + flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + + // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. + // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. + logic [`AHBW/8-1:0] BusByteMaskM; + swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); + + flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); + buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 41578437..0798d25f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -238,10 +238,10 @@ module ifu ( ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, - .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), + .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), - .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), - .CacheBusAck(ICacheBusAck), + .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), + .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), .FetchBuffer, .PAdr(PCPF), .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedF)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e66fb35a..6ac9bf4f 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -233,7 +233,6 @@ module lsu ( logic [AHBWLOGBWPL-1:0] BeatCount; logic DCacheBusAck; logic SelBusBeat; - logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; localparam integer LLENPOVERAHBW = `LLEN / `AHBW; @@ -260,10 +259,10 @@ module lsu ( .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), - .HRDATA, + .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), - .BeatCount, .SelBusBeat, - .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, + .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM), + .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); @@ -275,29 +274,6 @@ module lsu ( mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}), .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM)); - - // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [`AHBW-1:0] DCacheReadDataWordAHB; - if(LLENPOVERAHBW > 1) begin - logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; - genvar index; - for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; - end - assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; - mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), - .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - - flopen #(`AHBW) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec - - // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. - // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - logic [`AHBW/8-1:0] BusByteMaskM; - swbytemask #(`AHBW) busswbytemask(.Size(LSUHSIZE), .Adr(PAdrM[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); - - flop #(`AHBW/8) HWSTRBReg(clk, BusByteMaskM[`AHBW/8-1:0], LSUHWSTRB); - end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn; logic [1:0] BusRW; From 0502b8ea4d8cb489f3bf7b0723cfa12ec16af6d9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Nov 2022 04:17:37 -0800 Subject: [PATCH 11/23] Comments about division hazards --- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 1 + pipelined/src/hazard/hazard.sv | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6..c64dbc87 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -118,6 +118,7 @@ module fdivsqrtfsm( end end + // *** start logic is presently in fctl. Make it look more like integer division start logic assign DivDone = (state == DONE) | (WZero & (state == BUSY)); assign DivBusy = (state == BUSY & ~DivDone); diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0ca3c5bc..4eba6700 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -70,7 +70,7 @@ module hazard( // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE? - assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); + assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE in execute stage assign #1 StallF = StallFCause | StallD; assign #1 StallD = StallDCause | StallE; From 157f816cd3de803c7a2ba3efe6e9375106ebaacd Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Nov 2022 04:23:23 -0800 Subject: [PATCH 12/23] HPTW cleanup --- pipelined/src/mmu/hptw.sv | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index f348d1fd..746c7d58 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -104,14 +104,15 @@ module hptw ( assign TLBMiss = (DTLBMissOrDAFaultNoTrapM | ITLBMissOrDAFaultNoTrapF); // Determine which address to translate - assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; + mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); + //assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops - flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) - assign PRegEn = HPTWRW[1] & ~DCacheStallM; - - flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache + assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE; + flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) + + flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache // Assign PTE descriptors common across all XLEN values @@ -282,11 +283,8 @@ module hptw ( assign CPUBusy = StallW & ~SelHPTW; // multiplex the outputs to LSU - if(`XLEN+2-`PA_BITS > 0) begin // *** replace with XLEN=32 - logic [(`XLEN+2-`PA_BITS)-1:0] zeros; - assign zeros = '0; - assign HPTWAdrExt = {zeros, HPTWAdr}; - end else assign HPTWAdrExt = HPTWAdr; + if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits + else assign HPTWAdrExt = HPTWAdr; mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M); mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); From a27b81ef9078395e77671b7e065493e8e2bb3f44 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Nov 2022 12:27:48 -0600 Subject: [PATCH 13/23] Changed IMWriteDataM to IHWriteDataM. --- pipelined/src/lsu/atomic.sv | 6 +++--- pipelined/src/lsu/lsu.sv | 10 +++++----- pipelined/src/mmu/hptw.sv | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index dc51b52e..adb15940 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -34,7 +34,7 @@ module atomic ( input logic clk, input logic reset, StallW, input logic [`XLEN-1:0] ReadDataM, - input logic [`XLEN-1:0] IMWriteDataM, + input logic [`XLEN-1:0] IHWriteDataM, input logic [`PA_BITS-1:0] PAdrM, input logic [6:0] LSUFunct7M, input logic [2:0] LSUFunct3M, @@ -48,9 +48,9 @@ module atomic ( logic [`XLEN-1:0] AMOResult; logic MemReadM; - amoalu amoalu(.srca(ReadDataM), .srcb(IMWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), + amoalu amoalu(.srca(ReadDataM), .srcb(IHWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), .result(AMOResult)); - mux2 #(`XLEN) wdmux(IMWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM); + mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM); assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 6ac9bf4f..1894eec6 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -111,7 +111,7 @@ module lsu ( logic IgnoreRequestTLB; logic BusCommittedM, DCacheCommittedM; logic DataDAPageFaultM; - logic [`XLEN-1:0] IMWriteDataM, IMAWriteDataM; + logic [`XLEN-1:0] IHWriteDataM, IMAWriteDataM; logic [`LLEN-1:0] IMAFWriteDataM; logic [`LLEN-1:0] ReadDataM; logic [(`LLEN-1)/8:0] ByteMaskM; @@ -133,7 +133,7 @@ module lsu ( .FlushW, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, - .IEUAdrExtM, .PTE, .IMWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, + .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IHAdrM, .CPUBusy, .HPTWStall, .SelHPTW, .IgnoreRequestTLB); end else begin @@ -141,7 +141,7 @@ module lsu ( assign CPUBusy = StallW; assign PreLSURWM = MemRWM; assign IHAdrM = IEUAdrExtM; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; - assign IMWriteDataM = WriteDataM; + assign IHWriteDataM = WriteDataM; end // CommittedM tells the CPU's privilege unit the current instruction @@ -306,11 +306,11 @@ module lsu ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// if (`A_SUPPORTED) begin:atomic - atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .IMWriteDataM, .PAdrM, + atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .IHWriteDataM, .PAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .IMAWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc - assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IMWriteDataM; + assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM; end if (`F_SUPPORTED) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 8e2d3908..eede21e7 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -55,7 +55,7 @@ module hptw ( (* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry output logic [1:0] PreLSURWM, output logic [`XLEN+1:0] IHAdrM, - output logic [`XLEN-1:0] IMWriteDataM, + output logic [`XLEN-1:0] IHWriteDataM, output logic [1:0] LSUAtomicM, output logic [2:0] LSUFunct3M, output logic [6:0] LSUFunct7M, @@ -295,8 +295,8 @@ module hptw ( mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM); if(`HPTW_WRITES_SUPPORTED) - mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IMWriteDataM); - else assign IMWriteDataM = WriteDataM; + mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM); + else assign IHWriteDataM = WriteDataM; endmodule From 9c70ab917c36ab007f67c07c6de01fe3c2ec4d5c Mon Sep 17 00:00:00 2001 From: cturek Date: Sun, 13 Nov 2022 22:40:26 +0000 Subject: [PATCH 14/23] Added A Date: Sun, 13 Nov 2022 23:02:43 +0000 Subject: [PATCH 15/23] Added flops for n and m, added B=0 signal --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 8 ++++---- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 20 +++++++++++-------- 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index f5cf2e3f..2362b987 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -64,13 +64,13 @@ module fdivsqrt( logic Firstun; logic WZero; logic SpecialCaseM; - logic [`DIVBLEN:0] n, p, m, L; - logic OTFCSwap, ALTB; + logic [`DIVBLEN:0] n, m; + logic OTFCSwap, ALTB, BZero; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, - .n, .p, .m, .L, .OTFCSwap, .ALTB, + .n, .m, .OTFCSwap, .ALTB, .BZero, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, @@ -85,6 +85,6 @@ module fdivsqrt( fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), - .MDUE, .n, .ALTB, .m, + .MDUE, .n, .ALTB, .m, .BZero, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 44c7f901..716f1225 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,7 +38,7 @@ module fdivsqrtpostproc( input logic Firstun, input logic SqrtM, input logic SpecialCaseM, - input logic RemOp, MDUE, ALTB, + input logic RemOp, MDUE, ALTB, BZero, input logic [`DIVBLEN:0] n, m, output logic [`DIVb:0] QmM, output logic WZero, @@ -70,7 +70,7 @@ module fdivsqrtpostproc( end assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide - + // Determine if sticky bit is negative assign W = WC + WS; diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 0ee67019..3d2f529a 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -41,8 +41,8 @@ module fdivsqrtpreproc ( input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [2:0] Funct3E, Funct3M, input logic MDUE, W64E, - output logic [`DIVBLEN:0] n, p, m, L, - output logic OTFCSwap, ALTB, + output logic [`DIVBLEN:0] n, m, + output logic OTFCSwap, ALTB, BZero, output logic [`NE+1:0] QeM, output logic [`DIVb+3:0] X, output logic [`DIVN-2:0] Dpreproc @@ -58,8 +58,9 @@ module fdivsqrtpreproc ( logic [`XLEN-1:0] PosA, PosB; logic As, Bs, OTFCSwapTemp; logic [`XLEN-1:0] A64, B64; + logic [`DIVBLEN:0] Calcn, Calcm; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; - logic [`DIVBLEN:0] pPlusr, pPrCeil; + logic [`DIVBLEN:0] pPlusr, pPrCeil, p, L; logic [`LOGRK-1:0] pPrTrunc; logic [`DIVb+3:0] PreShiftX; @@ -75,23 +76,24 @@ module fdivsqrtpreproc ( assign PosA = As ? -A64 : A64; assign PosB = Bs ? -B64 : B64; + assign BZero = |ForwardedSrcBE; assign ZeroBufX = MDUE ? {PosA, {`DIVb-`XLEN{1'b0}}} : {Xm, {`DIVb-`NF-1{1'b0}}}; assign ZeroBufY = MDUE ? {PosB, {`DIVb-`XLEN{1'b0}}} : {Ym, {`DIVb-`NF-1{1'b0}}}; lzc #(`DIVb) lzcX (ZeroBufX, L); - lzc #(`DIVb) lzcY (ZeroBufY, m); + lzc #(`DIVb) lzcY (ZeroBufY, Calcm); assign PreprocX = Xm[`NF-1:0]<> `LOGRK) + {{`DIVBLEN-1{1'b0}}, |(pPrTrunc)}; - assign n = (pPrCeil << `LOGK) - 1; + assign Calcn = (pPrCeil << `LOGK) - 1; assign IntBits = (`DIVBLEN)'(`RK) + p; assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]}; @@ -115,7 +117,9 @@ module fdivsqrtpreproc ( // DIVRESLEN/(r*`DIVCOPIES) flopen #(`NE+2) expflop(clk, DivStartE, Qe, QeM); flopen #(1) swapflop(clk, DivStartE, OTFCSwapTemp, OTFCSwap); - expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m, .Qe); + flopen #(`DIVBLEN+1) nflop(clk, DivStartE, Calcn, n); + flopen #(`DIVBLEN+1) mflop(clk, DivStartE, Calcm, m); + expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m(Calcm), .Qe); endmodule From 74f58b5d895f0ca5e87e1a6d841d9af3f90e30a1 Mon Sep 17 00:00:00 2001 From: cturek Date: Sun, 13 Nov 2022 23:44:34 +0000 Subject: [PATCH 16/23] Added Quotient/Remainder calcs to normal termination --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 6 ++-- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 32 ++++++++++++++++--- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 +-- 3 files changed, 33 insertions(+), 9 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 2362b987..14e7cfa9 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -65,12 +65,12 @@ module fdivsqrt( logic WZero; logic SpecialCaseM; logic [`DIVBLEN:0] n, m; - logic OTFCSwap, ALTB, BZero; + logic OTFCSwap, ALTB, BZero, As; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, - .n, .m, .OTFCSwap, .ALTB, .BZero, + .n, .m, .OTFCSwap, .ALTB, .BZero, .As, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, @@ -85,6 +85,6 @@ module fdivsqrt( fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), - .MDUE, .n, .ALTB, .m, .BZero, + .MDUE, .n, .ALTB, .m, .BZero, .As, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 716f1225..65b68883 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,16 +38,16 @@ module fdivsqrtpostproc( input logic Firstun, input logic SqrtM, input logic SpecialCaseM, - input logic RemOp, MDUE, ALTB, BZero, + input logic RemOp, MDUE, ALTB, BZero, As, input logic [`DIVBLEN:0] n, m, output logic [`DIVb:0] QmM, output logic WZero, output logic DivSM ); - logic [`DIVb+3:0] W; + logic [`DIVb+3:0] W, Sum; logic [`DIVb:0] PreQmM; - logic NegSticky; + logic NegSticky, PostInc; logic weq0; logic [`DIVb:0] IntQuot, IntRem; @@ -73,9 +73,33 @@ module fdivsqrtpostproc( // Determine if sticky bit is negative - assign W = WC + WS; + assign Sum = WC + WS; + assign W = $signed(Sum) >>> `LOGR; assign NegSticky = W[`DIVb+3]; + assign RemD = {4'b0000, D, {(`DIVb-`DIVN){1'b0}}}; + always_comb + if (~As) + if (NegSticky) begin + assign IntQuot = FirstUM; + assign IntRem = W + RemD; + assign PostInc = 0; + end else begin + assign IntQuot = FirstU; + assign IntRem = W; + assign PostInc = 0; + end + else + if (NegSticky | weq0) begin + assign IntQuot = FirstU; + assign IntRem = W; + assign PostInc = 0; + end else begin + assign IntQuot = FirstU; + assign IntRem = W - RemD; + assign PostInc = 1; + end + // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 3d2f529a..af6a8617 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -42,7 +42,7 @@ module fdivsqrtpreproc ( input logic [2:0] Funct3E, Funct3M, input logic MDUE, W64E, output logic [`DIVBLEN:0] n, m, - output logic OTFCSwap, ALTB, BZero, + output logic OTFCSwap, ALTB, BZero, As, output logic [`NE+1:0] QeM, output logic [`DIVb+3:0] X, output logic [`DIVN-2:0] Dpreproc @@ -56,7 +56,7 @@ module fdivsqrtpreproc ( // Intdiv signals logic [`DIVb-1:0] ZeroBufX, ZeroBufY; logic [`XLEN-1:0] PosA, PosB; - logic As, Bs, OTFCSwapTemp; + logic Bs, OTFCSwapTemp; logic [`XLEN-1:0] A64, B64; logic [`DIVBLEN:0] Calcn, Calcm; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; From 0b2c8b9d460932525b6484de1e48b57837aa7f75 Mon Sep 17 00:00:00 2001 From: cturek Date: Mon, 14 Nov 2022 00:06:38 +0000 Subject: [PATCH 17/23] Added majority of combinational logic --- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 57 +++++++++++++++---- 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 65b68883..8f208764 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -49,7 +49,9 @@ module fdivsqrtpostproc( logic [`DIVb:0] PreQmM; logic NegSticky, PostInc; logic weq0; - logic [`DIVb:0] IntQuot, IntRem; + logic [`DIVBLEN:0] NormShift; + logic [`DIVb:0] IntQuot, IntRem, NormQuot, NormRem; + logic [`DIVb:0] PreResult, Result; // check for early termination on an exact result. If the result is not exact, the sticky should be set aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); @@ -70,8 +72,6 @@ module fdivsqrtpostproc( end assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide - - // Determine if sticky bit is negative assign Sum = WC + WS; assign W = $signed(Sum) >>> `LOGR; @@ -81,27 +81,62 @@ module fdivsqrtpostproc( always_comb if (~As) if (NegSticky) begin - assign IntQuot = FirstUM; - assign IntRem = W + RemD; + assign NormQuot = FirstUM; + assign NormRem = W + RemD; assign PostInc = 0; end else begin - assign IntQuot = FirstU; - assign IntRem = W; + assign NormQuot = FirstU; + assign NormRem = W; assign PostInc = 0; end else if (NegSticky | weq0) begin - assign IntQuot = FirstU; - assign IntRem = W; + assign NormQuot = FirstU; + assign NormRem = W; assign PostInc = 0; end else begin - assign IntQuot = FirstU; - assign IntRem = W - RemD; + assign NormQuot = FirstU; + assign NormRem = W - RemD; assign PostInc = 1; end + +/* + always_comb + if(ALTB) begin + assign IntQuot = '0; + assign IntRem = ForwardedSrcAE; + end else if (BZero) begin + assign IntQuot = '1; + assign IntRem = ForwardedSrcAE; + end else if (EarlyTerm) begin + if (weq0) begin + assign IntQuot = FirstU; + assign IntRem = '0; + end else begin + assign IntQuot = FirstUM; + assign IntRem = '0; + end + end else begin + assign IntQuot = NormQuot; + assign IntRem = NormRem; + end + */ + /* + always_comb + if (RemOp) begin + assign NormShift = m + (`DIVBLEN)'(`DIVa); + assign PreResult = IntRem; + end else begin + assign NormShift = DIVb - (j << `LOGR); + assign PreResult = IntQuot; + end + */ + // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted + assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp); + assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; endmodule \ No newline at end of file From 5800dfde60a82ecde6802618dd2ca30a1ef971fc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Nov 2022 21:34:45 -0600 Subject: [PATCH 18/23] Updated wave file. --- pipelined/regression/wave.do | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 56f6972b..ed41ea6e 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -385,15 +385,15 @@ add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpch add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissOrDAFaultNoTrapM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissOrDAFaultNoTrapF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCF +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWReadPTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBMissOrDAFaultNoTrapM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBMissOrDAFaultNoTrapF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt @@ -607,7 +607,7 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf add wave -noupdate /testbench/dut/core/fpu/fpu/XE add wave -noupdate /testbench/dut/core/fpu/fpu/YE add wave -noupdate /testbench/dut/core/fpu/fpu/ZE -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWRW +add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWRW add wave -noupdate /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate /testbench/dut/core/hzu/IntPendingM add wave -noupdate /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/CacheBusRW From 1a00e7bbeef2e89f8170f6f58163a30146990bf5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Nov 2022 21:36:12 -0600 Subject: [PATCH 19/23] Changed names of cache signals. --- pipelined/regression/fpga-wave.do | 2 +- pipelined/regression/wave.do | 2 +- pipelined/src/cache/cache.sv | 14 +++++++------- pipelined/src/cache/cacheway.sv | 4 ++-- pipelined/src/generic/mem/sram1p1rw.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index 41c3a2f0..f2f4ee11 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -318,7 +318,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ed41ea6e..99112e4c 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -345,7 +345,7 @@ add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /t add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 0761728b..ec1ab794 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -43,7 +43,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address input logic [(WORDLEN-1)/8:0] ByteMask, - input logic [WORDLEN-1:0] FinalWriteData, + input logic [WORDLEN-1:0] CacheWriteData, output logic CacheCommitted, output logic CacheStall, // to performance counters to cpu @@ -71,7 +71,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic SelAdr; logic [SETLEN-1:0] RAdr; - logic [LINELEN-1:0] CacheWriteData; + logic [LINELEN-1:0] LineWriteData; logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; @@ -124,7 +124,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) - CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .CacheWriteData, .LineByteMask, + CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush, .Invalidate(InvalidateCache)); @@ -156,8 +156,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - logic [LINELEN-1:0] FinalWriteDataDup; - assign FinalWriteDataDup = {WORDSPERLINE{FinalWriteData}}; + logic [LINELEN-1:0] CacheWriteDataDup; + assign CacheWriteDataDup = {WORDSPERLINE{CacheWriteData}}; onehotdecoder #(LOGCWPL) adrdec( .bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); @@ -169,8 +169,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE assign LineByteMask = ~SetValid & ~SetDirty ? '0 : ~SetValid & SetDirty ? DemuxedByteMask : '1; // if store hit only enable the word and subword bytes, else write all bytes. for(index = 0; index < LINELEN/8; index++) begin - mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]), - .d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index])); + mux2 #(8) WriteDataMux(.d0(CacheWriteDataDup[8*index+7:8*index]), + .d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(LineWriteData[8*index+7:8*index])); end mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 4776aeaf..7401a53a 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -38,7 +38,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, - input logic [LINELEN-1:0] CacheWriteData, + input logic [LINELEN-1:0] LineWriteData, input logic SetValidWay, input logic ClearValidWay, input logic SetDirtyWay, @@ -109,7 +109,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, for(words = 0; words < NUMSRAM; words++) begin: word sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), - .din(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), + .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/sram1p1rw.sv index b4aec922..7dd3ec0e 100644 --- a/pipelined/src/generic/mem/sram1p1rw.sv +++ b/pipelined/src/generic/mem/sram1p1rw.sv @@ -3,7 +3,7 @@ // // Written: ross1728@gmail.com May 3, 2021 // Basic sram with 1 read write port. -// When clk rises Addr and CacheWriteData are sampled. +// When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. // Write // diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 0798d25f..65526977 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -229,7 +229,7 @@ module ifu ( .SelHPTW('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .ByteMask('0), .BeatCount('0), .SelBusBeat('0), - .FinalWriteData('0), + .CacheWriteData('0), .CacheRW(CacheRWF), .CacheAtomic('0), .FlushCache('0), .NextAdr(PCNextFSpill[11:0]), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1894eec6..cd4846e5 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -251,7 +251,7 @@ module lsu ( .clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), - .FinalWriteData(LSUWriteDataM), .SelHPTW, + .CacheWriteData(LSUWriteDataM), .SelHPTW, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), From 79d416537a101137e4c9255f3e50dd91fe402c0b Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Nov 2022 09:52:21 -0800 Subject: [PATCH 20/23] Removed comment about nonexistent possible bug --- pipelined/src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 746c7d58..69fc07b1 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -224,7 +224,7 @@ module hptw ( if (`XLEN == 32) begin assign InitialWalkerState = L1_ADR; assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 - // *** Possible bug - should be L1_ADR? + // *** Possible bug - should be L1_ADR? If so, applies to 64 bits as well assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); end else begin logic GigapageMisaligned, TerapageMisaligned; From 895ee3d773ee8d70c16b1d8ef4d1f0b7d3a57ba5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Nov 2022 09:56:33 -0800 Subject: [PATCH 21/23] Removed comment about nonexistent possible bug --- pipelined/src/mmu/hptw.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 46f7806a..bcbefae5 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -223,7 +223,6 @@ module hptw ( if (`XLEN == 32) begin assign InitialWalkerState = L1_ADR; assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 - // *** Possible bug - should be L1_ADR? If so, applies to 64 bits as well assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); end else begin logic GigapageMisaligned, TerapageMisaligned; From f03d5d3ac8a6a3c895509c72ed17620b2db886a9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 14 Nov 2022 14:11:05 -0600 Subject: [PATCH 22/23] Renamed Flush to FlushStage in the cache. --- pipelined/src/cache/cache.sv | 8 ++++---- pipelined/src/cache/cachefsm.sv | 4 ++-- pipelined/src/cache/cacheway.sv | 14 +++++++------- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index ec1ab794..6fe11f35 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -34,7 +34,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic clk, input logic reset, // cpu side - input logic Flush, + input logic FlushStage, input logic CPUBusy, input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, @@ -126,11 +126,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, - .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush, + .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, .Invalidate(InvalidateCache)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~Flush)); + .clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage)); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; @@ -207,7 +207,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .Flush, .CacheRW, .CacheAtomic, .CPUBusy, + .FlushStage, .CacheRW, .CacheAtomic, .CPUBusy, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index edbf6f99..f20c1fec 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -34,7 +34,7 @@ module cachefsm (input logic clk, input logic reset, // inputs from IEU - input logic Flush, + input logic FlushStage, input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, input logic FlushCache, @@ -111,7 +111,7 @@ module cachefsm flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); always_ff @(posedge clk) - if (reset | Flush) CurrState <= #1 STATE_READY; + if (reset | FlushStage) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; always_comb begin diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 7401a53a..470cece1 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -48,7 +48,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, - input logic Flush, + input logic FlushStage, // input logic [(`XLEN-1)/8:0] ByteMask, input logic [LINELEN/8-1:0] LineByteMask, @@ -87,7 +87,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce, .addr(RAdr), .dout(ReadTag), .bwe('1), - .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~Flush)); + .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~FlushStage)); // AND portion of distributed tag multiplexer mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); @@ -110,7 +110,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), - .we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); + .we(SelectedWriteWordEn & ~FlushStage), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end // AND portion of distributed read multiplexers @@ -124,8 +124,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, always_ff @(posedge clk) begin // Valid bit array, if (reset | Invalidate) ValidBits <= #1 '0; if(ce) begin Valid <= #1 ValidBits[RAdr]; - if (SetValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b1; - else if (ClearValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b0; + if (SetValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b1; + else if (ClearValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b0; end end @@ -139,8 +139,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; if(ce) begin Dirty <= #1 DirtyBits[RAdr]; - if (SetDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b1; - else if (ClearDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b0; + if (SetDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b1; + else if (ClearDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b0; end end end else assign Dirty = 1'b0; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 65526977..ee271fe1 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -221,7 +221,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .Flush(FlushW), .CPUBusy, + icache(.clk, .reset, .FlushStage(FlushW), .CPUBusy, .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index cd4846e5..3747dece 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -248,7 +248,7 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .CPUBusy, .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW, From ec6517fadd2bf045befbb6268cc7ae18e5e00218 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 14 Nov 2022 16:02:20 -0600 Subject: [PATCH 23/23] Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state. --- pipelined/src/mmu/hptw.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index bcbefae5..6edf983d 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -262,9 +262,9 @@ module hptw ( else NextWalkerState = LEAF; L0_RD: if (DCacheStallM) NextWalkerState = L0_RD; else NextWalkerState = LEAF; - LEAF: if (DAPageFault) NextWalkerState = UPDATE_PTE; + LEAF: if (`HPTW_WRITES_SUPPORTED & DAPageFault) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; - UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) NextWalkerState = UPDATE_PTE; + UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE; else NextWalkerState = LEAF; default: NextWalkerState = IDLE; // should never be reached endcase // case (WalkerState)