From 4a17b2e4ed857bc562f12d848e7abcfd44bfb346 Mon Sep 17 00:00:00 2001
From: Kip Macsai-Goren <kipmacsaigoren@gmail.com>
Date: Mon, 21 Feb 2022 07:14:42 +0000
Subject: [PATCH] made sure program isn't passing the testwith a false
 posistive

---
 .../privilege/src/WALLY-CSR-permission-s-01.S | 274 +++++++++---------
 .../privilege/src/WALLY-CSR-permission-u-01.S | 224 +++++++-------
 .../privilege/src/WALLY-CSR-permission-s-01.S | 202 ++++++-------
 .../privilege/src/WALLY-CSR-permission-u-01.S | 224 +++++++-------
 .../rv64i_m/privilege/src/WALLY-minfo-01.S    |   2 +-
 .../rv64i_m/privilege/src/WALLY-misa-01.S     |   2 +-
 6 files changed, 464 insertions(+), 464 deletions(-)

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
index 2464e928..522fb6d0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
@@ -34,161 +34,161 @@ s_file_begin:
 
 GOTO_S_MODE 0x0, 0x0
 
-# Attempt to write 0xbad to each of these CSRs and read the value back
+# Attempt to write 0x111 to each of these CSRs and read the value back
 # should result in an illegal instruction for the write and read, respectively
 
 # High-bit versions storing the upper 32 bits of some CSRs for RV32
-# WRITE_READ_CSR mstatush 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR menvcfgh 0xbad
-# WRITE_READ_CSR mseccfgh 0xbad
-WRITE_READ_CSR pmpcfg1 0xbad
-WRITE_READ_CSR pmpcfg3 0xbad
-WRITE_READ_CSR mcycleh 0xbad
-WRITE_READ_CSR minstreth 0xbad
-WRITE_READ_CSR mhpmcounter3h 0xbad
-WRITE_READ_CSR mhpmcounter4h 0xbad
-WRITE_READ_CSR mhpmcounter5h 0xbad
-WRITE_READ_CSR mhpmcounter6h 0xbad
-WRITE_READ_CSR mhpmcounter7h 0xbad
-WRITE_READ_CSR mhpmcounter8h 0xbad
-WRITE_READ_CSR mhpmcounter9h 0xbad
-WRITE_READ_CSR mhpmcounter10h 0xbad
-WRITE_READ_CSR mhpmcounter11h 0xbad
-WRITE_READ_CSR mhpmcounter12h 0xbad
-WRITE_READ_CSR mhpmcounter13h 0xbad
-WRITE_READ_CSR mhpmcounter14h 0xbad
-WRITE_READ_CSR mhpmcounter15h 0xbad
-WRITE_READ_CSR mhpmcounter16h 0xbad
-WRITE_READ_CSR mhpmcounter17h 0xbad
-WRITE_READ_CSR mhpmcounter18h 0xbad
-WRITE_READ_CSR mhpmcounter19h 0xbad
-WRITE_READ_CSR mhpmcounter20h 0xbad
-WRITE_READ_CSR mhpmcounter21h 0xbad
-WRITE_READ_CSR mhpmcounter22h 0xbad
-WRITE_READ_CSR mhpmcounter23h 0xbad
-WRITE_READ_CSR mhpmcounter24h 0xbad
-WRITE_READ_CSR mhpmcounter25h 0xbad
-WRITE_READ_CSR mhpmcounter26h 0xbad
-WRITE_READ_CSR mhpmcounter27h 0xbad
-WRITE_READ_CSR mhpmcounter28h 0xbad
-WRITE_READ_CSR mhpmcounter29h 0xbad
-WRITE_READ_CSR mhpmcounter30h 0xbad
-WRITE_READ_CSR mhpmcounter31h 0xbad
+# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR menvcfgh 0x111
+# WRITE_READ_CSR mseccfgh 0x111
+WRITE_READ_CSR pmpcfg1 0x111
+WRITE_READ_CSR pmpcfg3 0x111
+WRITE_READ_CSR mcycleh 0x111
+WRITE_READ_CSR minstreth 0x111
+WRITE_READ_CSR mhpmcounter3h 0x111
+WRITE_READ_CSR mhpmcounter4h 0x111
+WRITE_READ_CSR mhpmcounter5h 0x111
+WRITE_READ_CSR mhpmcounter6h 0x111
+WRITE_READ_CSR mhpmcounter7h 0x111
+WRITE_READ_CSR mhpmcounter8h 0x111
+WRITE_READ_CSR mhpmcounter9h 0x111
+WRITE_READ_CSR mhpmcounter10h 0x111
+WRITE_READ_CSR mhpmcounter11h 0x111
+WRITE_READ_CSR mhpmcounter12h 0x111
+WRITE_READ_CSR mhpmcounter13h 0x111
+WRITE_READ_CSR mhpmcounter14h 0x111
+WRITE_READ_CSR mhpmcounter15h 0x111
+WRITE_READ_CSR mhpmcounter16h 0x111
+WRITE_READ_CSR mhpmcounter17h 0x111
+WRITE_READ_CSR mhpmcounter18h 0x111
+WRITE_READ_CSR mhpmcounter19h 0x111
+WRITE_READ_CSR mhpmcounter20h 0x111
+WRITE_READ_CSR mhpmcounter21h 0x111
+WRITE_READ_CSR mhpmcounter22h 0x111
+WRITE_READ_CSR mhpmcounter23h 0x111
+WRITE_READ_CSR mhpmcounter24h 0x111
+WRITE_READ_CSR mhpmcounter25h 0x111
+WRITE_READ_CSR mhpmcounter26h 0x111
+WRITE_READ_CSR mhpmcounter27h 0x111
+WRITE_READ_CSR mhpmcounter28h 0x111
+WRITE_READ_CSR mhpmcounter29h 0x111
+WRITE_READ_CSR mhpmcounter30h 0x111
+WRITE_READ_CSR mhpmcounter31h 0x111
 
 # Machine information Registers
-WRITE_READ_CSR mvendorid, 0xbad
-WRITE_READ_CSR marchid, 0xbad
-WRITE_READ_CSR mimpid, 0xbad
-WRITE_READ_CSR mhartid, 0xbad
-# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
+WRITE_READ_CSR mvendorid, 0x111
+WRITE_READ_CSR marchid, 0x111
+WRITE_READ_CSR mimpid, 0x111
+WRITE_READ_CSR mhartid, 0x111
+# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
-WRITE_READ_CSR mstatus, 0xbad
-WRITE_READ_CSR misa, 0xbad
-WRITE_READ_CSR medeleg, 0xbad
-WRITE_READ_CSR mideleg, 0xbad
-WRITE_READ_CSR mie, 0xbad
-WRITE_READ_CSR mtvec, 0xbad
-WRITE_READ_CSR mcounteren, 0xbad
+WRITE_READ_CSR mstatus, 0x111
+WRITE_READ_CSR misa, 0x111
+WRITE_READ_CSR medeleg, 0x111
+WRITE_READ_CSR mideleg, 0x111
+WRITE_READ_CSR mie, 0x111
+WRITE_READ_CSR mtvec, 0x111
+WRITE_READ_CSR mcounteren, 0x111
 
 # Machine Trap Handling
-WRITE_READ_CSR mscratch, 0xbad
-WRITE_READ_CSR mepc, 0xbad
-WRITE_READ_CSR mcause, 0xbad
-WRITE_READ_CSR mtval, 0xbad
-WRITE_READ_CSR mip, 0xbad
-# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mtval2, 0xbad
+WRITE_READ_CSR mscratch, 0x111
+WRITE_READ_CSR mepc, 0x111
+WRITE_READ_CSR mcause, 0x111
+WRITE_READ_CSR mtval, 0x111
+WRITE_READ_CSR mip, 0x111
+# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0x111
 
 # Machine Configuration
-# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mseccgf, 0xbad
+# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0x111
 
 # Machine Memory Protection
-WRITE_READ_CSR pmpcfg0, 0xbad
-WRITE_READ_CSR pmpcfg2, 0xbad # there's 1 pmpcfg reg per 8 pmpaddr regs 
+WRITE_READ_CSR pmpcfg0, 0x111
+WRITE_READ_CSR pmpcfg2, 0x111 # there's 1 pmpcfg reg per 8 pmpaddr regs 
 
-WRITE_READ_CSR pmpaddr0, 0xbad
-WRITE_READ_CSR pmpaddr1, 0xbad
-WRITE_READ_CSR pmpaddr2, 0xbad
-WRITE_READ_CSR pmpaddr3, 0xbad
-WRITE_READ_CSR pmpaddr4, 0xbad
-WRITE_READ_CSR pmpaddr5, 0xbad
-WRITE_READ_CSR pmpaddr6, 0xbad
-WRITE_READ_CSR pmpaddr7, 0xbad
-WRITE_READ_CSR pmpaddr8, 0xbad
-WRITE_READ_CSR pmpaddr9, 0xbad
-WRITE_READ_CSR pmpaddr10, 0xbad
-WRITE_READ_CSR pmpaddr11, 0xbad
-WRITE_READ_CSR pmpaddr12, 0xbad
-WRITE_READ_CSR pmpaddr13, 0xbad
-WRITE_READ_CSR pmpaddr14, 0xbad
-WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
+WRITE_READ_CSR pmpaddr0, 0x111
+WRITE_READ_CSR pmpaddr1, 0x111
+WRITE_READ_CSR pmpaddr2, 0x111
+WRITE_READ_CSR pmpaddr3, 0x111
+WRITE_READ_CSR pmpaddr4, 0x111
+WRITE_READ_CSR pmpaddr5, 0x111
+WRITE_READ_CSR pmpaddr6, 0x111
+WRITE_READ_CSR pmpaddr7, 0x111
+WRITE_READ_CSR pmpaddr8, 0x111
+WRITE_READ_CSR pmpaddr9, 0x111
+WRITE_READ_CSR pmpaddr10, 0x111
+WRITE_READ_CSR pmpaddr11, 0x111
+WRITE_READ_CSR pmpaddr12, 0x111
+WRITE_READ_CSR pmpaddr13, 0x111
+WRITE_READ_CSR pmpaddr14, 0x111
+WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
 
 # Machine Counter/Timers
-WRITE_READ_CSR mcycle, 0xbad
-WRITE_READ_CSR minstret, 0xbad
-WRITE_READ_CSR mhpmcounter3, 0xbad
-WRITE_READ_CSR mhpmcounter4, 0xbad
-WRITE_READ_CSR mhpmcounter5, 0xbad
-WRITE_READ_CSR mhpmcounter6, 0xbad
-WRITE_READ_CSR mhpmcounter7, 0xbad
-WRITE_READ_CSR mhpmcounter8, 0xbad
-WRITE_READ_CSR mhpmcounter9, 0xbad
-WRITE_READ_CSR mhpmcounter10, 0xbad
-WRITE_READ_CSR mhpmcounter11, 0xbad
-WRITE_READ_CSR mhpmcounter12, 0xbad
-WRITE_READ_CSR mhpmcounter13, 0xbad
-WRITE_READ_CSR mhpmcounter14, 0xbad
-WRITE_READ_CSR mhpmcounter15, 0xbad
-WRITE_READ_CSR mhpmcounter16, 0xbad
-WRITE_READ_CSR mhpmcounter17, 0xbad
-WRITE_READ_CSR mhpmcounter18, 0xbad
-WRITE_READ_CSR mhpmcounter19, 0xbad
-WRITE_READ_CSR mhpmcounter20, 0xbad
-WRITE_READ_CSR mhpmcounter21, 0xbad
-WRITE_READ_CSR mhpmcounter22, 0xbad
-WRITE_READ_CSR mhpmcounter23, 0xbad
-WRITE_READ_CSR mhpmcounter24, 0xbad
-WRITE_READ_CSR mhpmcounter25, 0xbad
-WRITE_READ_CSR mhpmcounter26, 0xbad
-WRITE_READ_CSR mhpmcounter27, 0xbad
-WRITE_READ_CSR mhpmcounter28, 0xbad
-WRITE_READ_CSR mhpmcounter29, 0xbad
-WRITE_READ_CSR mhpmcounter30, 0xbad
-WRITE_READ_CSR mhpmcounter31, 0xbad
+WRITE_READ_CSR mcycle, 0x111
+WRITE_READ_CSR minstret, 0x111
+WRITE_READ_CSR mhpmcounter3, 0x111
+WRITE_READ_CSR mhpmcounter4, 0x111
+WRITE_READ_CSR mhpmcounter5, 0x111
+WRITE_READ_CSR mhpmcounter6, 0x111
+WRITE_READ_CSR mhpmcounter7, 0x111
+WRITE_READ_CSR mhpmcounter8, 0x111
+WRITE_READ_CSR mhpmcounter9, 0x111
+WRITE_READ_CSR mhpmcounter10, 0x111
+WRITE_READ_CSR mhpmcounter11, 0x111
+WRITE_READ_CSR mhpmcounter12, 0x111
+WRITE_READ_CSR mhpmcounter13, 0x111
+WRITE_READ_CSR mhpmcounter14, 0x111
+WRITE_READ_CSR mhpmcounter15, 0x111
+WRITE_READ_CSR mhpmcounter16, 0x111
+WRITE_READ_CSR mhpmcounter17, 0x111
+WRITE_READ_CSR mhpmcounter18, 0x111
+WRITE_READ_CSR mhpmcounter19, 0x111
+WRITE_READ_CSR mhpmcounter20, 0x111
+WRITE_READ_CSR mhpmcounter21, 0x111
+WRITE_READ_CSR mhpmcounter22, 0x111
+WRITE_READ_CSR mhpmcounter23, 0x111
+WRITE_READ_CSR mhpmcounter24, 0x111
+WRITE_READ_CSR mhpmcounter25, 0x111
+WRITE_READ_CSR mhpmcounter26, 0x111
+WRITE_READ_CSR mhpmcounter27, 0x111
+WRITE_READ_CSR mhpmcounter28, 0x111
+WRITE_READ_CSR mhpmcounter29, 0x111
+WRITE_READ_CSR mhpmcounter30, 0x111
+WRITE_READ_CSR mhpmcounter31, 0x111
 
 # Machine Counter Setup
-WRITE_READ_CSR mcountinhibit, 0xbad
-WRITE_READ_CSR mhpmevent3, 0xbad
-WRITE_READ_CSR mhpmevent4, 0xbad
-WRITE_READ_CSR mhpmevent5, 0xbad
-WRITE_READ_CSR mhpmevent6, 0xbad
-WRITE_READ_CSR mhpmevent7, 0xbad
-WRITE_READ_CSR mhpmevent8, 0xbad
-WRITE_READ_CSR mhpmevent9, 0xbad
-WRITE_READ_CSR mhpmevent10, 0xbad
-WRITE_READ_CSR mhpmevent11, 0xbad
-WRITE_READ_CSR mhpmevent12, 0xbad
-WRITE_READ_CSR mhpmevent13, 0xbad
-WRITE_READ_CSR mhpmevent14, 0xbad
-WRITE_READ_CSR mhpmevent15, 0xbad
-WRITE_READ_CSR mhpmevent16, 0xbad
-WRITE_READ_CSR mhpmevent17, 0xbad
-WRITE_READ_CSR mhpmevent18, 0xbad
-WRITE_READ_CSR mhpmevent19, 0xbad
-WRITE_READ_CSR mhpmevent20, 0xbad
-WRITE_READ_CSR mhpmevent21, 0xbad
-WRITE_READ_CSR mhpmevent22, 0xbad
-WRITE_READ_CSR mhpmevent23, 0xbad
-WRITE_READ_CSR mhpmevent24, 0xbad
-WRITE_READ_CSR mhpmevent25, 0xbad
-WRITE_READ_CSR mhpmevent26, 0xbad
-WRITE_READ_CSR mhpmevent27, 0xbad
-WRITE_READ_CSR mhpmevent28, 0xbad
-WRITE_READ_CSR mhpmevent29, 0xbad
-WRITE_READ_CSR mhpmevent30, 0xbad
-WRITE_READ_CSR mhpmevent31, 0xbad
+WRITE_READ_CSR mcountinhibit, 0x111
+WRITE_READ_CSR mhpmevent3, 0x111
+WRITE_READ_CSR mhpmevent4, 0x111
+WRITE_READ_CSR mhpmevent5, 0x111
+WRITE_READ_CSR mhpmevent6, 0x111
+WRITE_READ_CSR mhpmevent7, 0x111
+WRITE_READ_CSR mhpmevent8, 0x111
+WRITE_READ_CSR mhpmevent9, 0x111
+WRITE_READ_CSR mhpmevent10, 0x111
+WRITE_READ_CSR mhpmevent11, 0x111
+WRITE_READ_CSR mhpmevent12, 0x111
+WRITE_READ_CSR mhpmevent13, 0x111
+WRITE_READ_CSR mhpmevent14, 0x111
+WRITE_READ_CSR mhpmevent15, 0x111
+WRITE_READ_CSR mhpmevent16, 0x111
+WRITE_READ_CSR mhpmevent17, 0x111
+WRITE_READ_CSR mhpmevent18, 0x111
+WRITE_READ_CSR mhpmevent19, 0x111
+WRITE_READ_CSR mhpmevent20, 0x111
+WRITE_READ_CSR mhpmevent21, 0x111
+WRITE_READ_CSR mhpmevent22, 0x111
+WRITE_READ_CSR mhpmevent23, 0x111
+WRITE_READ_CSR mhpmevent24, 0x111
+WRITE_READ_CSR mhpmevent25, 0x111
+WRITE_READ_CSR mhpmevent26, 0x111
+WRITE_READ_CSR mhpmevent27, 0x111
+WRITE_READ_CSR mhpmevent28, 0x111
+WRITE_READ_CSR mhpmevent29, 0x111
+WRITE_READ_CSR mhpmevent30, 0x111
+WRITE_READ_CSR mhpmevent31, 0x111
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
index 190b6ed2..9e40fd18 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
@@ -31,142 +31,142 @@ s_file_begin:
 
 GOTO_U_MODE 0x0, 0x0
 
-# Attempt to write 0xbad to each of these CSRs and read the value back
+# Attempt to write 0xAAA to each of these CSRs and read the value back
 # should result in an illegal instruction for the write and read, respectively
 
 # Supervisor Trap Setup
-WRITE_READ_CSR sstatus, 0xbad
-WRITE_READ_CSR sie, 0xbad
-WRITE_READ_CSR stvec, 0xbad
-WRITE_READ_CSR scounteren, 0xbad
+WRITE_READ_CSR sstatus, 0xAAA
+WRITE_READ_CSR sie, 0xAAA
+WRITE_READ_CSR stvec, 0xAAA
+WRITE_READ_CSR scounteren, 0xAAA
 
 # Supervisor Configuration
-# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
+# WRITE_READ_CSR senvcfg, 0xAAA # *** these appear not to be implemented in the compile step of make???
 
 # Supervisor Trap Handling
-WRITE_READ_CSR sscratch, 0xbad
-WRITE_READ_CSR sepc, 0xbad
-WRITE_READ_CSR scause, 0xbad
-WRITE_READ_CSR stval, 0xbad
-WRITE_READ_CSR sip, 0xbad
+WRITE_READ_CSR sscratch, 0xAAA
+WRITE_READ_CSR sepc, 0xAAA
+WRITE_READ_CSR scause, 0xAAA
+WRITE_READ_CSR stval, 0xAAA
+WRITE_READ_CSR sip, 0xAAA
 
 # Supervisor Protection and Translation
-WRITE_READ_CSR satp, 0xbad
+WRITE_READ_CSR satp, 0xAAA
 
 # Machine information Registers
-WRITE_READ_CSR mvendorid, 0xbad
-WRITE_READ_CSR marchid, 0xbad
-WRITE_READ_CSR mimpid, 0xbad
-WRITE_READ_CSR mhartid, 0xbad
-# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
+WRITE_READ_CSR mvendorid, 0xAAA
+WRITE_READ_CSR marchid, 0xAAA
+WRITE_READ_CSR mimpid, 0xAAA
+WRITE_READ_CSR mhartid, 0xAAA
+# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
-WRITE_READ_CSR mstatus, 0xbad
-WRITE_READ_CSR misa, 0xbad
-WRITE_READ_CSR medeleg, 0xbad
-WRITE_READ_CSR mideleg, 0xbad
-WRITE_READ_CSR mie, 0xbad
-WRITE_READ_CSR mtvec, 0xbad
-WRITE_READ_CSR mcounteren, 0xbad
+WRITE_READ_CSR mstatus, 0xAAA
+WRITE_READ_CSR misa, 0xAAA
+WRITE_READ_CSR medeleg, 0xAAA
+WRITE_READ_CSR mideleg, 0xAAA
+WRITE_READ_CSR mie, 0xAAA
+WRITE_READ_CSR mtvec, 0xAAA
+WRITE_READ_CSR mcounteren, 0xAAA
 
 # Machine Trap Handling
-WRITE_READ_CSR mscratch, 0xbad
-WRITE_READ_CSR mepc, 0xbad
-WRITE_READ_CSR mcause, 0xbad
-WRITE_READ_CSR mtval, 0xbad
-WRITE_READ_CSR mip, 0xbad
-# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mtval2, 0xbad
+WRITE_READ_CSR mscratch, 0xAAA
+WRITE_READ_CSR mepc, 0xAAA
+WRITE_READ_CSR mcause, 0xAAA
+WRITE_READ_CSR mtval, 0xAAA
+WRITE_READ_CSR mip, 0xAAA
+# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0xAAA
 
 # Machine Configuration
-# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mseccgf, 0xbad
+# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0xAAA
 
 # Machine Memory Protection
-WRITE_READ_CSR pmpcfg0, 0xbad
-WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
+WRITE_READ_CSR pmpcfg0, 0xAAA
+WRITE_READ_CSR pmpcfg2, 0xAAA # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
 
-WRITE_READ_CSR pmpaddr0, 0xbad
-WRITE_READ_CSR pmpaddr1, 0xbad
-WRITE_READ_CSR pmpaddr2, 0xbad
-WRITE_READ_CSR pmpaddr3, 0xbad
-WRITE_READ_CSR pmpaddr4, 0xbad
-WRITE_READ_CSR pmpaddr5, 0xbad
-WRITE_READ_CSR pmpaddr6, 0xbad
-WRITE_READ_CSR pmpaddr7, 0xbad
-WRITE_READ_CSR pmpaddr8, 0xbad
-WRITE_READ_CSR pmpaddr9, 0xbad
-WRITE_READ_CSR pmpaddr10, 0xbad
-WRITE_READ_CSR pmpaddr11, 0xbad
-WRITE_READ_CSR pmpaddr12, 0xbad
-WRITE_READ_CSR pmpaddr13, 0xbad
-WRITE_READ_CSR pmpaddr14, 0xbad
-WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
+WRITE_READ_CSR pmpaddr0, 0xAAA
+WRITE_READ_CSR pmpaddr1, 0xAAA
+WRITE_READ_CSR pmpaddr2, 0xAAA
+WRITE_READ_CSR pmpaddr3, 0xAAA
+WRITE_READ_CSR pmpaddr4, 0xAAA
+WRITE_READ_CSR pmpaddr5, 0xAAA
+WRITE_READ_CSR pmpaddr6, 0xAAA
+WRITE_READ_CSR pmpaddr7, 0xAAA
+WRITE_READ_CSR pmpaddr8, 0xAAA
+WRITE_READ_CSR pmpaddr9, 0xAAA
+WRITE_READ_CSR pmpaddr10, 0xAAA
+WRITE_READ_CSR pmpaddr11, 0xAAA
+WRITE_READ_CSR pmpaddr12, 0xAAA
+WRITE_READ_CSR pmpaddr13, 0xAAA
+WRITE_READ_CSR pmpaddr14, 0xAAA
+WRITE_READ_CSR pmpaddr15, 0xAAA # only pmpcfg0...15 are enabled in our config
 
 # Machine Counter/Timers
-WRITE_READ_CSR mcycle, 0xbad
-WRITE_READ_CSR minstret, 0xbad
-WRITE_READ_CSR mhpmcounter3, 0xbad
-WRITE_READ_CSR mhpmcounter4, 0xbad
-WRITE_READ_CSR mhpmcounter5, 0xbad
-WRITE_READ_CSR mhpmcounter6, 0xbad
-WRITE_READ_CSR mhpmcounter7, 0xbad
-WRITE_READ_CSR mhpmcounter8, 0xbad
-WRITE_READ_CSR mhpmcounter9, 0xbad
-WRITE_READ_CSR mhpmcounter10, 0xbad
-WRITE_READ_CSR mhpmcounter11, 0xbad
-WRITE_READ_CSR mhpmcounter12, 0xbad
-WRITE_READ_CSR mhpmcounter13, 0xbad
-WRITE_READ_CSR mhpmcounter14, 0xbad
-WRITE_READ_CSR mhpmcounter15, 0xbad
-WRITE_READ_CSR mhpmcounter16, 0xbad
-WRITE_READ_CSR mhpmcounter17, 0xbad
-WRITE_READ_CSR mhpmcounter18, 0xbad
-WRITE_READ_CSR mhpmcounter19, 0xbad
-WRITE_READ_CSR mhpmcounter20, 0xbad
-WRITE_READ_CSR mhpmcounter21, 0xbad
-WRITE_READ_CSR mhpmcounter22, 0xbad
-WRITE_READ_CSR mhpmcounter23, 0xbad
-WRITE_READ_CSR mhpmcounter24, 0xbad
-WRITE_READ_CSR mhpmcounter25, 0xbad
-WRITE_READ_CSR mhpmcounter26, 0xbad
-WRITE_READ_CSR mhpmcounter27, 0xbad
-WRITE_READ_CSR mhpmcounter28, 0xbad
-WRITE_READ_CSR mhpmcounter29, 0xbad
-WRITE_READ_CSR mhpmcounter30, 0xbad
-WRITE_READ_CSR mhpmcounter31, 0xbad
+WRITE_READ_CSR mcycle, 0xAAA
+WRITE_READ_CSR minstret, 0xAAA
+WRITE_READ_CSR mhpmcounter3, 0xAAA
+WRITE_READ_CSR mhpmcounter4, 0xAAA
+WRITE_READ_CSR mhpmcounter5, 0xAAA
+WRITE_READ_CSR mhpmcounter6, 0xAAA
+WRITE_READ_CSR mhpmcounter7, 0xAAA
+WRITE_READ_CSR mhpmcounter8, 0xAAA
+WRITE_READ_CSR mhpmcounter9, 0xAAA
+WRITE_READ_CSR mhpmcounter10, 0xAAA
+WRITE_READ_CSR mhpmcounter11, 0xAAA
+WRITE_READ_CSR mhpmcounter12, 0xAAA
+WRITE_READ_CSR mhpmcounter13, 0xAAA
+WRITE_READ_CSR mhpmcounter14, 0xAAA
+WRITE_READ_CSR mhpmcounter15, 0xAAA
+WRITE_READ_CSR mhpmcounter16, 0xAAA
+WRITE_READ_CSR mhpmcounter17, 0xAAA
+WRITE_READ_CSR mhpmcounter18, 0xAAA
+WRITE_READ_CSR mhpmcounter19, 0xAAA
+WRITE_READ_CSR mhpmcounter20, 0xAAA
+WRITE_READ_CSR mhpmcounter21, 0xAAA
+WRITE_READ_CSR mhpmcounter22, 0xAAA
+WRITE_READ_CSR mhpmcounter23, 0xAAA
+WRITE_READ_CSR mhpmcounter24, 0xAAA
+WRITE_READ_CSR mhpmcounter25, 0xAAA
+WRITE_READ_CSR mhpmcounter26, 0xAAA
+WRITE_READ_CSR mhpmcounter27, 0xAAA
+WRITE_READ_CSR mhpmcounter28, 0xAAA
+WRITE_READ_CSR mhpmcounter29, 0xAAA
+WRITE_READ_CSR mhpmcounter30, 0xAAA
+WRITE_READ_CSR mhpmcounter31, 0xAAA
 
 # Machine Counter Setup
-WRITE_READ_CSR mcountinhibit, 0xbad
-WRITE_READ_CSR mhpmevent3, 0xbad
-WRITE_READ_CSR mhpmevent4, 0xbad
-WRITE_READ_CSR mhpmevent5, 0xbad
-WRITE_READ_CSR mhpmevent6, 0xbad
-WRITE_READ_CSR mhpmevent7, 0xbad
-WRITE_READ_CSR mhpmevent8, 0xbad
-WRITE_READ_CSR mhpmevent9, 0xbad
-WRITE_READ_CSR mhpmevent10, 0xbad
-WRITE_READ_CSR mhpmevent11, 0xbad
-WRITE_READ_CSR mhpmevent12, 0xbad
-WRITE_READ_CSR mhpmevent13, 0xbad
-WRITE_READ_CSR mhpmevent14, 0xbad
-WRITE_READ_CSR mhpmevent15, 0xbad
-WRITE_READ_CSR mhpmevent16, 0xbad
-WRITE_READ_CSR mhpmevent17, 0xbad
-WRITE_READ_CSR mhpmevent18, 0xbad
-WRITE_READ_CSR mhpmevent19, 0xbad
-WRITE_READ_CSR mhpmevent20, 0xbad
-WRITE_READ_CSR mhpmevent21, 0xbad
-WRITE_READ_CSR mhpmevent22, 0xbad
-WRITE_READ_CSR mhpmevent23, 0xbad
-WRITE_READ_CSR mhpmevent24, 0xbad
-WRITE_READ_CSR mhpmevent25, 0xbad
-WRITE_READ_CSR mhpmevent26, 0xbad
-WRITE_READ_CSR mhpmevent27, 0xbad
-WRITE_READ_CSR mhpmevent28, 0xbad
-WRITE_READ_CSR mhpmevent29, 0xbad
-WRITE_READ_CSR mhpmevent30, 0xbad
-WRITE_READ_CSR mhpmevent31, 0xbad
+WRITE_READ_CSR mcountinhibit, 0xAAA
+WRITE_READ_CSR mhpmevent3, 0xAAA
+WRITE_READ_CSR mhpmevent4, 0xAAA
+WRITE_READ_CSR mhpmevent5, 0xAAA
+WRITE_READ_CSR mhpmevent6, 0xAAA
+WRITE_READ_CSR mhpmevent7, 0xAAA
+WRITE_READ_CSR mhpmevent8, 0xAAA
+WRITE_READ_CSR mhpmevent9, 0xAAA
+WRITE_READ_CSR mhpmevent10, 0xAAA
+WRITE_READ_CSR mhpmevent11, 0xAAA
+WRITE_READ_CSR mhpmevent12, 0xAAA
+WRITE_READ_CSR mhpmevent13, 0xAAA
+WRITE_READ_CSR mhpmevent14, 0xAAA
+WRITE_READ_CSR mhpmevent15, 0xAAA
+WRITE_READ_CSR mhpmevent16, 0xAAA
+WRITE_READ_CSR mhpmevent17, 0xAAA
+WRITE_READ_CSR mhpmevent18, 0xAAA
+WRITE_READ_CSR mhpmevent19, 0xAAA
+WRITE_READ_CSR mhpmevent20, 0xAAA
+WRITE_READ_CSR mhpmevent21, 0xAAA
+WRITE_READ_CSR mhpmevent22, 0xAAA
+WRITE_READ_CSR mhpmevent23, 0xAAA
+WRITE_READ_CSR mhpmevent24, 0xAAA
+WRITE_READ_CSR mhpmevent25, 0xAAA
+WRITE_READ_CSR mhpmevent26, 0xAAA
+WRITE_READ_CSR mhpmevent27, 0xAAA
+WRITE_READ_CSR mhpmevent28, 0xAAA
+WRITE_READ_CSR mhpmevent29, 0xAAA
+WRITE_READ_CSR mhpmevent30, 0xAAA
+WRITE_READ_CSR mhpmevent31, 0xAAA
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S
index 927e8653..4336a510 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S
@@ -34,123 +34,123 @@ s_file_begin:
 
 GOTO_S_MODE 0x0, 0x0
 
-# Attempt to write 0xbad to each of these CSRs and read the value back
+# Attempt to write 0x111 to each of these CSRs and read the value back
 # should result in an illegal instruction for the write and read, respectively
 
 # Machine information Registers
-WRITE_READ_CSR mvendorid, 0xbad
-WRITE_READ_CSR marchid, 0xbad
-WRITE_READ_CSR mimpid, 0xbad
-WRITE_READ_CSR mhartid, 0xbad
-# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
+WRITE_READ_CSR mvendorid, 0x111
+WRITE_READ_CSR marchid, 0x111
+WRITE_READ_CSR mimpid, 0x111
+WRITE_READ_CSR mhartid, 0x111
+# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
-WRITE_READ_CSR mstatus, 0xbad
-WRITE_READ_CSR misa, 0xbad
-WRITE_READ_CSR medeleg, 0xbad
-WRITE_READ_CSR mideleg, 0xbad
-WRITE_READ_CSR mie, 0xbad
-WRITE_READ_CSR mtvec, 0xbad
-WRITE_READ_CSR mcounteren, 0xbad
+WRITE_READ_CSR mstatus, 0x111
+WRITE_READ_CSR misa, 0x111
+WRITE_READ_CSR medeleg, 0x111
+WRITE_READ_CSR mideleg, 0x111
+WRITE_READ_CSR mie, 0x111
+WRITE_READ_CSR mtvec, 0x111
+WRITE_READ_CSR mcounteren, 0x111
 
 # Machine Trap Handling
-WRITE_READ_CSR mscratch, 0xbad
-WRITE_READ_CSR mepc, 0xbad
-WRITE_READ_CSR mcause, 0xbad
-WRITE_READ_CSR mtval, 0xbad
-WRITE_READ_CSR mip, 0xbad
-# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mtval2, 0xbad
+WRITE_READ_CSR mscratch, 0x111
+WRITE_READ_CSR mepc, 0x111
+WRITE_READ_CSR mcause, 0x111
+WRITE_READ_CSR mtval, 0x111
+WRITE_READ_CSR mip, 0x111
+# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0x111
 
 # Machine Configuration
-# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mseccgf, 0xbad
+# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0x111
 
 # Machine Memory Protection
-WRITE_READ_CSR pmpcfg0, 0xbad
-WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
+WRITE_READ_CSR pmpcfg0, 0x111
+WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
 
-WRITE_READ_CSR pmpaddr0, 0xbad
-WRITE_READ_CSR pmpaddr1, 0xbad
-WRITE_READ_CSR pmpaddr2, 0xbad
-WRITE_READ_CSR pmpaddr3, 0xbad
-WRITE_READ_CSR pmpaddr4, 0xbad
-WRITE_READ_CSR pmpaddr5, 0xbad
-WRITE_READ_CSR pmpaddr6, 0xbad
-WRITE_READ_CSR pmpaddr7, 0xbad
-WRITE_READ_CSR pmpaddr8, 0xbad
-WRITE_READ_CSR pmpaddr9, 0xbad
-WRITE_READ_CSR pmpaddr10, 0xbad
-WRITE_READ_CSR pmpaddr11, 0xbad
-WRITE_READ_CSR pmpaddr12, 0xbad
-WRITE_READ_CSR pmpaddr13, 0xbad
-WRITE_READ_CSR pmpaddr14, 0xbad
-WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
+WRITE_READ_CSR pmpaddr0, 0x111
+WRITE_READ_CSR pmpaddr1, 0x111
+WRITE_READ_CSR pmpaddr2, 0x111
+WRITE_READ_CSR pmpaddr3, 0x111
+WRITE_READ_CSR pmpaddr4, 0x111
+WRITE_READ_CSR pmpaddr5, 0x111
+WRITE_READ_CSR pmpaddr6, 0x111
+WRITE_READ_CSR pmpaddr7, 0x111
+WRITE_READ_CSR pmpaddr8, 0x111
+WRITE_READ_CSR pmpaddr9, 0x111
+WRITE_READ_CSR pmpaddr10, 0x111
+WRITE_READ_CSR pmpaddr11, 0x111
+WRITE_READ_CSR pmpaddr12, 0x111
+WRITE_READ_CSR pmpaddr13, 0x111
+WRITE_READ_CSR pmpaddr14, 0x111
+WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
 
 # Machine Counter/Timers
-WRITE_READ_CSR mcycle, 0xbad
-WRITE_READ_CSR minstret, 0xbad
-WRITE_READ_CSR mhpmcounter3, 0xbad
-WRITE_READ_CSR mhpmcounter4, 0xbad
-WRITE_READ_CSR mhpmcounter5, 0xbad
-WRITE_READ_CSR mhpmcounter6, 0xbad
-WRITE_READ_CSR mhpmcounter7, 0xbad
-WRITE_READ_CSR mhpmcounter8, 0xbad
-WRITE_READ_CSR mhpmcounter9, 0xbad
-WRITE_READ_CSR mhpmcounter10, 0xbad
-WRITE_READ_CSR mhpmcounter11, 0xbad
-WRITE_READ_CSR mhpmcounter12, 0xbad
-WRITE_READ_CSR mhpmcounter13, 0xbad
-WRITE_READ_CSR mhpmcounter14, 0xbad
-WRITE_READ_CSR mhpmcounter15, 0xbad
-WRITE_READ_CSR mhpmcounter16, 0xbad
-WRITE_READ_CSR mhpmcounter17, 0xbad
-WRITE_READ_CSR mhpmcounter18, 0xbad
-WRITE_READ_CSR mhpmcounter19, 0xbad
-WRITE_READ_CSR mhpmcounter20, 0xbad
-WRITE_READ_CSR mhpmcounter21, 0xbad
-WRITE_READ_CSR mhpmcounter22, 0xbad
-WRITE_READ_CSR mhpmcounter23, 0xbad
-WRITE_READ_CSR mhpmcounter24, 0xbad
-WRITE_READ_CSR mhpmcounter25, 0xbad
-WRITE_READ_CSR mhpmcounter26, 0xbad
-WRITE_READ_CSR mhpmcounter27, 0xbad
-WRITE_READ_CSR mhpmcounter28, 0xbad
-WRITE_READ_CSR mhpmcounter29, 0xbad
-WRITE_READ_CSR mhpmcounter30, 0xbad
-WRITE_READ_CSR mhpmcounter31, 0xbad
+WRITE_READ_CSR mcycle, 0x111
+WRITE_READ_CSR minstret, 0x111
+WRITE_READ_CSR mhpmcounter3, 0x111
+WRITE_READ_CSR mhpmcounter4, 0x111
+WRITE_READ_CSR mhpmcounter5, 0x111
+WRITE_READ_CSR mhpmcounter6, 0x111
+WRITE_READ_CSR mhpmcounter7, 0x111
+WRITE_READ_CSR mhpmcounter8, 0x111
+WRITE_READ_CSR mhpmcounter9, 0x111
+WRITE_READ_CSR mhpmcounter10, 0x111
+WRITE_READ_CSR mhpmcounter11, 0x111
+WRITE_READ_CSR mhpmcounter12, 0x111
+WRITE_READ_CSR mhpmcounter13, 0x111
+WRITE_READ_CSR mhpmcounter14, 0x111
+WRITE_READ_CSR mhpmcounter15, 0x111
+WRITE_READ_CSR mhpmcounter16, 0x111
+WRITE_READ_CSR mhpmcounter17, 0x111
+WRITE_READ_CSR mhpmcounter18, 0x111
+WRITE_READ_CSR mhpmcounter19, 0x111
+WRITE_READ_CSR mhpmcounter20, 0x111
+WRITE_READ_CSR mhpmcounter21, 0x111
+WRITE_READ_CSR mhpmcounter22, 0x111
+WRITE_READ_CSR mhpmcounter23, 0x111
+WRITE_READ_CSR mhpmcounter24, 0x111
+WRITE_READ_CSR mhpmcounter25, 0x111
+WRITE_READ_CSR mhpmcounter26, 0x111
+WRITE_READ_CSR mhpmcounter27, 0x111
+WRITE_READ_CSR mhpmcounter28, 0x111
+WRITE_READ_CSR mhpmcounter29, 0x111
+WRITE_READ_CSR mhpmcounter30, 0x111
+WRITE_READ_CSR mhpmcounter31, 0x111
 
 # Machine Counter Setup
-WRITE_READ_CSR mcountinhibit, 0xbad
-WRITE_READ_CSR mhpmevent3, 0xbad
-WRITE_READ_CSR mhpmevent4, 0xbad
-WRITE_READ_CSR mhpmevent5, 0xbad
-WRITE_READ_CSR mhpmevent6, 0xbad
-WRITE_READ_CSR mhpmevent7, 0xbad
-WRITE_READ_CSR mhpmevent8, 0xbad
-WRITE_READ_CSR mhpmevent9, 0xbad
-WRITE_READ_CSR mhpmevent10, 0xbad
-WRITE_READ_CSR mhpmevent11, 0xbad
-WRITE_READ_CSR mhpmevent12, 0xbad
-WRITE_READ_CSR mhpmevent13, 0xbad
-WRITE_READ_CSR mhpmevent14, 0xbad
-WRITE_READ_CSR mhpmevent15, 0xbad
-WRITE_READ_CSR mhpmevent16, 0xbad
-WRITE_READ_CSR mhpmevent17, 0xbad
-WRITE_READ_CSR mhpmevent18, 0xbad
-WRITE_READ_CSR mhpmevent19, 0xbad
-WRITE_READ_CSR mhpmevent20, 0xbad
-WRITE_READ_CSR mhpmevent21, 0xbad
-WRITE_READ_CSR mhpmevent22, 0xbad
-WRITE_READ_CSR mhpmevent23, 0xbad
-WRITE_READ_CSR mhpmevent24, 0xbad
-WRITE_READ_CSR mhpmevent25, 0xbad
-WRITE_READ_CSR mhpmevent26, 0xbad
-WRITE_READ_CSR mhpmevent27, 0xbad
-WRITE_READ_CSR mhpmevent28, 0xbad
-WRITE_READ_CSR mhpmevent29, 0xbad
-WRITE_READ_CSR mhpmevent30, 0xbad
-WRITE_READ_CSR mhpmevent31, 0xbad
+WRITE_READ_CSR mcountinhibit, 0x111
+WRITE_READ_CSR mhpmevent3, 0x111
+WRITE_READ_CSR mhpmevent4, 0x111
+WRITE_READ_CSR mhpmevent5, 0x111
+WRITE_READ_CSR mhpmevent6, 0x111
+WRITE_READ_CSR mhpmevent7, 0x111
+WRITE_READ_CSR mhpmevent8, 0x111
+WRITE_READ_CSR mhpmevent9, 0x111
+WRITE_READ_CSR mhpmevent10, 0x111
+WRITE_READ_CSR mhpmevent11, 0x111
+WRITE_READ_CSR mhpmevent12, 0x111
+WRITE_READ_CSR mhpmevent13, 0x111
+WRITE_READ_CSR mhpmevent14, 0x111
+WRITE_READ_CSR mhpmevent15, 0x111
+WRITE_READ_CSR mhpmevent16, 0x111
+WRITE_READ_CSR mhpmevent17, 0x111
+WRITE_READ_CSR mhpmevent18, 0x111
+WRITE_READ_CSR mhpmevent19, 0x111
+WRITE_READ_CSR mhpmevent20, 0x111
+WRITE_READ_CSR mhpmevent21, 0x111
+WRITE_READ_CSR mhpmevent22, 0x111
+WRITE_READ_CSR mhpmevent23, 0x111
+WRITE_READ_CSR mhpmevent24, 0x111
+WRITE_READ_CSR mhpmevent25, 0x111
+WRITE_READ_CSR mhpmevent26, 0x111
+WRITE_READ_CSR mhpmevent27, 0x111
+WRITE_READ_CSR mhpmevent28, 0x111
+WRITE_READ_CSR mhpmevent29, 0x111
+WRITE_READ_CSR mhpmevent30, 0x111
+WRITE_READ_CSR mhpmevent31, 0x111
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S
index f6819141..21fdc1d7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S
@@ -31,142 +31,142 @@ s_file_begin:
 
 GOTO_U_MODE 0x0, 0x0
 
-# Attempt to write 0xbad to each of these CSRs and read the value back
+# Attempt to write 0x111 to each of these CSRs and read the value back
 # should result in an illegal instruction for the write and read, respectively
 
 # Supervisor Trap Setup
-WRITE_READ_CSR sstatus, 0xbad
-WRITE_READ_CSR sie, 0xbad
-WRITE_READ_CSR stvec, 0xbad
-WRITE_READ_CSR scounteren, 0xbad
+WRITE_READ_CSR sstatus, 0x111
+WRITE_READ_CSR sie, 0x111
+WRITE_READ_CSR stvec, 0x111
+WRITE_READ_CSR scounteren, 0x111
 
 # Supervisor Configuration
-# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR senvcfg, 0x111 # *** these appear not to be implemented in GCC
 
 # Supervisor Trap Handling
-WRITE_READ_CSR sscratch, 0xbad
-WRITE_READ_CSR sepc, 0xbad
-WRITE_READ_CSR scause, 0xbad
-WRITE_READ_CSR stval, 0xbad
-WRITE_READ_CSR sip, 0xbad
+WRITE_READ_CSR sscratch, 0x111
+WRITE_READ_CSR sepc, 0x111
+WRITE_READ_CSR scause, 0x111
+WRITE_READ_CSR stval, 0x111
+WRITE_READ_CSR sip, 0x111
 
 # Supervisor Protection and Translation
-WRITE_READ_CSR satp, 0xbad
+WRITE_READ_CSR satp, 0x111
 
 # Machine information Registers
-WRITE_READ_CSR mvendorid, 0xbad
-WRITE_READ_CSR marchid, 0xbad
-WRITE_READ_CSR mimpid, 0xbad
-WRITE_READ_CSR mhartid, 0xbad
-# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
+WRITE_READ_CSR mvendorid, 0x111
+WRITE_READ_CSR marchid, 0x111
+WRITE_READ_CSR mimpid, 0x111
+WRITE_READ_CSR mhartid, 0x111
+# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
-WRITE_READ_CSR mstatus, 0xbad
-WRITE_READ_CSR misa, 0xbad
-WRITE_READ_CSR medeleg, 0xbad
-WRITE_READ_CSR mideleg, 0xbad
-WRITE_READ_CSR mie, 0xbad
-WRITE_READ_CSR mtvec, 0xbad
-WRITE_READ_CSR mcounteren, 0xbad
+WRITE_READ_CSR mstatus, 0x111
+WRITE_READ_CSR misa, 0x111
+WRITE_READ_CSR medeleg, 0x111
+WRITE_READ_CSR mideleg, 0x111
+WRITE_READ_CSR mie, 0x111
+WRITE_READ_CSR mtvec, 0x111
+WRITE_READ_CSR mcounteren, 0x111
 
 # Machine Trap Handling
-WRITE_READ_CSR mscratch, 0xbad
-WRITE_READ_CSR mepc, 0xbad
-WRITE_READ_CSR mcause, 0xbad
-WRITE_READ_CSR mtval, 0xbad
-WRITE_READ_CSR mip, 0xbad
-# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mtval2, 0xbad
+WRITE_READ_CSR mscratch, 0x111
+WRITE_READ_CSR mepc, 0x111
+WRITE_READ_CSR mcause, 0x111
+WRITE_READ_CSR mtval, 0x111
+WRITE_READ_CSR mip, 0x111
+# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0x111
 
 # Machine Configuration
-# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
-# WRITE_READ_CSR mseccgf, 0xbad
+# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0x111
 
 # Machine Memory Protection
-WRITE_READ_CSR pmpcfg0, 0xbad
-WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
+WRITE_READ_CSR pmpcfg0, 0x111
+WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
 
-WRITE_READ_CSR pmpaddr0, 0xbad
-WRITE_READ_CSR pmpaddr1, 0xbad
-WRITE_READ_CSR pmpaddr2, 0xbad
-WRITE_READ_CSR pmpaddr3, 0xbad
-WRITE_READ_CSR pmpaddr4, 0xbad
-WRITE_READ_CSR pmpaddr5, 0xbad
-WRITE_READ_CSR pmpaddr6, 0xbad
-WRITE_READ_CSR pmpaddr7, 0xbad
-WRITE_READ_CSR pmpaddr8, 0xbad
-WRITE_READ_CSR pmpaddr9, 0xbad
-WRITE_READ_CSR pmpaddr10, 0xbad
-WRITE_READ_CSR pmpaddr11, 0xbad
-WRITE_READ_CSR pmpaddr12, 0xbad
-WRITE_READ_CSR pmpaddr13, 0xbad
-WRITE_READ_CSR pmpaddr14, 0xbad
-WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
+WRITE_READ_CSR pmpaddr0, 0x111
+WRITE_READ_CSR pmpaddr1, 0x111
+WRITE_READ_CSR pmpaddr2, 0x111
+WRITE_READ_CSR pmpaddr3, 0x111
+WRITE_READ_CSR pmpaddr4, 0x111
+WRITE_READ_CSR pmpaddr5, 0x111
+WRITE_READ_CSR pmpaddr6, 0x111
+WRITE_READ_CSR pmpaddr7, 0x111
+WRITE_READ_CSR pmpaddr8, 0x111
+WRITE_READ_CSR pmpaddr9, 0x111
+WRITE_READ_CSR pmpaddr10, 0x111
+WRITE_READ_CSR pmpaddr11, 0x111
+WRITE_READ_CSR pmpaddr12, 0x111
+WRITE_READ_CSR pmpaddr13, 0x111
+WRITE_READ_CSR pmpaddr14, 0x111
+WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
 
 # Machine Counter/Timers
-WRITE_READ_CSR mcycle, 0xbad
-WRITE_READ_CSR minstret, 0xbad
-WRITE_READ_CSR mhpmcounter3, 0xbad
-WRITE_READ_CSR mhpmcounter4, 0xbad
-WRITE_READ_CSR mhpmcounter5, 0xbad
-WRITE_READ_CSR mhpmcounter6, 0xbad
-WRITE_READ_CSR mhpmcounter7, 0xbad
-WRITE_READ_CSR mhpmcounter8, 0xbad
-WRITE_READ_CSR mhpmcounter9, 0xbad
-WRITE_READ_CSR mhpmcounter10, 0xbad
-WRITE_READ_CSR mhpmcounter11, 0xbad
-WRITE_READ_CSR mhpmcounter12, 0xbad
-WRITE_READ_CSR mhpmcounter13, 0xbad
-WRITE_READ_CSR mhpmcounter14, 0xbad
-WRITE_READ_CSR mhpmcounter15, 0xbad
-WRITE_READ_CSR mhpmcounter16, 0xbad
-WRITE_READ_CSR mhpmcounter17, 0xbad
-WRITE_READ_CSR mhpmcounter18, 0xbad
-WRITE_READ_CSR mhpmcounter19, 0xbad
-WRITE_READ_CSR mhpmcounter20, 0xbad
-WRITE_READ_CSR mhpmcounter21, 0xbad
-WRITE_READ_CSR mhpmcounter22, 0xbad
-WRITE_READ_CSR mhpmcounter23, 0xbad
-WRITE_READ_CSR mhpmcounter24, 0xbad
-WRITE_READ_CSR mhpmcounter25, 0xbad
-WRITE_READ_CSR mhpmcounter26, 0xbad
-WRITE_READ_CSR mhpmcounter27, 0xbad
-WRITE_READ_CSR mhpmcounter28, 0xbad
-WRITE_READ_CSR mhpmcounter29, 0xbad
-WRITE_READ_CSR mhpmcounter30, 0xbad
-WRITE_READ_CSR mhpmcounter31, 0xbad
+WRITE_READ_CSR mcycle, 0x111
+WRITE_READ_CSR minstret, 0x111
+WRITE_READ_CSR mhpmcounter3, 0x111
+WRITE_READ_CSR mhpmcounter4, 0x111
+WRITE_READ_CSR mhpmcounter5, 0x111
+WRITE_READ_CSR mhpmcounter6, 0x111
+WRITE_READ_CSR mhpmcounter7, 0x111
+WRITE_READ_CSR mhpmcounter8, 0x111
+WRITE_READ_CSR mhpmcounter9, 0x111
+WRITE_READ_CSR mhpmcounter10, 0x111
+WRITE_READ_CSR mhpmcounter11, 0x111
+WRITE_READ_CSR mhpmcounter12, 0x111
+WRITE_READ_CSR mhpmcounter13, 0x111
+WRITE_READ_CSR mhpmcounter14, 0x111
+WRITE_READ_CSR mhpmcounter15, 0x111
+WRITE_READ_CSR mhpmcounter16, 0x111
+WRITE_READ_CSR mhpmcounter17, 0x111
+WRITE_READ_CSR mhpmcounter18, 0x111
+WRITE_READ_CSR mhpmcounter19, 0x111
+WRITE_READ_CSR mhpmcounter20, 0x111
+WRITE_READ_CSR mhpmcounter21, 0x111
+WRITE_READ_CSR mhpmcounter22, 0x111
+WRITE_READ_CSR mhpmcounter23, 0x111
+WRITE_READ_CSR mhpmcounter24, 0x111
+WRITE_READ_CSR mhpmcounter25, 0x111
+WRITE_READ_CSR mhpmcounter26, 0x111
+WRITE_READ_CSR mhpmcounter27, 0x111
+WRITE_READ_CSR mhpmcounter28, 0x111
+WRITE_READ_CSR mhpmcounter29, 0x111
+WRITE_READ_CSR mhpmcounter30, 0x111
+WRITE_READ_CSR mhpmcounter31, 0x111
 
 # Machine Counter Setup
-WRITE_READ_CSR mcountinhibit, 0xbad
-WRITE_READ_CSR mhpmevent3, 0xbad
-WRITE_READ_CSR mhpmevent4, 0xbad
-WRITE_READ_CSR mhpmevent5, 0xbad
-WRITE_READ_CSR mhpmevent6, 0xbad
-WRITE_READ_CSR mhpmevent7, 0xbad
-WRITE_READ_CSR mhpmevent8, 0xbad
-WRITE_READ_CSR mhpmevent9, 0xbad
-WRITE_READ_CSR mhpmevent10, 0xbad
-WRITE_READ_CSR mhpmevent11, 0xbad
-WRITE_READ_CSR mhpmevent12, 0xbad
-WRITE_READ_CSR mhpmevent13, 0xbad
-WRITE_READ_CSR mhpmevent14, 0xbad
-WRITE_READ_CSR mhpmevent15, 0xbad
-WRITE_READ_CSR mhpmevent16, 0xbad
-WRITE_READ_CSR mhpmevent17, 0xbad
-WRITE_READ_CSR mhpmevent18, 0xbad
-WRITE_READ_CSR mhpmevent19, 0xbad
-WRITE_READ_CSR mhpmevent20, 0xbad
-WRITE_READ_CSR mhpmevent21, 0xbad
-WRITE_READ_CSR mhpmevent22, 0xbad
-WRITE_READ_CSR mhpmevent23, 0xbad
-WRITE_READ_CSR mhpmevent24, 0xbad
-WRITE_READ_CSR mhpmevent25, 0xbad
-WRITE_READ_CSR mhpmevent26, 0xbad
-WRITE_READ_CSR mhpmevent27, 0xbad
-WRITE_READ_CSR mhpmevent28, 0xbad
-WRITE_READ_CSR mhpmevent29, 0xbad
-WRITE_READ_CSR mhpmevent30, 0xbad
-WRITE_READ_CSR mhpmevent31, 0xbad
+WRITE_READ_CSR mcountinhibit, 0x111
+WRITE_READ_CSR mhpmevent3, 0x111
+WRITE_READ_CSR mhpmevent4, 0x111
+WRITE_READ_CSR mhpmevent5, 0x111
+WRITE_READ_CSR mhpmevent6, 0x111
+WRITE_READ_CSR mhpmevent7, 0x111
+WRITE_READ_CSR mhpmevent8, 0x111
+WRITE_READ_CSR mhpmevent9, 0x111
+WRITE_READ_CSR mhpmevent10, 0x111
+WRITE_READ_CSR mhpmevent11, 0x111
+WRITE_READ_CSR mhpmevent12, 0x111
+WRITE_READ_CSR mhpmevent13, 0x111
+WRITE_READ_CSR mhpmevent14, 0x111
+WRITE_READ_CSR mhpmevent15, 0x111
+WRITE_READ_CSR mhpmevent16, 0x111
+WRITE_READ_CSR mhpmevent17, 0x111
+WRITE_READ_CSR mhpmevent18, 0x111
+WRITE_READ_CSR mhpmevent19, 0x111
+WRITE_READ_CSR mhpmevent20, 0x111
+WRITE_READ_CSR mhpmevent21, 0x111
+WRITE_READ_CSR mhpmevent22, 0x111
+WRITE_READ_CSR mhpmevent23, 0x111
+WRITE_READ_CSR mhpmevent24, 0x111
+WRITE_READ_CSR mhpmevent25, 0x111
+WRITE_READ_CSR mhpmevent26, 0x111
+WRITE_READ_CSR mhpmevent27, 0x111
+WRITE_READ_CSR mhpmevent28, 0x111
+WRITE_READ_CSR mhpmevent29, 0x111
+WRITE_READ_CSR mhpmevent30, 0x111
+WRITE_READ_CSR mhpmevent31, 0x111
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
index 1eeaed0b..850d0c2a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
@@ -1,6 +1,6 @@
 ///////////////////////////////////////////
 //
-// WALLY-MMU
+// WALLY-minfo
 //
 // Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
 //
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
index d9a45556..7ea1e782 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
@@ -1,6 +1,6 @@
 ///////////////////////////////////////////
 //
-// WALLY-MMU
+// WALLY-misa
 //
 // Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
 //