From 49daa736b12cb7719b77cb17b2fa97627d295090 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 18 Jan 2023 19:25:54 -0600 Subject: [PATCH] Formatting spillsupport. --- pipelined/src/ifu/ifu.sv | 5 ++- pipelined/src/ifu/spillsupport.sv | 58 ++++++++++++++++--------------- 2 files changed, 32 insertions(+), 31 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c65fe0e8..72967539 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -122,9 +122,8 @@ module ifu ( ///////////////////////////////////////////////////////////////////////////////////////////// if(`C_SUPPORTED) begin : SpillSupport - spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF), - .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, - .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); + spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, + .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport assign PCNextFSpill = PCNextF; assign PCFSpill = PCF; diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 4cb6e359..89f86efc 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -28,37 +28,39 @@ `include "wally-config.vh" -module spillsupport #(parameter CACHE_ENABLED) - (input logic clk, - input logic reset, - input logic StallF, Flush, - input logic [`XLEN-1:0] PCF, - input logic [`XLEN-1:2] PCPlus4F, - input logic [`XLEN-1:0] PCNextF, - input logic [31:0] InstrRawF, - input logic IFUCacheBusStallD, - input logic ITLBMissF, - input logic InstrDAPageFaultF, - output logic [`XLEN-1:0] PCNextFSpill, - output logic [`XLEN-1:0] PCFSpill, - output logic SelNextSpillF, - output logic [31:0] PostSpillInstrRawF, - output logic CompressedF); +module spillsupport #( + parameter CACHE_ENABLED // Changes spill threshold to 1 if there is no cache +)(input logic clk, + input logic reset, + input logic StallD, FlushD, + input logic [`XLEN-1:0] PCF, // 2 byte aligned PC in Fetch stage + input logic [`XLEN-1:2] PCPlus4F, // PCF + 4 + input logic [`XLEN-1:0] PCNextF, // The next PCF + input logic [31:0] InstrRawF, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed + input logic IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched + input logic ITLBMissF, // ITLB miss, ignore memory request + input logic InstrDAPageFaultF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active) + output logic [`XLEN-1:0] PCNextFSpill, // The next PCF for one of the two memory addresses of the spill + output logic [`XLEN-1:0] PCFSpill, // PCF for one of the two memory addresses of the spill + output logic SelNextSpillF, // During the transition between the two spill operations, the IFU should stall the pipeline + output logic [31:0] PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction + output logic CompressedF); // The fetched instruction is compressed - - localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; - logic [`XLEN-1:0] PCPlus2F; + // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1] + localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; + logic [`XLEN-1:0] PCPlus2F; logic TakeSpillF; logic SpillF; - logic SelSpillF, SpillSaveF; - logic [15:0] SpillDataLine0; + logic SelSpillF; + logic SpillSaveF; + logic [15:0] InstrFirstHalf; typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; - // compute PCF+2 + // compute PCF+2 from the raw PC+4 mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); // select between PCNextF and PCF+2 - mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill)); + mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~FlushD), .y(PCNextFSpill)); // select between PCF and PCF+2 mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); @@ -66,14 +68,14 @@ module spillsupport #(parameter CACHE_ENABLED) assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF)); always_ff @(posedge clk) - if (reset | Flush) CurrState <= #1 STATE_READY; + if (reset | FlushD) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; always_comb begin case (CurrState) STATE_READY: if (TakeSpillF) NextState = STATE_SPILL; else NextState = STATE_READY; - STATE_SPILL: if(IFUCacheBusStallD | StallF) NextState = STATE_SPILL; + STATE_SPILL: if(IFUCacheBusStallD | StallD) NextState = STATE_SPILL; else NextState = STATE_READY; default: NextState = STATE_READY; endcase @@ -85,12 +87,12 @@ module spillsupport #(parameter CACHE_ENABLED) assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF; flopenr #(16) SpillInstrReg(.clk(clk), - .en(SpillSaveF & ~Flush), + .en(SpillSaveF & ~FlushD), .reset(reset), .d(InstrRawF[15:0]), - .q(SpillDataLine0)); + .q(InstrFirstHalf)); - mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF), + mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], InstrFirstHalf}), .s(SpillF), .y(PostSpillInstrRawF)); assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;