From 49a1259cf98d9fba6291a15703e469de67f40a6d Mon Sep 17 00:00:00 2001 From: cturek Date: Tue, 20 Sep 2022 20:00:01 +0000 Subject: [PATCH] Fixed fgen4 --- pipelined/config/shared/wally-shared.vh | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 14924fcc..7527e490 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -102,8 +102,8 @@ `define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6)) // division constants -`define RADIX 32'h2 -`define DIVCOPIES 32'h3 +`define RADIX 32'h4 +`define DIVCOPIES 32'h1 `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3)) // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input `define DIVN (`NF < `XLEN ? `XLEN : `NF+3) // length of input diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 08b2dfab..01b067c6 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -49,7 +49,7 @@ module fdivsqrtfgen4 ( always_comb if (u[3]) F = F2; else if (u[2]) F = F1; - else if (U[1]) F = FN1; + else if (u[1]) F = FN1; else if (u[0]) F = FN2; else F = F0; endmodule \ No newline at end of file