From 4908f77cf94f44a48b73041aa070e37c26054f9e Mon Sep 17 00:00:00 2001
From: slmnemo <nicholas.lucioforlife@yahoo.com>
Date: Tue, 17 May 2022 16:33:09 -0700
Subject: [PATCH] Intentionally broke wally by setting datapath Rs1D to use
 bits 18:14 instead of 19:15 to test regression

---
 pipelined/src/ieu/datapath.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index 90b5f033..068beb1c 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -88,7 +88,7 @@ module datapath (
   logic [`XLEN-1:0] IFResultW;
   
   // Decode stage
-  assign Rs1D      = InstrD[19:15];
+  assign Rs1D      = InstrD[18:14]; // Broke this, it should be 19 to 15.
   assign Rs2D      = InstrD[24:20];
   assign RdD       = InstrD[11:7];
   regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);