From 48c862d53654806918df4320a953ca759d9754f7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 31 Mar 2022 16:44:49 -0500 Subject: [PATCH] Added PLIC to ILA. --- fpga/constraints/debug2.xdc | 20 ++++++++++++++++++++ pipelined/src/uncore/plic.sv | 8 ++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 7cc4f8d1..8eb3e2b3 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -631,3 +631,23 @@ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe133] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133] connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe134] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134] +connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe135] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135] +connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore/plic.plic/requests[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe136] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136] +connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe137] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137] +connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]] diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv index 082664dd..6e9f95b8 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic.sv @@ -57,16 +57,16 @@ module plic ( input logic UARTIntr,GPIOIntr, output logic [`XLEN-1:0] HREADPLIC, output logic HRESPPLIC, HREADYPLIC, - output logic MExtIntM, SExtIntM); + (* mark_debug = "true" *) output logic MExtIntM, SExtIntM); logic memwrite, memread, initTrans; logic [23:0] entry, entryd; logic [31:0] Din, Dout; // context-independent signals - logic [`N:1] requests; - logic [`N:1][2:0] intPriority; - logic [`N:1] intInProgress, intPending, nextIntPending; + (* mark_debug = "true" *) logic [`N:1] requests; + (* mark_debug = "true" *) logic [`N:1][2:0] intPriority; + (* mark_debug = "true" *) logic [`N:1] intInProgress, intPending, nextIntPending; // context-dependent signals logic [`C-1:0][2:0] intThreshold;