From 4850d058b26d373634141b224ddc30a54b7af5ce Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 27 Dec 2022 10:30:42 -0800
Subject: [PATCH] fdiv typo

---
 pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 7438ba57..2e549c2b 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -74,8 +74,7 @@ module fdivsqrtpostproc(
     assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
     assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
     assign FZeroDivE =  {3'b001,D,1'b0};                                    // F for divide
-    assign FZeroE = SqrtE ? FZeroSqrtE : FZeroDivE;
-    // assign FZeroE = (SqrtE & ~MDUE) ? FZeroSqrtE : FZeroDivE;
+    mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
     csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
     assign WZeroE = weq0E|(wfeq0E & Firstun);