From 469efa61afce6f41b06bf101e6967b3e40e1bced Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 18 Jan 2023 18:17:48 -0600 Subject: [PATCH] Formatting. --- pipelined/src/lsu/lrsc.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index 80b584dc..7edae6b8 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -1,11 +1,14 @@ /////////////////////////////////////////// // lrsc.sv // -// Written: David_Harris@hmc.edu 17 July 2021 -// Modified: +// Written: David_Harris@hmc.edu +// Created: 17 July 2021 +// Modified: 18 January 2023 // // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails +// +// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. //