From 465aad372a1a5069740e71f66952b847ca8c81ce Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:42:32 -0800 Subject: [PATCH] added comments to zbc units --- src/ieu/alu.sv | 2 ++ src/ieu/bmu/clmul.sv | 3 +-- src/ieu/bmu/zbc.sv | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3026765b..60bcf552 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -89,11 +89,13 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; + //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; + //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU if (`ZBC_SUPPORTED) begin : zbcdecoder always_comb case ({Funct7, Funct3}) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 280c3fbd..46893573 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -33,8 +33,7 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result - logic [(WIDTH*WIDTH)-1:0] s; - logic [WIDTH-1:0] intial; + logic [(WIDTH*WIDTH)-1:0] s; // intermediary signals for carry-less multiply integer i; integer j; diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 400aaf53..580cdacc 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -38,10 +38,10 @@ module zbc #(parameter WIDTH=32) ( logic [WIDTH-1:0] RevA, RevB; logic [WIDTH-1:0] x,y; - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); + //NOTE: Optimize this when doing decoder stuff. always_comb begin casez (Funct3) 3'b001: begin //clmul