diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv
index ff251aeb..b91abdea 100644
--- a/pipelined/src/fpu/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt.sv
@@ -59,9 +59,7 @@ module fdivsqrt(
   logic [`DIVb:0] X;
   logic [`DIVN-2:0]  D; // U0.N-1
   logic [`DIVN-2:0] Dpreproc;
-  logic [`DIVb:0] LastSM;
-  logic [`DIVb-1:0] LastC;
-  logic [`DIVb:0] FirstSM;
+  logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;
   logic [`DIVb-1:0] FirstC;
   logic [`DURLEN-1:0] Dur;
   logic NegSticky;
@@ -72,14 +70,14 @@ module fdivsqrt(
     .clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
     .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
   fdivsqrtfsm fdivsqrtfsm(
-    .reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, 
+    .reset, .qn, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, 
     .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, 
     .XNaNE, .YNaNE,
-    .StickyWSA, .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
+    .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
   fdivsqrtiter fdivsqrtiter(
-    .clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, 
-    .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, 
+    .clk, .qn, .D, .FirstS, .FirstSM, .FirstQ, .FirstQM, .FirstC, .SqrtE, .SqrtM, 
+    .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, 
     .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
-    .StickyWSA, .DivBusy, .Qm(QmM));
-  fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstSM, .FirstC, .qn, .SqrtM, .WZero, .DivSM, .NegSticky);
+    .DivBusy);
+  fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstS, .FirstSM, .FirstQ, .FirstQM, .FirstC, .qn, .SqrtM, .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index 2b69dc19..ee79470d 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -44,12 +44,7 @@ module fdivsqrtfsm(
   input  logic StallE,
   input  logic StallM,
   input logic [`DIVN-2:0]  D, // U0.N-1
-  input  logic [`DIVb+3:0] StickyWSA,
   input  logic [`DURLEN-1:0] Dur,
-  input logic [`DIVb:0] LastSM,
-  input logic [`DIVb:0] FirstSM,
-  input logic [`DIVb-1:0] LastC,
-  input logic [`DIVb-1:0] FirstC,
   input logic [`DIVCOPIES-1:0] qn,
   input logic WZero,
   output logic [`DURLEN-1:0] EarlyTermShiftE,
diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv
index 8835b59f..aad7d4e7 100644
--- a/pipelined/src/fpu/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrtiter.sv
@@ -40,14 +40,10 @@ module fdivsqrtiter(
   input  logic SqrtM,
   input  logic [`DIVb:0] X,
   input  logic [`DIVN-2:0] Dpreproc,
-  input  logic NegSticky,
-  output logic [`DIVb-(`RADIX/4):0] Qm,
   output logic [`DIVN-2:0]  D, // U0.N-1
   output logic [`DIVb+3:0]  NextWSN, NextWCN,
-  output logic [`DIVb+3:0]  StickyWSA,
-  output logic [`DIVb:0] LastSM,
-  output logic [`DIVb-1:0] LastC,
-  output logic [`DIVb:0] FirstSM,
+  output logic [`DIVb:0] FirstS, FirstSM,
+  output logic [`DIVb:0] FirstQ, FirstQM,
   output logic [`DIVb-1:0] FirstC,
   output logic [`DIVCOPIES-1:0] qn,
   output logic [`DIVb+3:0]  FirstWS, FirstWC
@@ -164,27 +160,14 @@ module fdivsqrtiter(
   flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
   mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux);
   flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]);
- // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
-  always_comb
-    if(SqrtM) // sqrt ouputs in the range (1, .5]
-      if(NegSticky) Qm = {SM[0][`DIVb-1-(`RADIX/4):0], 1'b0};
-      else          Qm = {S[0][`DIVb-1-(`RADIX/4):0], 1'b0};
-    else  
-      if(NegSticky) Qm = QM[0][`DIVb-(`RADIX/4):0];
-      else          Qm = Q[0][`DIVb-(`RADIX/4):0];
 
   assign FirstWS = WS[0];
   assign FirstWC = WC[0];
 
-  assign LastSM = SM[`DIVCOPIES-1];
-  assign LastC = C[`DIVCOPIES-1];
+  assign FirstS = S[0];
   assign FirstSM = SM[0];
+  assign FirstQ = Q[0];
+  assign FirstQM = QM[0];
   assign FirstC = C[0];
-
-  if(`RADIX==2)
-    if (`DIVCOPIES == 1)
-      assign StickyWSA = {WSA[0][`DIVb+2:0], 1'b0};
-    else
-      assign StickyWSA = {WSA[1][`DIVb+2:0], 1'b0};
 endmodule
 
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index a6e7ccb4..d5152f79 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -33,16 +33,17 @@
 module fdivsqrtpostproc(
   input logic [`DIVb+3:0] WS, WC,
   input logic [`DIVN-2:0]  D, // U0.N-1
-  input logic [`DIVb:0] FirstSM,
+  input logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM,
   input logic [`DIVb-1:0] FirstC,
   input logic [`DIVCOPIES-1:0] qn,
   input logic SqrtM,
+  output logic [`DIVb-(`RADIX/4):0] QmM,
   output logic WZero,
-  output logic DivSM,
-  output logic NegSticky
+  output logic DivSM
 );
   
   logic [`DIVb+3:0] W;
+  logic NegSticky;
 
   // check for early termination on an exact result.  If the result is not exact, the sticky should be set
   if (`RADIX == 2) begin
@@ -60,4 +61,13 @@ module fdivsqrtpostproc(
   assign W = WC+WS;
   assign NegSticky = W[`DIVb+3];
 
+   // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
+  always_comb
+    if(SqrtM) // sqrt ouputs in the range (1, .5]
+      if(NegSticky) QmM = {FirstSM[`DIVb-1-(`RADIX/4):0], 1'b0};
+      else          QmM = {FirstS[`DIVb-1-(`RADIX/4):0], 1'b0};
+    else  
+      if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0];
+      else          QmM = FirstQ[`DIVb-(`RADIX/4):0];
+
 endmodule
\ No newline at end of file