From 459f4bd3b4125b2e64c6873149abdaa194ed555e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 8 Jan 2022 14:21:58 -0600 Subject: [PATCH] Hack "fix" to prevent interrupt from occuring during an integer divide. This is not the desired solution but will allow continued debuging of linux. --- pipelined/src/ifu/ifu.sv | 1 + pipelined/src/muldiv/muldiv.sv | 2 +- pipelined/src/privileged/privileged.sv | 4 ++-- pipelined/src/privileged/trap.sv | 6 ++++-- pipelined/src/wally/wallypipelinedhart.sv | 7 ++++--- 5 files changed, 12 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2dd67bf1..7d1fe5d3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -360,6 +360,7 @@ module ifu ( assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment + // *** double check this enable. It cannot be correct. flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF); // branch and jump predictor diff --git a/pipelined/src/muldiv/muldiv.sv b/pipelined/src/muldiv/muldiv.sv index da1e5e1d..d7d063c4 100644 --- a/pipelined/src/muldiv/muldiv.sv +++ b/pipelined/src/muldiv/muldiv.sv @@ -41,6 +41,7 @@ module muldiv ( output logic [`XLEN-1:0] MDUResultW, // Divide Done output logic DivBusyE, + output logic DivE, // hazards input logic StallM, StallW, FlushM, FlushW ); @@ -50,7 +51,6 @@ module muldiv ( logic [`XLEN-1:0] QuotM, RemM; logic [`XLEN*2-1:0] ProdM; - logic DivE; logic DivSignedE; logic W64M; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 0c0e3184..8f58fd13 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -39,7 +39,7 @@ module privileged ( output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, output logic ITLBFlushF, DTLBFlushM, - input logic InstrValidM, CommittedM, + input logic InstrValidM, CommittedM, DivE, input logic FRegWriteM, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, @@ -230,7 +230,7 @@ module privileged ( .PCM, .InstrMisalignedAdrM, .IEUAdrM, .InstrM, - .InstrValidM, .CommittedM, + .InstrValidM, .CommittedM, .DivE, .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .InterruptM, .ExceptionM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 3c70c108..057f678b 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -46,7 +46,7 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [31:0] InstrM, - input logic InstrValidM, CommittedM, + input logic InstrValidM, CommittedM, DivE, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic ExceptionM, @@ -71,7 +71,9 @@ module trap ( assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); assign PendingInterruptM = (|PendingIntsM) & InstrValidM; - assign InterruptM = PendingInterruptM & ~CommittedM; + assign InterruptM = PendingInterruptM & (~CommittedM | ~DivE); // *** RT. temporary hack to prevent integer division from having an interrupt during divide. + // ideally this should be disabled for all but the first cycle. However I'm not familar with the internals of the integer divider. This should (could) be an issue for + // floating point and integer multiply. //assign ExceptionM = TrapM; assign ExceptionM = Exception1M; // *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M diff --git a/pipelined/src/wally/wallypipelinedhart.sv b/pipelined/src/wally/wallypipelinedhart.sv index 6d798b3f..48e1c1c3 100644 --- a/pipelined/src/wally/wallypipelinedhart.sv +++ b/pipelined/src/wally/wallypipelinedhart.sv @@ -87,11 +87,12 @@ module wallypipelinedhart ( logic PCSrcE; logic CSRWritePendingDEM; logic DivBusyE; + logic DivE; logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; - logic [4:0] RdM, RdW; + logic [4:0] RdM, RdW; logic FStallD; logic FWriteIntE; logic [`XLEN-1:0] FWriteDataE; @@ -321,7 +322,7 @@ module wallypipelinedhart ( .InstrM, .CSRReadValW, .PrivilegedNextPCM, .RetM, .TrapM, .ITLBFlushF, .DTLBFlushM, - .InstrValidM, .CommittedM, + .InstrValidM, .CommittedM, .DivE, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, @@ -356,7 +357,7 @@ module wallypipelinedhart ( .clk, .reset, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, - .MDUResultW, .DivBusyE, + .MDUResultW, .DivBusyE, .DivE, .StallM, .StallW, .FlushM, .FlushW ); end else begin // no M instructions supported