diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index 527a2428..3ee6c42e 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -48,13 +48,15 @@ module bmuctrl(
   output logic [2:0]  ALUSelectE,
   output logic [3:0]  BSelectE,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
   output logic [2:0]  ZBBSelectE,              // ZBB mux select signal
-  output logic        BRegWriteE               // Indicates if it is a R type B instruction in Execute
+  output logic        BRegWriteE,              // Indicates if it is a R type B instruction in Execute
+  output logic        BComparatorSignedE       // Indicates if comparator signed in Execute Stage
 );
 
   logic [6:0] OpD;                             // Opcode in Decode stage
   logic [2:0] Funct3D;                         // Funct3 field in Decode stage
   logic [6:0] Funct7D;                         // Funct7 field in Decode stage
   logic [4:0] Rs2D;                            // Rs2 source register in Decode stage
+  logic       BComparatorSignedD;              // Indicates if comparator signed (max, min instruction) in Decode Stage
 
   `define BMUCTRLW 15
 
@@ -158,8 +160,11 @@ module bmuctrl(
   // Unpack Control Signals
   assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD;
 
+  // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches
+  assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6];
+
    
 
   // BMU Execute stage pipieline control register
-  flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE});
+  flopenrc#(12) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE});
 endmodule
\ No newline at end of file
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index ec54394e..9ea091e3 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -126,9 +126,10 @@ module controller(
   logic [3:0]  BSelectD;                       // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
   logic [2:0]  ZBBSelectD;                     // ZBB Mux Select Signal
   logic        BRegWriteD;                     // Indicates if it is a R type B instruction in decode stage
-  logic        BW64D;                          // Indiciates if it is a W type B instruction in decode stage
+  logic        BW64D;                          // Indicates if it is a W type B instruction in decode stage
   logic        BALUOpD;                        // Indicates if it is an ALU B instruction in decode stage
   logic        BSubArithD;                     // TRUE for B-type ext, clr, andn, orn, xnor
+  logic        BComparatorSignedE;             // Indicates if max, min (signed comarison) instruction in Execute Stage
    
 
   // Extract fields
@@ -243,7 +244,8 @@ module controller(
 
   // BITMANIP Configuration Block
   if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
-    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
+    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE);
+
 
     //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
   end else begin: bitmanipi
@@ -257,6 +259,7 @@ module controller(
     assign BALUOpD = 1'b0;
     assign BRegWriteE = 1'b0;
     assign BSubArithD = 1'b0;
+    assign BComparatorSignedE = 1'b0;
 
 
     assign IllegalBitmanipInstrD = 1'b1;
@@ -286,8 +289,8 @@ module controller(
   // Branch Logic
   //  The comparator handles both signed and unsigned branches using BranchSignedE
   //  Hence, only eq and lt flags are needed
-  assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & ~BSelectE[2]) | (`ZBB_SUPPORTED & (maxE | minE)) ;
-  //assign BranchSignedE = ~(Funct3E[2:1] == 2'b11);
+  //  We also want comparator to handle signed comparison on a max/min bitmanip instruction
+  assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE ;
   assign {eqE, ltE} = FlagsE;
   mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];