From a9e884acc803c5db4bf54b558d5a70b5cab9551a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 17:28:05 -0800 Subject: [PATCH 1/8] Moved TLB into subdirectory of MMU --- src/mmu/tlb/tlb.sv | 121 +++++++++++++++++++++++++++++++++ src/mmu/tlb/tlbcam.sv | 62 +++++++++++++++++ src/mmu/tlb/tlbcamline.sv | 106 +++++++++++++++++++++++++++++ src/mmu/tlb/tlbcontrol.sv | 113 ++++++++++++++++++++++++++++++ src/mmu/tlb/tlblru.sv | 56 +++++++++++++++ src/mmu/tlb/tlbmixer.sv | 69 +++++++++++++++++++ src/mmu/tlb/tlbram.sv | 54 +++++++++++++++ src/mmu/tlb/tlbramline.sv | 43 ++++++++++++ src/mmu/{ => tlb}/vm64check.sv | 6 +- 9 files changed, 627 insertions(+), 3 deletions(-) create mode 100644 src/mmu/tlb/tlb.sv create mode 100644 src/mmu/tlb/tlbcam.sv create mode 100644 src/mmu/tlb/tlbcamline.sv create mode 100644 src/mmu/tlb/tlbcontrol.sv create mode 100644 src/mmu/tlb/tlblru.sv create mode 100644 src/mmu/tlb/tlbmixer.sv create mode 100644 src/mmu/tlb/tlbram.sv create mode 100644 src/mmu/tlb/tlbramline.sv rename src/mmu/{ => tlb}/vm64check.sv (90%) diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv new file mode 100644 index 00000000..f8bf0d17 --- /dev/null +++ b/src/mmu/tlb/tlb.sv @@ -0,0 +1,121 @@ +/////////////////////////////////////////// +// tlb.sv +// +// Written: jtorrey@hmc.edu 16 February 2021 +// Modified: kmacsaigoren@hmc.edu 1 June 2021 +// Implemented SV48 on top of SV39. This included adding the SvMode signal, +// and using it to decide the translate signal and get the virtual page number +// +// Purpose: Translation lookaside buffer +// Cache of virtural-to-physical address translations +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +/** + * SV32 specs + * ---------- + * Virtual address [31:0] (32 bits) + * [________________________________] + * |--VPN1--||--VPN0--||----OFF---| + * 10 10 12 + * + * Physical address [33:0] (34 bits) + * [__________________________________] + * |---PPN1---||--PPN0--||----OFF---| + * 12 10 12 + * + * Page Table Entry [31:0] (32 bits) + * [________________________________] + * |---PPN1---||--PPN0--|||DAGUXWRV + * 12 10 ^^ + * RSW(2) -- for OS + */ + +`include "wally-config.vh" + +// The TLB will have 2**ENTRY_BITS total entries +module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) ( + input logic clk, reset, + input logic [`SVMODE_BITS-1:0] SATP_MODE, // Current address translation mode + input logic [`ASID_BITS-1:0] SATP_ASID, + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, + input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor + input logic ReadAccess, + input logic WriteAccess, + input logic DisableTranslation, + input logic [`XLEN-1:0] VAdr, // address input before translation (could be physical or virtual) + input logic [`XLEN-1:0] PTE, + input logic [1:0] PageTypeWriteVal, + input logic TLBWrite, + input logic TLBFlush, + output logic [`PA_BITS-1:0] TLBPAdr, + output logic TLBMiss, + output logic TLBHit, + output logic Translate, + output logic TLBPageFault, + output logic DAPageFault +); + + logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex + // Sections of the virtual and physical addresses + logic [`VPN_BITS-1:0] VPN; + logic [`PPN_BITS-1:0] PPN; + // Sections of the page table entry + logic [7:0] PTEAccessBits; + logic [1:0] HitPageType; + logic CAMHit; + logic SV39Mode; + logic Misaligned; + logic MegapageMisaligned; + + if(`XLEN == 32) begin + assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 + assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned; + end else begin // 64-bit + logic GigapageMisaligned, TerapageMisaligned; + assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0 + assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0 + assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0 + assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) | + ((HitPageType == 2'b10) & GigapageMisaligned) | + ((HitPageType == 2'b01) & MegapageMisaligned); + end + + assign VPN = VAdr[`VPN_BITS+11:12]; + + tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, + .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, + .DAPageFault, .SV39Mode, .Translate); + + tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables); + tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) + tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, + .SATP_ASID, .Matches, .HitPageType, .CAMHit); + tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs); + + // Replace segments of the virtual page number with segments of the physical + // page number. For 4 KB pages, the entire virtual page number is replaced. + // For superpages, some segments are considered offsets into a larger page. + tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr); + +endmodule diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv new file mode 100644 index 00000000..449411e2 --- /dev/null +++ b/src/mmu/tlb/tlbcam.sv @@ -0,0 +1,62 @@ +/////////////////////////////////////////// +// tlbcam.sv +// +// Written: jtorrey@hmc.edu 16 February 2021 +// Modified: kmacsaigoren@hmc.edu 1 June 2021 +// Implemented SV48 on top of SV39. This included adding the SvMode signal input and wally constants +// Mostly this was to make the cam_lines work. +// +// Purpose: Stores virtual page numbers with cached translations. +// Determines whether a given virtual page number is in the TLB. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) ( + input logic clk, reset, + input logic [`VPN_BITS-1:0] VPN, + input logic [1:0] PageTypeWriteVal, + input logic SV39Mode, + input logic TLBFlush, + input logic [TLB_ENTRIES-1:0] WriteEnables, + input logic [TLB_ENTRIES-1:0] PTE_Gs, + input logic [`ASID_BITS-1:0] SATP_ASID, + output logic [TLB_ENTRIES-1:0] Matches, + output logic [1:0] HitPageType, + output logic CAMHit +); + + logic [1:0] PageTypeRead [TLB_ENTRIES-1:0]; + + // TLB_ENTRIES CAM lines, each of which will independently consider + // whether the requested virtual address is a match. Each line stores the + // original virtual page number from when the address was written, regardless + // of page type. However, matches are determined based on a subset of the + // page number segments. + + tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0]( + .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush, + .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); + assign CAMHit = |Matches & ~TLBFlush; + or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType); +endmodule + diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv new file mode 100644 index 00000000..9f7a68e8 --- /dev/null +++ b/src/mmu/tlb/tlbcamline.sv @@ -0,0 +1,106 @@ +/////////////////////////////////////////// +// tlbcamline.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021 +// Modified: kmacsaigoren@hmc.edu 1 June 2021 +// Implemented SV48 on top of SV39. This included adding SvMode input signal and the wally constants +// Mostly this was done to make the PageNumberMixer work. +// +// Purpose: CAM line for the translation lookaside buffer (TLB) +// Determines whether a virtual page number matches the stored key. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) ( + input logic clk, reset, + input logic [`VPN_BITS-1:0] VPN, // The requested page number to compare against the key + input logic [`ASID_BITS-1:0] SATP_ASID, + input logic SV39Mode, + input logic WriteEnable, // Write a new entry to this line + input logic PTE_G, + input logic [1:0] PageTypeWriteVal, + input logic TLBFlush, // Flush this line (set valid to 0) + output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one? + output logic Match +); + + // PageTypeRead is a key for a tera, giga, mega, or kilopage. + // PageType == 2'b00 --> kilopage + // PageType == 2'b01 --> megapage + // PageType == 2'b10 --> gigapage + // PageType == 2'b11 --> terapage + + // This entry has KEY_BITS for the key plus one valid bit. + logic Valid; + logic [KEY_BITS-1:0] Key; + logic [1:0] PageType; + + // Split up key and query into sections for each page table level. + logic [`ASID_BITS-1:0] Key_ASID; + logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1; + logic MatchASID, Match0, Match1; + + assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; + + if (`XLEN == 32) begin: match + + assign {Key_ASID, Key1, Key0} = Key; + assign {Query1, Query0} = VPN; + + // Calculate the actual match value based on the input vpn and the page type. + // For example, a megapage in SV32 only cares about VPN[1], so VPN[0] + // should automatically match. + assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section + assign Match1 = (Query1 == Key1); + + assign Match = Match0 & Match1 & MatchASID & Valid; + end else begin: match + + logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3; + logic Match2, Match3; + + assign {Query3, Query2, Query1, Query0} = VPN; + assign {Key_ASID, Key3, Key2, Key1, Key0} = Key; + + // Calculate the actual match value based on the input vpn and the page type. + // For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1] + // should automatically match. + assign Match0 = (Query0 == Key0) | (PageType > 2'd0); // least signifcant section + assign Match1 = (Query1 == Key1) | (PageType > 2'd1); + assign Match2 = (Query2 == Key2) | (PageType > 2'd2); + assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used + + assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid; + end + + // On a write, update the type of the page referred to by this line. + flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType); + assign PageTypeRead = PageType & {2{Match}}; + + // On a write, set the valid bit high and update the stored key. + // On a flush, zero the valid bit and leave the key unchanged. + // *** Might we want to update stored key right away to output match on the + // write cycle? (using a mux) + flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid); + flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key); +endmodule diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv new file mode 100644 index 00000000..45c56f1b --- /dev/null +++ b/src/mmu/tlb/tlbcontrol.sv @@ -0,0 +1,113 @@ +/////////////////////////////////////////// +// tlbcontrol.sv +// +// Written: David_Harris@hmc.edu 5 July 2021 +// Modified: +// +// Purpose: Control signals for TLB +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbcontrol #(parameter ITLB = 0) ( + input logic [`SVMODE_BITS-1:0] SATP_MODE, + input logic [`XLEN-1:0] VAdr, + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, + input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor + input logic ReadAccess, WriteAccess, + input logic DisableTranslation, + input logic TLBFlush, // Invalidate all TLB entries + input logic [7:0] PTEAccessBits, + input logic CAMHit, + input logic Misaligned, + output logic TLBMiss, + output logic TLBHit, + output logic TLBPageFault, + output logic DAPageFault, + output logic SV39Mode, + output logic Translate +); + + // Sections of the page table entry + logic [1:0] EffectivePrivilegeMode; + + logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits + logic UpperBitsUnequal; + logic TLBAccess; + logic ImproperPrivilege; + + // Grab the sv mode from SATP and determine whether translation should occur + assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 + assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; + + // Determine whether TLB is being used + assign TLBAccess = ReadAccess | WriteAccess; + + // Check that upper bits are legal (all 0s or all 1s) + vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal); + + // unswizzle useful PTE bits + assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; + assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0]; + + // Check whether the access is allowed, page faulting if not. + if (ITLB == 1) begin:itlb // Instruction TLB fault checking + // User mode may only execute user mode pages, and supervisor mode may + // only execute non-user mode pages. + assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | + ((EffectivePrivilegeMode == `S_MODE) & PTE_U); + if(`SVADU_SUPPORTED) begin : hptwwrites + assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V)); + end else begin + // fault for software handling if access bit is off + assign DAPageFault = ~PTE_A; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequal | Misaligned | ~PTE_V)); + end + end else begin:dtlb // Data TLB fault checking + logic InvalidRead, InvalidWrite; + + // User mode may only load/store from user mode pages, and supervisor mode + // may only access user mode pages when STATUS_SUM is low. + assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | + ((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM); + // Check for read error. Reads are invalid when the page is not readable + // (and executable pages are not readable) or when the page is neither + // readable nor executable (and executable pages are readable). + assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X); + // Check for write error. Writes are invalid when the page's write bit is + // low. + assign InvalidWrite = WriteAccess & ~PTE_W; + if(`SVADU_SUPPORTED) begin : hptwwrites + assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V)); + end else begin + // Fault for software handling if access bit is off or writing a page with dirty bit off + assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequal | Misaligned | ~PTE_V)); + end + end + + assign TLBHit = CAMHit & TLBAccess; + assign TLBMiss = ~CAMHit & TLBAccess & Translate ; +endmodule diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv new file mode 100644 index 00000000..6cdb475e --- /dev/null +++ b/src/mmu/tlb/tlblru.sv @@ -0,0 +1,56 @@ +/////////////////////////////////////////// +// tlblru.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 16 February 2021 +// Modified: +// +// Purpose: Implementation of bit pseudo least-recently-used algorithm for +// cache evictions. Outputs the index of the next entry to be written. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module tlblru #(parameter TLB_ENTRIES = 8) ( + input logic clk, reset, + input logic TLBWrite, + input logic TLBFlush, + input logic [TLB_ENTRIES-1:0] Matches, + input logic CAMHit, + output logic [TLB_ENTRIES-1:0] WriteEnables +); + + logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed; + logic [TLB_ENTRIES-1:0] WriteLines; + logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed + logic AllUsed; // High if the next access causes all RU bits to be 1 + + // Find the first line not recently used + priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines)); + + // Track recently used lines, updating on a CAM Hit or TLB write + assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}}; + assign AccessLines = TLBWrite ? WriteLines : Matches; + assign RUBitsAccessed = AccessLines | RUBits; + assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none + assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; + + // enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 + flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); +endmodule diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv new file mode 100644 index 00000000..f5555c2a --- /dev/null +++ b/src/mmu/tlb/tlbmixer.sv @@ -0,0 +1,69 @@ +/////////////////////////////////////////// +// tlbmixer.sv +// +// Written: David Harris and kmacsaigoren@hmc.edu 7 June 2021 +// Modified: +// +// +// Purpose: Takes two page numbers and replaces segments of the first page +// number with segments from the second, based on the page type. +// NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbmixer ( + input logic [`VPN_BITS-1:0] VPN, + input logic [`PPN_BITS-1:0] PPN, + input logic [1:0] HitPageType, + input logic [11:0] Offset, + input logic TLBHit, + output logic [`PA_BITS-1:0] TLBPAdr +); + + localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS; + logic [`PPN_BITS-1:0] ZeroExtendedVPN; + logic [`PPN_BITS-1:0] PageNumberMask; + logic [`PPN_BITS-1:0] PPNMixed; + + // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages + if (`XLEN == 32) + // kilopage: 22 bits of PPN, 0 bits of VPN + // megapage: 12 bits of PPN, 10 bits of VPN + mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask); + else + // kilopage: 44 bits of PPN, 0 bits of VPN + // megapage: 35 bits of PPN, 9 bits of VPN + // gigapage: 26 bits of PPN, 18 bits of VPN + // terapage: 17 bits of PPN, 27 bits of VPN + mux4 #(44) pnm(44'h00000000000, 44'h000000001FF, 44'h0000003FFFF, 44'h00007FFFFFF, HitPageType, PageNumberMask); + + // merge low segments of VPN with high segments of PPN decided by the pagetype. + assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN. + assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // + //mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed); + //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask); + // Output the hit physical address if translation is currently on. + // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal + mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system + +endmodule diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv new file mode 100644 index 00000000..febb8b6f --- /dev/null +++ b/src/mmu/tlb/tlbram.sv @@ -0,0 +1,54 @@ +/////////////////////////////////////////// +// tlbram.sv +// +// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021 +// Modified: +// +// Purpose: Stores page table entries of cached address translations. +// Outputs the physical page number and access bits of the current +// virtual address on a TLB hit. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbram #(parameter TLB_ENTRIES = 8) ( + input logic clk, reset, + input logic [`XLEN-1:0] PTE, + input logic [TLB_ENTRIES-1:0] Matches, WriteEnables, + output logic [`PPN_BITS-1:0] PPN, + output logic [7:0] PTEAccessBits, + output logic [TLB_ENTRIES-1:0] PTE_Gs +); + + logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0]; + logic [`PPN_BITS+9:0] PageTableEntry; + + // RAM implemented with array of flops and AND/OR read logic + tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0] + (.clk, .reset, .re(Matches), .we(WriteEnables), + .d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs)); + or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry); + + // Rename the bits read from the TLB RAM + assign PTEAccessBits = PageTableEntry[7:0]; + assign PPN = PageTableEntry[`PPN_BITS+9:10]; +endmodule diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv new file mode 100644 index 00000000..035c58d5 --- /dev/null +++ b/src/mmu/tlb/tlbramline.sv @@ -0,0 +1,43 @@ +/////////////////////////////////////////// +// tlbramline.sv +// +// Written: David_Harris@hmc.edu 4 July 2021 +// Modified: +// +// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbramline #(parameter WIDTH = 22) + (input logic clk, reset, + input logic re, we, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q, + output logic PTE_G); + + logic [WIDTH-1:0] line; + + flopenr #(WIDTH) pteflop(clk, reset, we, d, line); + assign q = re ? line : 0; + assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching +endmodule diff --git a/src/mmu/vm64check.sv b/src/mmu/tlb/vm64check.sv similarity index 90% rename from src/mmu/vm64check.sv rename to src/mmu/tlb/vm64check.sv index a78b853e..5f12eef7 100644 --- a/src/mmu/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -32,7 +32,7 @@ module vm64check ( input logic [`SVMODE_BITS-1:0] SATP_MODE, input logic [`XLEN-1:0] VAdr, output logic SV39Mode, - output logic UpperBitsUnequalPageFault + output logic UpperBitsUnequal ); if (`XLEN == 64) begin @@ -42,9 +42,9 @@ module vm64check ( logic eq_63_47, eq_46_38; assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); - assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; + assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; end else begin assign SV39Mode = 0; - assign UpperBitsUnequalPageFault = 0; + assign UpperBitsUnequal = 0; end endmodule From 099267ffcea29b7ada4c18eb307ba0667617cd7e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 17:31:03 -0800 Subject: [PATCH 2/8] moved tlb to subdirectory --- src/mmu/tlb.sv | 121 ------------------------------------------ src/mmu/tlbcam.sv | 62 ---------------------- src/mmu/tlbcamline.sv | 106 ------------------------------------ src/mmu/tlbcontrol.sv | 113 --------------------------------------- src/mmu/tlblru.sv | 56 ------------------- src/mmu/tlbmixer.sv | 69 ------------------------ src/mmu/tlbram.sv | 54 ------------------- src/mmu/tlbramline.sv | 43 --------------- 8 files changed, 624 deletions(-) delete mode 100644 src/mmu/tlb.sv delete mode 100644 src/mmu/tlbcam.sv delete mode 100644 src/mmu/tlbcamline.sv delete mode 100644 src/mmu/tlbcontrol.sv delete mode 100644 src/mmu/tlblru.sv delete mode 100644 src/mmu/tlbmixer.sv delete mode 100644 src/mmu/tlbram.sv delete mode 100644 src/mmu/tlbramline.sv diff --git a/src/mmu/tlb.sv b/src/mmu/tlb.sv deleted file mode 100644 index f8bf0d17..00000000 --- a/src/mmu/tlb.sv +++ /dev/null @@ -1,121 +0,0 @@ -/////////////////////////////////////////// -// tlb.sv -// -// Written: jtorrey@hmc.edu 16 February 2021 -// Modified: kmacsaigoren@hmc.edu 1 June 2021 -// Implemented SV48 on top of SV39. This included adding the SvMode signal, -// and using it to decide the translate signal and get the virtual page number -// -// Purpose: Translation lookaside buffer -// Cache of virtural-to-physical address translations -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -/** - * SV32 specs - * ---------- - * Virtual address [31:0] (32 bits) - * [________________________________] - * |--VPN1--||--VPN0--||----OFF---| - * 10 10 12 - * - * Physical address [33:0] (34 bits) - * [__________________________________] - * |---PPN1---||--PPN0--||----OFF---| - * 12 10 12 - * - * Page Table Entry [31:0] (32 bits) - * [________________________________] - * |---PPN1---||--PPN0--|||DAGUXWRV - * 12 10 ^^ - * RSW(2) -- for OS - */ - -`include "wally-config.vh" - -// The TLB will have 2**ENTRY_BITS total entries -module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) ( - input logic clk, reset, - input logic [`SVMODE_BITS-1:0] SATP_MODE, // Current address translation mode - input logic [`ASID_BITS-1:0] SATP_ASID, - input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, - input logic [1:0] STATUS_MPP, - input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor - input logic ReadAccess, - input logic WriteAccess, - input logic DisableTranslation, - input logic [`XLEN-1:0] VAdr, // address input before translation (could be physical or virtual) - input logic [`XLEN-1:0] PTE, - input logic [1:0] PageTypeWriteVal, - input logic TLBWrite, - input logic TLBFlush, - output logic [`PA_BITS-1:0] TLBPAdr, - output logic TLBMiss, - output logic TLBHit, - output logic Translate, - output logic TLBPageFault, - output logic DAPageFault -); - - logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex - // Sections of the virtual and physical addresses - logic [`VPN_BITS-1:0] VPN; - logic [`PPN_BITS-1:0] PPN; - // Sections of the page table entry - logic [7:0] PTEAccessBits; - logic [1:0] HitPageType; - logic CAMHit; - logic SV39Mode; - logic Misaligned; - logic MegapageMisaligned; - - if(`XLEN == 32) begin - assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 - assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned; - end else begin // 64-bit - logic GigapageMisaligned, TerapageMisaligned; - assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0 - assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0 - assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0 - assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) | - ((HitPageType == 2'b10) & GigapageMisaligned) | - ((HitPageType == 2'b01) & MegapageMisaligned); - end - - assign VPN = VAdr[`VPN_BITS+11:12]; - - tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, - .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, - .DAPageFault, .SV39Mode, .Translate); - - tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables); - tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) - tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, - .SATP_ASID, .Matches, .HitPageType, .CAMHit); - tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs); - - // Replace segments of the virtual page number with segments of the physical - // page number. For 4 KB pages, the entire virtual page number is replaced. - // For superpages, some segments are considered offsets into a larger page. - tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr); - -endmodule diff --git a/src/mmu/tlbcam.sv b/src/mmu/tlbcam.sv deleted file mode 100644 index 449411e2..00000000 --- a/src/mmu/tlbcam.sv +++ /dev/null @@ -1,62 +0,0 @@ -/////////////////////////////////////////// -// tlbcam.sv -// -// Written: jtorrey@hmc.edu 16 February 2021 -// Modified: kmacsaigoren@hmc.edu 1 June 2021 -// Implemented SV48 on top of SV39. This included adding the SvMode signal input and wally constants -// Mostly this was to make the cam_lines work. -// -// Purpose: Stores virtual page numbers with cached translations. -// Determines whether a given virtual page number is in the TLB. -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) ( - input logic clk, reset, - input logic [`VPN_BITS-1:0] VPN, - input logic [1:0] PageTypeWriteVal, - input logic SV39Mode, - input logic TLBFlush, - input logic [TLB_ENTRIES-1:0] WriteEnables, - input logic [TLB_ENTRIES-1:0] PTE_Gs, - input logic [`ASID_BITS-1:0] SATP_ASID, - output logic [TLB_ENTRIES-1:0] Matches, - output logic [1:0] HitPageType, - output logic CAMHit -); - - logic [1:0] PageTypeRead [TLB_ENTRIES-1:0]; - - // TLB_ENTRIES CAM lines, each of which will independently consider - // whether the requested virtual address is a match. Each line stores the - // original virtual page number from when the address was written, regardless - // of page type. However, matches are determined based on a subset of the - // page number segments. - - tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0]( - .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush, - .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); - assign CAMHit = |Matches & ~TLBFlush; - or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType); -endmodule - diff --git a/src/mmu/tlbcamline.sv b/src/mmu/tlbcamline.sv deleted file mode 100644 index 9f7a68e8..00000000 --- a/src/mmu/tlbcamline.sv +++ /dev/null @@ -1,106 +0,0 @@ -/////////////////////////////////////////// -// tlbcamline.sv -// -// Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021 -// Modified: kmacsaigoren@hmc.edu 1 June 2021 -// Implemented SV48 on top of SV39. This included adding SvMode input signal and the wally constants -// Mostly this was done to make the PageNumberMixer work. -// -// Purpose: CAM line for the translation lookaside buffer (TLB) -// Determines whether a virtual page number matches the stored key. -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) ( - input logic clk, reset, - input logic [`VPN_BITS-1:0] VPN, // The requested page number to compare against the key - input logic [`ASID_BITS-1:0] SATP_ASID, - input logic SV39Mode, - input logic WriteEnable, // Write a new entry to this line - input logic PTE_G, - input logic [1:0] PageTypeWriteVal, - input logic TLBFlush, // Flush this line (set valid to 0) - output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one? - output logic Match -); - - // PageTypeRead is a key for a tera, giga, mega, or kilopage. - // PageType == 2'b00 --> kilopage - // PageType == 2'b01 --> megapage - // PageType == 2'b10 --> gigapage - // PageType == 2'b11 --> terapage - - // This entry has KEY_BITS for the key plus one valid bit. - logic Valid; - logic [KEY_BITS-1:0] Key; - logic [1:0] PageType; - - // Split up key and query into sections for each page table level. - logic [`ASID_BITS-1:0] Key_ASID; - logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1; - logic MatchASID, Match0, Match1; - - assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; - - if (`XLEN == 32) begin: match - - assign {Key_ASID, Key1, Key0} = Key; - assign {Query1, Query0} = VPN; - - // Calculate the actual match value based on the input vpn and the page type. - // For example, a megapage in SV32 only cares about VPN[1], so VPN[0] - // should automatically match. - assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section - assign Match1 = (Query1 == Key1); - - assign Match = Match0 & Match1 & MatchASID & Valid; - end else begin: match - - logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3; - logic Match2, Match3; - - assign {Query3, Query2, Query1, Query0} = VPN; - assign {Key_ASID, Key3, Key2, Key1, Key0} = Key; - - // Calculate the actual match value based on the input vpn and the page type. - // For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1] - // should automatically match. - assign Match0 = (Query0 == Key0) | (PageType > 2'd0); // least signifcant section - assign Match1 = (Query1 == Key1) | (PageType > 2'd1); - assign Match2 = (Query2 == Key2) | (PageType > 2'd2); - assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used - - assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid; - end - - // On a write, update the type of the page referred to by this line. - flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType); - assign PageTypeRead = PageType & {2{Match}}; - - // On a write, set the valid bit high and update the stored key. - // On a flush, zero the valid bit and leave the key unchanged. - // *** Might we want to update stored key right away to output match on the - // write cycle? (using a mux) - flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid); - flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key); -endmodule diff --git a/src/mmu/tlbcontrol.sv b/src/mmu/tlbcontrol.sv deleted file mode 100644 index 04af0f2a..00000000 --- a/src/mmu/tlbcontrol.sv +++ /dev/null @@ -1,113 +0,0 @@ -/////////////////////////////////////////// -// tlbcontrol.sv -// -// Written: David_Harris@hmc.edu 5 July 2021 -// Modified: -// -// Purpose: Control signals for TLB -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module tlbcontrol #(parameter ITLB = 0) ( - input logic [`SVMODE_BITS-1:0] SATP_MODE, - input logic [`XLEN-1:0] VAdr, - input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, - input logic [1:0] STATUS_MPP, - input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor - input logic ReadAccess, WriteAccess, - input logic DisableTranslation, - input logic TLBFlush, // Invalidate all TLB entries - input logic [7:0] PTEAccessBits, - input logic CAMHit, - input logic Misaligned, - output logic TLBMiss, - output logic TLBHit, - output logic TLBPageFault, - output logic DAPageFault, - output logic SV39Mode, - output logic Translate -); - - // Sections of the page table entry - logic [1:0] EffectivePrivilegeMode; - - logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits - logic UpperBitsUnequalPageFault; - logic TLBAccess; - logic ImproperPrivilege; - - // Grab the sv mode from SATP and determine whether translation should occur - assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 - assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; - - // Determine whether TLB is being used - assign TLBAccess = ReadAccess | WriteAccess; - - // Check that upper bits are legal (all 0s or all 1s) - vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault); - - // unswizzle useful PTE bits - assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; - assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0]; - - // Check whether the access is allowed, page faulting if not. - if (ITLB == 1) begin:itlb // Instruction TLB fault checking - // User mode may only execute user mode pages, and supervisor mode may - // only execute non-user mode pages. - assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | - ((EffectivePrivilegeMode == `S_MODE) & PTE_U); - if(`SVADU_SUPPORTED) begin : hptwwrites - assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); - end else begin - // fault for software handling if access bit is off - assign DAPageFault = ~PTE_A; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); - end - end else begin:dtlb // Data TLB fault checking - logic InvalidRead, InvalidWrite; - - // User mode may only load/store from user mode pages, and supervisor mode - // may only access user mode pages when STATUS_SUM is low. - assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | - ((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM); - // Check for read error. Reads are invalid when the page is not readable - // (and executable pages are not readable) or when the page is neither - // readable nor executable (and executable pages are readable). - assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X); - // Check for write error. Writes are invalid when the page's write bit is - // low. - assign InvalidWrite = WriteAccess & ~PTE_W; - if(`SVADU_SUPPORTED) begin : hptwwrites - assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); - end else begin - // Fault for software handling if access bit is off or writing a page with dirty bit off - assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); - end - end - - assign TLBHit = CAMHit & TLBAccess; - assign TLBMiss = ~CAMHit & TLBAccess & Translate ; -endmodule diff --git a/src/mmu/tlblru.sv b/src/mmu/tlblru.sv deleted file mode 100644 index 6cdb475e..00000000 --- a/src/mmu/tlblru.sv +++ /dev/null @@ -1,56 +0,0 @@ -/////////////////////////////////////////// -// tlblru.sv -// -// Written: tfleming@hmc.edu & jtorrey@hmc.edu 16 February 2021 -// Modified: -// -// Purpose: Implementation of bit pseudo least-recently-used algorithm for -// cache evictions. Outputs the index of the next entry to be written. -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module tlblru #(parameter TLB_ENTRIES = 8) ( - input logic clk, reset, - input logic TLBWrite, - input logic TLBFlush, - input logic [TLB_ENTRIES-1:0] Matches, - input logic CAMHit, - output logic [TLB_ENTRIES-1:0] WriteEnables -); - - logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed; - logic [TLB_ENTRIES-1:0] WriteLines; - logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed - logic AllUsed; // High if the next access causes all RU bits to be 1 - - // Find the first line not recently used - priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines)); - - // Track recently used lines, updating on a CAM Hit or TLB write - assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}}; - assign AccessLines = TLBWrite ? WriteLines : Matches; - assign RUBitsAccessed = AccessLines | RUBits; - assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none - assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; - - // enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 - flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); -endmodule diff --git a/src/mmu/tlbmixer.sv b/src/mmu/tlbmixer.sv deleted file mode 100644 index f5555c2a..00000000 --- a/src/mmu/tlbmixer.sv +++ /dev/null @@ -1,69 +0,0 @@ -/////////////////////////////////////////// -// tlbmixer.sv -// -// Written: David Harris and kmacsaigoren@hmc.edu 7 June 2021 -// Modified: -// -// -// Purpose: Takes two page numbers and replaces segments of the first page -// number with segments from the second, based on the page type. -// NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module tlbmixer ( - input logic [`VPN_BITS-1:0] VPN, - input logic [`PPN_BITS-1:0] PPN, - input logic [1:0] HitPageType, - input logic [11:0] Offset, - input logic TLBHit, - output logic [`PA_BITS-1:0] TLBPAdr -); - - localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS; - logic [`PPN_BITS-1:0] ZeroExtendedVPN; - logic [`PPN_BITS-1:0] PageNumberMask; - logic [`PPN_BITS-1:0] PPNMixed; - - // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages - if (`XLEN == 32) - // kilopage: 22 bits of PPN, 0 bits of VPN - // megapage: 12 bits of PPN, 10 bits of VPN - mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask); - else - // kilopage: 44 bits of PPN, 0 bits of VPN - // megapage: 35 bits of PPN, 9 bits of VPN - // gigapage: 26 bits of PPN, 18 bits of VPN - // terapage: 17 bits of PPN, 27 bits of VPN - mux4 #(44) pnm(44'h00000000000, 44'h000000001FF, 44'h0000003FFFF, 44'h00007FFFFFF, HitPageType, PageNumberMask); - - // merge low segments of VPN with high segments of PPN decided by the pagetype. - assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN. - assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // - //mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed); - //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask); - // Output the hit physical address if translation is currently on. - // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal - mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system - -endmodule diff --git a/src/mmu/tlbram.sv b/src/mmu/tlbram.sv deleted file mode 100644 index febb8b6f..00000000 --- a/src/mmu/tlbram.sv +++ /dev/null @@ -1,54 +0,0 @@ -/////////////////////////////////////////// -// tlbram.sv -// -// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021 -// Modified: -// -// Purpose: Stores page table entries of cached address translations. -// Outputs the physical page number and access bits of the current -// virtual address on a TLB hit. -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module tlbram #(parameter TLB_ENTRIES = 8) ( - input logic clk, reset, - input logic [`XLEN-1:0] PTE, - input logic [TLB_ENTRIES-1:0] Matches, WriteEnables, - output logic [`PPN_BITS-1:0] PPN, - output logic [7:0] PTEAccessBits, - output logic [TLB_ENTRIES-1:0] PTE_Gs -); - - logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0]; - logic [`PPN_BITS+9:0] PageTableEntry; - - // RAM implemented with array of flops and AND/OR read logic - tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0] - (.clk, .reset, .re(Matches), .we(WriteEnables), - .d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs)); - or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry); - - // Rename the bits read from the TLB RAM - assign PTEAccessBits = PageTableEntry[7:0]; - assign PPN = PageTableEntry[`PPN_BITS+9:10]; -endmodule diff --git a/src/mmu/tlbramline.sv b/src/mmu/tlbramline.sv deleted file mode 100644 index 035c58d5..00000000 --- a/src/mmu/tlbramline.sv +++ /dev/null @@ -1,43 +0,0 @@ -/////////////////////////////////////////// -// tlbramline.sv -// -// Written: David_Harris@hmc.edu 4 July 2021 -// Modified: -// -// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR -// -// Documentation: RISC-V System on Chip Design Chapter 8 -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module tlbramline #(parameter WIDTH = 22) - (input logic clk, reset, - input logic re, we, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q, - output logic PTE_G); - - logic [WIDTH-1:0] line; - - flopenr #(WIDTH) pteflop(clk, reset, we, d, line); - assign q = re ? line : 0; - assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching -endmodule From 246deeda8298324b78462a46a90ea1296fea218e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 17:32:34 -0800 Subject: [PATCH 3/8] renamed UpperBitsUnequalPageFault to UpperBitsUnequal --- src/mmu/hptw.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 19a3aca7..f77ca0c9 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -127,8 +127,8 @@ module hptw ( if(`SVADU_SUPPORTED) begin : hptwwrites logic ReadAccess, WriteAccess; - logic InvalidRead, InvalidWrite; - logic UpperBitsUnequalPageFault; + logic InvalidRead, InvalidWrite, InvalidOp; + logic UpperBitsUnequal; logic OtherPageFault; logic [1:0] EffectivePrivilegeMode; logic ImproperPrivilege; @@ -147,7 +147,7 @@ module hptw ( mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); assign {Dirty, Accessed} = PTE[7:6]; - assign WriteAccess = MemRWM[0] | (|AtomicM); + assign WriteAccess = MemRWM[0]; // implies | (|AtomicM); assign SetDirty = ~Dirty & DTLBWalk & WriteAccess; assign ReadAccess = MemRWM[1]; @@ -157,11 +157,11 @@ module hptw ( // Check for page faults vm64check vm64check(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), .VAdr(TranslationVAdr), - .SV39Mode(), .UpperBitsUnequalPageFault); + .SV39Mode(), .UpperBitsUnequal); assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable); assign InvalidWrite = WriteAccess & ~Writable; - assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid : - ImproperPrivilege | ~Executable | UpperBitsUnequalPageFault | Misaligned | ~Valid; + assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable; + assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid; // hptw needs to know if there is a Dirty or Access fault occuring on this // memory access. If there is the PTE needs to be updated seting Access From d2fd34efe6c3a85150c3493614067135ba3372ef Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 17:51:45 -0800 Subject: [PATCH 4/8] Renamed DAPageFault to UpdateDA --- src/ifu/ifu.sv | 8 ++++---- src/ifu/spill.sv | 4 ++-- src/lsu/lsu.sv | 8 ++++---- src/mmu/hptw.sv | 22 +++++++++++----------- src/mmu/mmu.sv | 4 ++-- src/mmu/tlb/tlb.sv | 4 ++-- src/mmu/tlb/tlbcontrol.sv | 16 ++++++++-------- src/wally/wallypipelinedcore.sv | 6 +++--- 8 files changed, 36 insertions(+), 36 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 71221ef6..887d1f45 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -88,7 +88,7 @@ module ifu ( input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk - output logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits + output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP address from privileged unit output logic InstrAccessFaultF, // Instruction access fault @@ -145,7 +145,7 @@ module ifu ( if(`C_SUPPORTED) begin : Spill spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, - .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); + .InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill assign PCNextFSpill = PCNextF; assign PCFSpill = PCF; @@ -185,12 +185,12 @@ module ifu ( .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(), .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(), .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(), - .DAPageFault(InstrDAPageFaultF), + .UpdateDA(InstrUpdateDAF), .AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin - assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0; + assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = '0; assign PCPF = PCFExt[`PA_BITS-1:0]; assign CacheableF = '1; assign SelIROM = '0; diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index a5b27463..4b89a3ce 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -42,7 +42,7 @@ module spill #( input logic [31:0] InstrRawF, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed input logic IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched input logic ITLBMissF, // ITLB miss, ignore memory request - input logic InstrDAPageFaultF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active) + input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active) output logic [`XLEN-1:0] PCNextFSpill, // The next PCF for one of the two memory addresses of the spill output logic [`XLEN-1:0] PCFSpill, // PCF for one of the two memory addresses of the spill output logic SelNextSpillF, // During the transition between the two spill operations, the IFU should stall the pipeline @@ -77,7 +77,7 @@ module spill #( //////////////////////////////////////////////////////////////////////////////////////////////////// assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; - assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`SVADU_SUPPORTED & InstrDAPageFaultF)); + assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF)); always_ff @(posedge clk) if (reset | FlushD) CurrState <= #1 STATE_READY; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index e01de312..18383e0d 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -81,7 +81,7 @@ module lsu ( input logic [1:0] STATUS_MPP, // Machine previous privilege mode input logic [`XLEN-1:0] PCFSpill, // Fetch PC input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk - input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits + input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB output logic [1:0] PageType, // Type of page table entry to write to ITLB output logic ITLBWriteF, // Write PTE to ITLB @@ -127,7 +127,7 @@ module lsu ( logic DTLBMissM; // DTLB miss causes HPTW walk logic DTLBWriteM; // Writes PTE and PageType to DTLB - logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits + logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits logic LSULoadAccessFaultM; // Load acces fault logic LSUStoreAmoAccessFaultM; // Store access fault logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle @@ -151,7 +151,7 @@ module lsu ( if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, - .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, + .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM, .FlushW, .DCacheStallM, .SATP_REGW, .PCFSpill, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN @@ -196,7 +196,7 @@ module lsu ( .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM, .StoreAmoPageFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw. - .DAPageFault(DataDAPageFaultM), + .UpdateDA(DataUpdateDAM), .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index f77ca0c9..d7f8ccdc 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -49,8 +49,8 @@ module hptw ( input logic ITLBMissF, input logic DTLBMissM, input logic FlushW, - input logic InstrDAPageFaultF, - input logic DataDAPageFaultM, + input logic InstrUpdateDAF, + input logic DataUpdateDAM, output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry @@ -87,7 +87,7 @@ module hptw ( logic [`XLEN-1:0] TranslationVAdr; logic [`XLEN-1:0] NextPTE; logic UpdatePTE; - logic HPTWDAPageFault; + logic HPTWUpdateDA; logic [`PA_BITS-1:0] HPTWReadAdr; logic SelHPTWAdr; logic [`XLEN+1:0] HPTWAdrExt; @@ -167,14 +167,14 @@ module hptw ( // memory access. If there is the PTE needs to be updated seting Access // and possibly also Dirty. Dirty is set if the operation is a store/amo. // However any other fault should not cause the update. - assign HPTWDAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; + assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; assign HPTWRW[0] = (WalkerState == UPDATE_PTE); - assign UpdatePTE = (WalkerState == LEAF) & HPTWDAPageFault; + assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; end else begin // block: hptwwrites assign NextPTE = ReadDataM; assign HPTWAdr = HPTWReadAdr; - assign HPTWDAPageFault = '0; + assign HPTWUpdateDA = '0; assign UpdatePTE = '0; assign HPTWRW[0] = '0; end @@ -182,8 +182,8 @@ module hptw ( // Enable and select signals based on states assign StartWalk = (WalkerState == IDLE) & TLBMiss; assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD); - assign DTLBWriteM = (WalkerState == LEAF & ~HPTWDAPageFault) & DTLBWalk; - assign ITLBWriteF = (WalkerState == LEAF & ~HPTWDAPageFault) & ~DTLBWalk; + assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk; + assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk; // FSM to track PageType based on the levels of the page table traversed flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType); @@ -262,7 +262,7 @@ module hptw ( else NextWalkerState = LEAF; L0_RD: if (DCacheStallM) NextWalkerState = L0_RD; else NextWalkerState = LEAF; - LEAF: if (`SVADU_SUPPORTED & HPTWDAPageFault) NextWalkerState = UPDATE_PTE; + LEAF: if (`SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE; else NextWalkerState = LEAF; @@ -273,8 +273,8 @@ module hptw ( assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss); - assign ITLBMissOrDAFaultF = ITLBMissF | (`SVADU_SUPPORTED & InstrDAPageFaultF); - assign DTLBMissOrDAFaultM = DTLBMissM | (`SVADU_SUPPORTED & DataDAPageFaultM); + assign ITLBMissOrDAFaultF = ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF); + assign DTLBMissOrDAFaultM = DTLBMissM | (`SVADU_SUPPORTED & DataUpdateDAM); // HTPW address/data/control muxing diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 0193a547..728b6b80 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -51,7 +51,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( // Faults output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources - output logic DAPageFault, // page fault due to setting dirty or access bit + output logic UpdateDA, // page fault due to setting dirty or access bit output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources // PMA checker signals input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type @@ -84,7 +84,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .PTE, .PageTypeWriteVal, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, - .Translate, .TLBPageFault, .DAPageFault); + .Translate, .TLBPageFault, .UpdateDA); end else begin:tlb// just pass address through as physical assign Translate = 0; assign TLBMiss = 0; diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index f8bf0d17..7d6cd317 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -72,7 +72,7 @@ module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) ( output logic TLBHit, output logic Translate, output logic TLBPageFault, - output logic DAPageFault + output logic UpdateDA ); logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex @@ -105,7 +105,7 @@ module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) ( tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, - .DAPageFault, .SV39Mode, .Translate); + .UpdateDA, .SV39Mode, .Translate); tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables); tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 45c56f1b..9754124d 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -43,7 +43,7 @@ module tlbcontrol #(parameter ITLB = 0) ( output logic TLBMiss, output logic TLBHit, output logic TLBPageFault, - output logic DAPageFault, + output logic UpdateDA, output logic SV39Mode, output logic Translate ); @@ -77,12 +77,12 @@ module tlbcontrol #(parameter ITLB = 0) ( assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | ((EffectivePrivilegeMode == `S_MODE) & PTE_U); if(`SVADU_SUPPORTED) begin : hptwwrites - assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V)); + assign UpdateDA = Translate & TLBHit & ~PTE_A & ~TLBPageFault; + assign TLBPageFault = Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V); end else begin // fault for software handling if access bit is off - assign DAPageFault = ~PTE_A; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequal | Misaligned | ~PTE_V)); + assign UpdateDA = ~PTE_A; + assign TLBPageFault = Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpdateDA | UpperBitsUnequal | Misaligned | ~PTE_V); end end else begin:dtlb // Data TLB fault checking logic InvalidRead, InvalidWrite; @@ -99,12 +99,12 @@ module tlbcontrol #(parameter ITLB = 0) ( // low. assign InvalidWrite = WriteAccess & ~PTE_W; if(`SVADU_SUPPORTED) begin : hptwwrites - assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; + assign UpdateDA = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V)); end else begin // Fault for software handling if access bit is off or writing a page with dirty bit off - assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D; - assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequal | Misaligned | ~PTE_V)); + assign UpdateDA = ~PTE_A | WriteAccess & ~PTE_D; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpdateDA | UpperBitsUnequal | Misaligned | ~PTE_V)); end end diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 02074f97..f9498634 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -156,7 +156,7 @@ module wallypipelinedcore ( logic ICacheMiss; logic ICacheAccess; logic BreakpointFaultM, EcallFaultM; - logic InstrDAPageFaultF; + logic InstrUpdateDAF; logic BigEndianM; logic FCvtIntE; logic CommittedF; @@ -184,7 +184,7 @@ module wallypipelinedcore ( .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF, // pmp/pma (inside mmu) signals. - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF); // integer execution unit: integer register file, datapath and controller ieu ieu(.clk, .reset, @@ -238,7 +238,7 @@ module wallypipelinedcore ( .HPTWInstrAccessFaultM, // connects to privilege .StoreAmoMisalignedFaultM, // connects to privilege .StoreAmoAccessFaultM, // connects to privilege - .InstrDAPageFaultF, + .InstrUpdateDAF, .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); From d3f5708ded113d79927664c334866d3fdc26f0f2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 18:35:10 -0800 Subject: [PATCH 5/8] StoreAmo faults are generated instead of load faults on AMO operations --- src/mmu/mmu.sv | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 728b6b80..e3cd8031 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -70,6 +70,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( logic Translate; // Translation occurs when virtual memory is active and DisableTranslation is off logic TLBHit; // Hit in TLB logic TLBPageFault; // Page fault from TLB + logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults // only instantiate TLB if Virtual Memory is supported if (`VIRTMEM_SUPPORTED) begin:tlb @@ -118,6 +119,8 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( assign PMPLoadAccessFaultM = 0; end + assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault + // Access faults // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss; @@ -132,11 +135,11 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( 2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu 2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd endcase - assign LoadMisalignedFaultM = DataMisalignedM & ReadAccessM; - assign StoreAmoMisalignedFaultM = DataMisalignedM & (WriteAccessM | AtomicAccessM); + assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM; + assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM; // Specify which type of page fault is occurring assign InstrPageFaultF = TLBPageFault & ExecuteAccessF; - assign LoadPageFaultM = TLBPageFault & ReadAccessM; - assign StoreAmoPageFaultM = TLBPageFault & (WriteAccessM | AtomicAccessM); + assign LoadPageFaultM = TLBPageFault & ReadNoAmoAccessM; + assign StoreAmoPageFaultM = TLBPageFault & WriteAccessM; endmodule From 907fbfec382a3b8c5b3882b27a13de80b3e68203 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 18:50:37 -0800 Subject: [PATCH 6/8] Simplified Access fault logic in HPTW --- src/mmu/hptw.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index d7f8ccdc..248bceeb 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -93,15 +93,17 @@ module hptw ( logic [`XLEN+1:0] HPTWAdrExt; logic ITLBMissOrDAFaultF; logic DTLBMissOrDAFaultM; + logic LSUAccessFaultM; logic [`PA_BITS-1:0] HPTWAdr; logic [1:0] HPTWRW; logic [2:0] HPTWSize; // 32 or 64 bit access statetype WalkerState, NextWalkerState, InitialWalkerState; // map hptw access faults onto either the original LSU load/store fault or instruction access fault - assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0]; - assign StoreAmoAccessFaultM = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[0]; - assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: (LSUStoreAmoAccessFaultM | LSULoadAccessFaultM) & ~DTLBWalk; + assign LSUAccessFault = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; + assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; + assign StoreAmoAccessFaultM = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : LSUAccessFaultM & DTLBWalk & MemRWM[0]; + assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: LSUAccessFaultM & ~DTLBWalk; // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; From 0d3d499940bcf772cfc2abcfd0f19f60bd44b8f5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 19:38:34 -0800 Subject: [PATCH 7/8] hptw typo fix --- src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 248bceeb..f2df8ea9 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -100,7 +100,7 @@ module hptw ( statetype WalkerState, NextWalkerState, InitialWalkerState; // map hptw access faults onto either the original LSU load/store fault or instruction access fault - assign LSUAccessFault = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; + assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; assign StoreAmoAccessFaultM = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : LSUAccessFaultM & DTLBWalk & MemRWM[0]; assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: LSUAccessFaultM & ~DTLBWalk; From 5c8fee127bf8f608e5d672604772a3f66c8b3dfc Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 27 Feb 2023 07:29:53 -0800 Subject: [PATCH 8/8] Added support for ZMMUL --- config/buildroot/wally-config.vh | 1 + config/fpga/wally-config.vh | 1 + config/rv32e/wally-config.vh | 1 + config/rv32gc/wally-config.vh | 1 + config/rv32i/wally-config.vh | 1 + config/rv32imc/wally-config.vh | 1 + config/rv64fpquad/wally-config.vh | 1 + config/rv64gc/wally-config.vh | 1 + config/rv64i/wally-config.vh | 1 + src/ieu/controller.sv | 4 +- src/mdu/mdu.sv | 6 ++- src/wally/wallypipelinedcore.sv | 2 +- testbench/common/riscvassertions.sv | 60 +++++++++++++++-------------- 13 files changed, 47 insertions(+), 34 deletions(-) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index fbb5799d..3a68571d 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -136,6 +136,7 @@ `define SVADU_SUPPORTED 1 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index 03bc3f75..1f7447f4 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -145,6 +145,7 @@ `define SVADU_SUPPORTED 1 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh index b000b791..aee0e541 100644 --- a/config/rv32e/wally-config.vh +++ b/config/rv32e/wally-config.vh @@ -139,6 +139,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index d1571067..ac68e3ee 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -138,6 +138,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index 0f2e91c9..d75d0c46 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -139,6 +139,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh index f6b29895..42442d46 100644 --- a/config/rv32imc/wally-config.vh +++ b/config/rv32imc/wally-config.vh @@ -138,6 +138,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh index 3e4b9160..34d7628e 100644 --- a/config/rv64fpquad/wally-config.vh +++ b/config/rv64fpquad/wally-config.vh @@ -141,6 +141,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index f0dad93b..4e2ab3df 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -141,6 +141,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index f485c667..34c37f73 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -141,6 +141,7 @@ `define BTB_SIZE 10 `define SVADU_SUPPORTED 0 +`define ZMMUL_SUPPORTED 0 // FPU division architecture `define RADIX 32'h4 diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0b1852cb..51284704 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -150,14 +150,14 @@ module controller( ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type - else if (Funct7D == 7'b0000001 & `M_SUPPORTED) + else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2]))) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i - else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) + else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 4a85bf47..b62add60 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -51,16 +51,18 @@ module mdu( // Divider // Start a divide when a new division instruction is received and the divider isn't already busy or finishing // When IDIV_ON_FPU is set, use the FPU divider instead - if (`IDIV_ON_FPU) begin + // In ZMMUL, with M_SUPPORTED = 0, omit the divider + if ((`IDIV_ON_FPU) || (!`M_SUPPORTED)) begin:nodiv assign QuotM = 0; assign RemM = 0; assign DivBusyE = 0; - end else begin + end else begin:div intdivrestoring div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM); end // Result multiplexer + // For ZMMUL, QuotM and RemM are tied to 0, so the mux automatically simplifies always_comb case (Funct3M) 3'b000: PrelimResultM = ProdM[`XLEN-1:0]; // mul diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index f9498634..d5458ed7 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -313,7 +313,7 @@ module wallypipelinedcore ( end // multiply/divide unit - if (`M_SUPPORTED) begin:mdu + if (`M_SUPPORTED | `ZMMUL_SUPPORTED) begin:mdu mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E, diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index f6cb4c6f..f733aac5 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -23,40 +23,42 @@ module riscvassertions; initial begin - assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); - assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); - assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); - assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); - assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + $display("IDIV_ON_FPU = %b M_SUPPORTED %b comb %b\n", `IDIV_ON_FPU, `M_SUPPORTED, ((`IDIV_ON_FPU) || (!`M_SUPPORTED))); + assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); + assert (`S_SUPPORTED || `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); + assert (`IDIV_BITSPERCYCLE == 1 || `IDIV_BITSPERCYCLE==2 || `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); + assert (`D_SUPPORTED || ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); + assert (`F_SUPPORTED || ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); + assert (`DCACHE_SUPPORTED || ~`F_SUPPORTED || `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`FLEN<=`XLEN || `DCACHE_SUPPORTED || `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 || (!`DCACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 || (!`ICACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); - assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); + assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); + assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); + assert (`VIRTMEM_SUPPORTED == 0 || (`DTIM_SUPPORTED == 0 && `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); + assert (`DCACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`ICACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert ((`DCACHE_SUPPORTED == 0 && `ICACHE_SUPPORTED == 0) || `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); - assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - assert (`SSTC_SUPPORTED == 0 | (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); + assert (`DCACHE_SUPPORTED || (`A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); + assert (`IDIV_ON_FPU == 0 || `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); + assert (`SSTC_SUPPORTED == 0 || (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); + assert ((`ZMMUL_SUPPORTED == 0) || (`M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); end endmodule