From 44023e7ee7d6570c38aa614129f261b112b672a6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 12 Apr 2023 03:34:01 -0700 Subject: [PATCH] Removed unnecessary start term from initialization muxes to simplify and improve coverage --- src/fpu/fdivsqrt/fdivsqrtiter.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index d1cf2435..7de120ed 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -79,8 +79,8 @@ module fdivsqrtiter( assign initUM = {~SqrtE, {(`DIVb){1'b0}}}; mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux); mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux); - flopen #(`DIVb+1) UReg(clk, IFDivStartE|FDivBusyE, UMux, U[0]); - flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]); + flopen #(`DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]); + flopen #(`DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]); // C register/initialization mux // Initialize C to -1 for sqrt and -R for division @@ -93,7 +93,7 @@ module fdivsqrtiter( assign initC = {initCUpper, {`DIVb{1'b0}}}; mux2 #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); - flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]); + flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]); // Divisior register flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);