diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index c516fcf6..65129656 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -19,18 +19,20 @@ if {$tech == "sky130"} {
     lappend search_path $s9lib
 } elseif {$tech == "tsmc28"} {
     set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
+    set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
     set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
 } elseif {$tech == "tsmc28psyn"} {
-    set TLU /home/jstine/TLU+
+    set TLU /import/yukari1/pdk/TSMC/TLU+
     set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
+    set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/    
     set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
     set TLUPLUS true
     set mw_logic1_net VDD
     set mw_logic0_net VSS
     set CAPTABLE $TLU/1p8m/
-    set MW_REFERENCE_LIBRARY /home/jstine/MW
+    set MW_REFERENCE_LIBRARY /import/yukari1/pdk/TSMC/MW
     set MW_TECH_FILE tcbn28hpcplusbwp30p140
     set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus
     set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
@@ -56,9 +58,6 @@ if {$tech == "sky130"} {
     lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140    
 }
 
-# Set Link Library
-set link_library "$target_library $synthetic_library"
-
 # Set up DesignWare cache read and write directories to speed up compile.
 set cache_write  ~
 set cache_read   $cache_write
@@ -67,15 +66,19 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-if {$tech == "tsmc28" || $tech == "tsmc28psyn"} {
+if {($tech == "tsmc28psyn") || ($tech == "tsmc28psyn")} {
     set memory /home/jstine/WallyMem/rv64gc/
-    lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
+    set osumemory /import/yukari1/pdk/TSMC/WallyMem/rv64gc/    
     lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
     lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
     lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
     lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
+
 }
 
+# Set Link Library
+set link_library "$target_library $synthetic_library"
+
 # Set up User Information
 set company "Oklahoma State University"
 set user    "James E. Stine"