diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index a8ba7856..ed8cf606 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -142,7 +142,7 @@ module cachefsm
 
   // com back to CPU
   assign CacheCommitted = CurrState != STATE_READY;
-  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | 
+  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss) & ~FlushStage) | 
                       (CurrState == STATE_FETCH) |
                       (CurrState == STATE_WRITEBACK) |
                       (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv
index 7d3d2bee..79d22b63 100644
--- a/pipelined/src/ebu/buscachefsm.sv
+++ b/pipelined/src/ebu/buscachefsm.sv
@@ -128,7 +128,7 @@ module buscachefsm #(parameter integer   BeatCountThreshold,
   assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY);
   assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
 
-  assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
+  assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW) & ~Flush) |
 					//(CurrState == DATA_PHASE & ~BusRW[0]) |  // replace the next line with this.  Fails uart test but i think it's a test problem not a hardware problem.
 					(CurrState == DATA_PHASE) | 
                     (CurrState == CACHE_FETCH & ~HREADY) |
diff --git a/pipelined/src/ifu/.ifu.sv.swp b/pipelined/src/ifu/.ifu.sv.swp
deleted file mode 100644
index 5d26e0c7..00000000
Binary files a/pipelined/src/ifu/.ifu.sv.swp and /dev/null differ
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 1597fb98..071dca55 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -131,7 +131,7 @@ module ifu (
 
   if(`C_SUPPORTED) begin : SpillSupport
 
-    spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF),
+    spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM | BPPredWrongE), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF),
       .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
       .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpillSupport
@@ -222,7 +222,7 @@ module ifu (
       cache #(.LINELEN(`ICACHE_LINELENINBITS),
               .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
               .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
-      icache(.clk, .reset, .FlushStage(TrapM), .Stall(GatedStallD),
+      icache(.clk, .reset, .FlushStage(TrapM | BPPredWrongE), .Stall(GatedStallD),
              .FetchBuffer, .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
              .CacheBusRW,
@@ -239,7 +239,7 @@ module ifu (
       ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) 
       ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
             .HRDATA,
-            .Flush(TrapM), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
+            .Flush(TrapM | BPPredWrongE), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
             .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
             .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
              .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv
index 55de81f4..7049fac9 100644
--- a/pipelined/src/ifu/spillsupport.sv
+++ b/pipelined/src/ifu/spillsupport.sv
@@ -84,7 +84,7 @@ module spillsupport #(parameter CACHE_ENABLED)
   end
 
   assign SelSpillF = (CurrState == STATE_SPILL);
-  assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) |
+  assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF & ~Flush) |
                          (CurrState == STATE_SPILL & IFUCacheBusStallF);
   assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
   assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16];