From 41010aa4183cbc9673d70d5110977abe8fb1afb2 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 19 Oct 2021 12:09:43 -0500 Subject: [PATCH] Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this --- wally-pipelined/src/muldiv/mult_cs.sv | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/muldiv/mult_cs.sv b/wally-pipelined/src/muldiv/mult_cs.sv index 07d03420..f297401c 100644 --- a/wally-pipelined/src/muldiv/mult_cs.sv +++ b/wally-pipelined/src/muldiv/mult_cs.sv @@ -30,7 +30,8 @@ module mult_cs #(parameter WIDTH = 8) input logic [WIDTH-1:0] b; input logic tc; - output logic [2*WIDTH-1:0] sum, carry; + output logic [2*WIDTH-1:0] sum; + output logic [2*WIDTH-1:0] carry; // PP array logic [2*WIDTH-1:0] pp_array [0:WIDTH-1]; @@ -38,18 +39,18 @@ module mult_cs #(parameter WIDTH = 8) logic [2*WIDTH-1:0] tmp_sum, tmp_carry; logic [2*WIDTH-1:0] temp_pp; logic [2*WIDTH-1:0] tmp_pp_carry; - logic [WIDTH-1:0] temp_b_padded; + logic [WIDTH-1:0] temp_b; logic temp_bitgroup; integer bit_pair, height, i; always_comb begin - // For each multiplicand + // For each multiplicand PP generation for (bit_pair=0; bit_pair < WIDTH; bit_pair=bit_pair+1) begin // Shift to the right via P&H - temp_b_padded = (b >> (bit_pair)); - temp_bitgroup = temp_b_padded[0]; + temp_b = (b >> (bit_pair)); + temp_bitgroup = temp_b[0]; // PP generation case (temp_bitgroup) 1'b0 : temp_pp = {2*WIDTH-1{1'b0}}; @@ -64,7 +65,7 @@ module mult_cs #(parameter WIDTH = 8) // Height is multiplier height = WIDTH; - // Wallace Tree Reduction + // Wallace Tree PP reduction while (height > 2) begin for (i=0; i < (height/3); i=i+1)