From 40c0e67930c0371e33c16bfbca8331722b043d41 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 18 Jan 2023 18:05:11 -0600
Subject: [PATCH] Formatting.

---
 pipelined/src/lsu/atomic.sv | 34 +++++++++++++++++++---------------
 pipelined/src/lsu/lsu.sv    |  2 +-
 2 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv
index 64c1dc4b..69591928 100644
--- a/pipelined/src/lsu/atomic.sv
+++ b/pipelined/src/lsu/atomic.sv
@@ -1,10 +1,13 @@
 ///////////////////////////////////////////
 // atomic.sv
 //
-// Written: Ross Thompson ross1728@gmail.com January 31, 2022
-// Modified:
+// Written: Ross Thompson ross1728@gmail.com
+// Created: 31 January 2022
+// Modified: 18 January 2023
 //
-// Purpose: atomic data path.
+// Purpose: Wrapper for amoalu and lrsc
+//
+// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -28,18 +31,19 @@
 
 module atomic (
   input logic                clk,
-  input logic                reset, StallW,
-  input logic [`XLEN-1:0]    ReadDataM,
-  input logic [`XLEN-1:0]    IHWriteDataM, 
-  input logic [`PA_BITS-1:0] PAdrM,
-  input logic [6:0]          LSUFunct7M,
-  input logic [2:0]          LSUFunct3M,
-  input logic [1:0]          LSUAtomicM,
-  input logic [1:0]          PreLSURWM,
-  input logic                IgnoreRequest,
-  output logic [`XLEN-1:0]   IMAWriteDataM,
-  output logic               SquashSCW,
-  output logic [1:0]         LSURWM
+  input logic                reset, 
+  input logic                StallW,
+  input logic [`XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [`XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [`PA_BITS-1:0] PAdrM,          // Physical memory address
+  input logic [6:0]          LSUFunct7M,     // AMO alu operation gated by HPTW
+  input logic [2:0]          LSUFunct3M,     // IEU or HPTW memory operation size
+  input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation
+  input logic [1:0]          PreLSURWM,      // IEU or HPTW Read/Write signal
+  input logic                IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
+  output logic [`XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
+  output logic               SquashSCW,      // Store conditional failed disable write to GPR
+  output logic [1:0]         LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
 );
 
   logic [`XLEN-1:0]          AMOResult;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 95f058c3..b0998510 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -131,7 +131,7 @@ module lsu (
   logic                     LSULoadAccessFaultM;                     // Load acces fault
   logic 					LSUStoreAmoAccessFaultM;                 // Store access fault
   logic                     IgnoreRequestTLB;                        // On either ITLB or DTLB miss, ignore miss so HPTW can handle
-  logic 					IgnoreRequest;                           // On FlushM, ignore TLB miss
+  logic 					IgnoreRequest;                           // On FlushM or TLB miss ignore memory operation
   logic                     SelDTIM;                                 // Select DTIM rather than bus or D$