diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do
index 51046eb7..32ca64ee 100644
--- a/pipelined/regression/fpga-wave.do
+++ b/pipelined/regression/fpga-wave.do
@@ -508,8 +508,17 @@ add wave -noupdate /testbench/dut/SDCCLK
 add wave -noupdate -color Gold -label {cmd fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
 add wave -noupdate -color Gold -label {dat fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
 add wave -noupdate -color Gold -label {clk fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/i_CLK
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/o_CLK
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/i_RST
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_TIMER_OUT
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/TIMER_OUT_GT_ZERO
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/clkdivider/i_COUNT_IN_MAX
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/clkdivider/i_CLK
+add wave -noupdate /testbench/dut/uncore/sdc/SDC/clkdivider/o_CLK
+add wave -noupdate -radix decimal /testbench/dut/uncore/sdc/SDC/clkdivider/i_COUNT_IN_MAX
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 5} {2125334 ns} 0}
+WaveRestoreCursors {{Cursor 5} {3081 ns} 0} {{Cursor 2} {3101 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 177
@@ -525,4 +534,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {2124499 ns} {2128105 ns}
+WaveRestoreZoom {3039 ns} {3123 ns}
diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv
index f3db14eb..c1fac8dd 100644
--- a/pipelined/src/uncore/sdc/SDC.sv
+++ b/pipelined/src/uncore/sdc/SDC.sv
@@ -30,7 +30,7 @@
 
 `include "wally-config.vh"
 
-`define SDCCLKDIV -8'd2
+`define SDCCLKDIV -8'd3
 
 module SDC 
   (input  logic             HCLK, 
@@ -330,15 +330,14 @@ module SDC
 			.ECLK(CLKGate));
 
 
-/* -----\/----- EXCLUDED -----\/-----
   clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
-			     .i_EN(CLKDiv != 'b1),
+//			     .i_EN(CLKDiv != 'b1),
+			     .i_EN('1),							 
 			     .i_CLK(CLKGate),
 			     .i_RST(~HRESETn | CLKDivUpdateEn),
 			     .o_CLK(SDCCLKIn));
- -----/\----- EXCLUDED -----/\----- */
 
-  assign SDCCLKIn = CLKGate;
+//  assign SDCCLKIn = CLKGate;
   
 
   sd_top sd_top(.CLK(SDCCLKIn),
@@ -359,7 +358,7 @@ module SDC
 		.o_ERROR_CODE_Q(ErrorCode),
 		.o_FATAL_ERROR(FatalError),
 		.i_COUNT_IN_MAX(-8'd62),
-		.LIMIT_SD_TIMERS(1'b0)); // *** must change this to 0 for real hardware.
+		.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware.
 
   
 endmodule
diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv
index b7cd2fc6..da068d60 100644
--- a/pipelined/src/uncore/sdc/clkdivider.sv
+++ b/pipelined/src/uncore/sdc/clkdivider.sv
@@ -52,6 +52,7 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
   logic 			   w_load;
 
   logic 			   resetD, resetDD, resetPulse;
+  logic 			   rstdd2, rstddn;
 
   assign  w_load = resetPulse | w_counter_overflowed;  // reload when zero occurs or when set by outside
 
@@ -82,7 +83,15 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
     .q(resetDD),
     .clk(i_CLK));
   
-  assign resetPulse = i_RST & ~resetDD;
+  //assign resetPulse = i_RST & ~resetDD;
+  assign resetPulse = ~i_RST & resetDD;
+
+  assign rstdd2 = i_RST | resetDD;
+  
+  flop #(1) fallingEdge
+	(.d(rstdd2),
+	 .q(rstddn),
+	 .clk(~i_CLK));
   
   flopenr #(1) toggle_flip_flop
     (.d(w_fd_D),
@@ -93,6 +102,11 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
 
   assign w_fd_D = ~ r_fd_Q;
 
+/* -----\/----- EXCLUDED -----\/-----
   if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN), .O(o_CLK)); 
   else  assign o_CLK = i_EN ? r_fd_Q : i_CLK;
+ -----/\----- EXCLUDED -----/\----- */
+
+  if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN & ~rstddn), .O(o_CLK)); 
+  else  assign o_CLK = i_EN & ~rstddn ? r_fd_Q : i_CLK;
 endmodule