From 26e8b85111a57e677b52bae6785ee6ed979b4832 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 1 Feb 2023 21:31:25 -0800 Subject: [PATCH 001/183] added beginning of a ZBS instruction module to the ALU. Control signals still needed --- pipelined/src/ieu/alu.sv | 5 ++++ pipelined/src/ieu/zbs.sv | 58 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 pipelined/src/ieu/zbs.sv diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index ccd55779..e7f7786a 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -32,6 +32,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [6:0] Funct7, input logic [2:0] Funct3, // With ALUControl, indicates operation to perform output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -83,6 +84,10 @@ module alu #(parameter WIDTH=32) ( 3'b111: FullResult = A & B; // and endcase + if (`ZBS_SUPPORTED) + zbs zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); + else assign ZBSResult = 0; + // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign Result = FullResult; diff --git a/pipelined/src/ieu/zbs.sv b/pipelined/src/ieu/zbs.sv new file mode 100644 index 00000000..021594ac --- /dev/null +++ b/pipelined/src/ieu/zbs.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// zbs.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 31 January 2023 +// Modified: +// +// Purpose: RISC-V single bit manipulation unit (ZBS instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module zbs #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [6:0] Funct7, + input logic [2:0] Funct3, // With ***Control, indicates operation to perform + output logic [WIDTH-1:0] ZBSResult); // ZBS result + //output logic [WIDTH-1:0] Sum); // Sum of operands + + logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; + + decoder #(clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); + + assign InvResult = A ^ BMask; + assign ClrResult = A & ~BMask; + assign SetResult = A | BMask; + assign ExtResult = |(A & BMask); + + casez ({Funct7, Funct3}) + 10'b010010?_001: ZBSResult = ClrResult; + 10'b010010?_101: ZBSResult = ExtResult; + 10'b011010?_001: ZBSResult = ClrResult; + 10'b001010?_001: ZBSResult = ClrResult; + default: ZBSResult = 0; // *** should never be reached or selected + endcase + +endmodule + From bdd12bfec6af06262e454e4558bb0d735c23562f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 16:40:58 +0000 Subject: [PATCH 002/183] started clmul --- pipelined/src/ieu/clmul.sv | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 pipelined/src/ieu/clmul.sv diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv new file mode 100644 index 00000000..e69de29b From 655f5bbc5e166559cd0ae08f04c3cc712b1163fa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 18:54:33 +0000 Subject: [PATCH 003/183] continued clmul unit --- pipelined/src/ieu/clmul.sv | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index e69de29b..2fba79f0 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// clmul.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 1 February 2023 +// Modified: +// +// Purpose: RISC-V single bit manipulation unit (ZBS instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module clmul #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] Result); // ZBS result + //output logic [WIDTH-1:0] Sum); // Sum of operands + + logic [WIDTH-1] pp [WIDTH-1]; //partial AND products + logic [WIDTH-1] sop; //sum of partial products + genvar i; + for (i=0; i Date: Thu, 2 Feb 2023 19:49:14 +0000 Subject: [PATCH 004/183] clmul finished initial hdl; passes lint --- pipelined/src/ieu/clmul.sv | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index 2fba79f0..bd2615a9 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -32,21 +32,23 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] Result); // ZBS result - //output logic [WIDTH-1:0] Sum); // Sum of operands - logic [WIDTH-1] pp [WIDTH-1]; //partial AND products - logic [WIDTH-1] sop; //sum of partial products - genvar i; - for (i=0; i Date: Thu, 2 Feb 2023 20:04:38 +0000 Subject: [PATCH 005/183] zbs passes lint --- pipelined/src/ieu/zbs.sv | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ieu/zbs.sv b/pipelined/src/ieu/zbs.sv index 021594ac..3d764c0f 100644 --- a/pipelined/src/ieu/zbs.sv +++ b/pipelined/src/ieu/zbs.sv @@ -35,7 +35,6 @@ module zbs #(parameter WIDTH=32) ( input logic [6:0] Funct7, input logic [2:0] Funct3, // With ***Control, indicates operation to perform output logic [WIDTH-1:0] ZBSResult); // ZBS result - //output logic [WIDTH-1:0] Sum); // Sum of operands logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; @@ -46,13 +45,15 @@ module zbs #(parameter WIDTH=32) ( assign SetResult = A | BMask; assign ExtResult = |(A & BMask); - casez ({Funct7, Funct3}) - 10'b010010?_001: ZBSResult = ClrResult; - 10'b010010?_101: ZBSResult = ExtResult; - 10'b011010?_001: ZBSResult = ClrResult; - 10'b001010?_001: ZBSResult = ClrResult; - default: ZBSResult = 0; // *** should never be reached or selected - endcase + always_comb begin + casez ({Funct7, Funct3}) + 10'b010010?_001: ZBSResult = ClrResult; + 10'b010010?_101: ZBSResult = ExtResult; + 10'b011010?_001: ZBSResult = InvResult; + 10'b001010?_001: ZBSResult = SetResult; + default: ZBSResult = 0; // *** should never be reached or selected + endcase + end endmodule From 1b6aca189df0a9749d6ea70524970d3cc9386ecd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 20:11:11 +0000 Subject: [PATCH 006/183] started zbc --- pipelined/src/ieu/clmul.sv | 2 +- pipelined/src/ieu/zbc.sv | 41 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 pipelined/src/ieu/zbc.sv diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index bd2615a9..4fa8dda5 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -5,7 +5,7 @@ // Created: 1 February 2023 // Modified: // -// Purpose: RISC-V single bit manipulation unit (ZBS instructions) +// Purpose: Carry-Less multiplication top-level unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/pipelined/src/ieu/zbc.sv b/pipelined/src/ieu/zbc.sv new file mode 100644 index 00000000..14cc2b88 --- /dev/null +++ b/pipelined/src/ieu/zbc.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// zbc.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 2 February 2023 +// Modified: +// +// Purpose: RISC-V single bit manipulation unit (ZBC instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module zbs #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [6:0] Funct7, + input logic [2:0] Funct3, // With ***Control, indicates operation to perform + output logic [WIDTH-1:0] ZBCResult); // ZBC result + + + +endmodule \ No newline at end of file From 34eb33a5e7a6259c8946f616b466df9d3ce6bab9 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 23:10:57 +0000 Subject: [PATCH 007/183] added bit reverse module, passes lint --- pipelined/src/ieu/bitreverse.sv | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 pipelined/src/ieu/bitreverse.sv diff --git a/pipelined/src/ieu/bitreverse.sv b/pipelined/src/ieu/bitreverse.sv new file mode 100644 index 00000000..5d195d24 --- /dev/null +++ b/pipelined/src/ieu/bitreverse.sv @@ -0,0 +1,43 @@ + +/////////////////////////////////////////// +// bitreverse.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 1 February 2023 +// Modified: +// +// Purpose: Carry-Less multiplication top-level unit +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module bitreverse #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] b); + + genvar i; + for (i=0; i Date: Fri, 3 Feb 2023 04:48:23 +0000 Subject: [PATCH 008/183] zbc initial done; passes lint. clmul logic changes have not verified yet --- pipelined/src/ieu/clmul.sv | 11 ++++----- pipelined/src/ieu/zbc.sv | 47 ++++++++++++++++++++++++++++++++++---- 2 files changed, 47 insertions(+), 11 deletions(-) diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index 4fa8dda5..5557283f 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -31,23 +31,22 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands - output logic [WIDTH-1:0] Result); // ZBS result + output logic [WIDTH-1:0] ClmulResult); // ZBS result logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products - logic [WIDTH-1:0] sop; //sum of partial products genvar i,j; - for (i=1; i CLMUL -> MUX -> RESULT + //alternate could have CLMUL * 3 -> MUX -> MUX + always_comb begin + casez (Funct3) + 3'b001: begin //clmul + X = A; + Y = B; + end + 3'b011: begin //clmulh + X = {RevA[WIDTH-2:0], {1'b0}}; + Y = {{1'b0}, RevB[WIDTH-2:0]}; + end + 3'b010: begin //clmulr + X = {A[WIDTH-2:0], {1'b0}}; + Y = B; + end + default: begin + X = 0; + Y = 0; + end + endcase + + end + clmul clm(.A(X), .B(Y), .ClmulResult(ClmulResult)); + bitreverse brClmulResult(.a(ClmulResult), .b(RevClmulResult)); + + assign ZBCResult = (Funct3 == 3'b011) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From ea98fdd7e412349c69a333f59f56dde38e3bd1c4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Feb 2023 05:31:50 +0000 Subject: [PATCH 009/183] zbs minor lint fix --- pipelined/src/ieu/datapath.sv | 31 +------------------------------ pipelined/src/ieu/zbs.sv | 2 +- 2 files changed, 2 insertions(+), 31 deletions(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 60d43de9..e1202bb9 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -1,32 +1,3 @@ -/////////////////////////////////////////// -// datapath.sv -// -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu -// Created: 9 January 2021 -// Modified: -// -// Purpose: Wally Integer Datapath -// -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - `include "wally-config.vh" module datapath ( @@ -141,4 +112,4 @@ module datapath ( // handle Store Conditional result if atomic extension supported if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW}; else assign SCResultW = 0; -endmodule +endmodule \ No newline at end of file diff --git a/pipelined/src/ieu/zbs.sv b/pipelined/src/ieu/zbs.sv index 3d764c0f..ae3b751a 100644 --- a/pipelined/src/ieu/zbs.sv +++ b/pipelined/src/ieu/zbs.sv @@ -38,7 +38,7 @@ module zbs #(parameter WIDTH=32) ( logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; - decoder #(clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); assign InvResult = A ^ BMask; assign ClrResult = A & ~BMask; From dd4f8c0712dbd33a852366a81cb9d7d2b50481f3 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Feb 2023 05:40:38 +0000 Subject: [PATCH 010/183] Started Zbb -Performs byte instructions (orc.b, rev8 (32/64)) --- pipelined/src/ieu/zbb.sv | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 pipelined/src/ieu/zbb.sv diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv new file mode 100644 index 00000000..2a7ea302 --- /dev/null +++ b/pipelined/src/ieu/zbb.sv @@ -0,0 +1,59 @@ + +/////////////////////////////////////////// +// zbb.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 2 February 2023 +// Modified: +// +// Purpose: RISC-V miscellaneous bit manipulation unit (subset of ZBB instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module zbb #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] Funct3, // Indicates operation to perform + input logic [6:0] Funct7, // Indicates operation to perform + output logic [WIDTH-1:0] ZBBResult); // ZBC result + + logic [WIDTH-1:0] OrcBResult; + logic [WIDTH-1:0] Rev8Result; + + genvar i; + + for (i=0;i Date: Fri, 3 Feb 2023 16:00:32 +0000 Subject: [PATCH 011/183] ALU changes (ZBB) - handles inverted operand instructions - handles shift-and-add instructions --- pipelined/src/ieu/alu.sv | 61 +++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index e7f7786a..1d472268 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -37,22 +37,52 @@ module alu #(parameter WIDTH=32) ( output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands - // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. + // CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results + logic [WIDTH-1:0] ZBBResult, ZBSResult; + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B + logic InvB; // Is Inverted Operand Instruction (ZBB) // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + // Addition - assign CondInvB = SubArith ? ~B : B; - assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + if (`ZBB_SUPPORTED) + always_comb begin + case({Funct7, Funct3}) + 10'b0010000_010: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add + 10'b0010000_100: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add + 10'b0010000_110: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add + 10'b0000100_000: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 10'b0010000_010: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw + 10'b0010000_100: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw + 10'b0010000_110: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw + default: CondShiftA = A; + endcase + + case ({Funct7,Funct3}) + 10'b0100000_111: InvB = 1'b1; //andn + 10'b0100000_110: InvB = 1'b1; //orn + 10'b0100000_100: InvB = 1'b1; //xnor + default: InvB = 1'b0; + endcase + + end + else begin + assign CondShiftA = A; + assign InvB = 1'b0; + end + + assign CondInvB = (SubArith | InvB) ? ~B : B; + + assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); @@ -73,20 +103,25 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (Funct3) // Otherwise check Funct3 - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor - 3'b110: FullResult = A | B; // or - 3'b111: FullResult = A & B; // and + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (Funct3) // Otherwise check Funct3 + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ CondInvB; // xor + 3'b110: FullResult = A | CondInvB; // or + 3'b111: FullResult = A & CondInvB; // and endcase if (`ZBS_SUPPORTED) zbs zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); else assign ZBSResult = 0; + + + if (`ZBB_SUPPORTED) + zbb zbb(.A, .B, .Funct7, .Funct3, .ZBBResult); + else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; From 8c9107ffa4eb6dba8aaf18d58010d5298c6f443b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Feb 2023 17:40:02 +0000 Subject: [PATCH 012/183] arch32ba includes the 32i_m tests instead of 64 --- pipelined/testbench/tests.vh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 1d094254..2214d2a8 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -883,9 +883,9 @@ string imperas32f[] = '{ string arch32ba[] = '{ `RISCVARCHTEST, // *** unclear why add.uw isn't in the list - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh1add-02.S", - "rv64i_m/B/src/sh1add-013.S" + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh1add-02.S", + "rv32i_m/B/src/sh1add-013.S" }; string arch64m[] = '{ From 049f2e1e87f3b150ca124c4bd32144f95860d7bf Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Feb 2023 20:01:41 +0000 Subject: [PATCH 013/183] Started count instructions --- pipelined/src/ieu/zbb.sv | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 2a7ea302..62353067 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -34,8 +34,55 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] Funct3, // Indicates operation to perform input logic [6:0] Funct7, // Indicates operation to perform + input logic [6:0] W64, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBC result + + //count instructions + logic [WIDTH-1:0] czResult; + logic [WIDTH-1:0] clzResult; //leading zeros result + logic [WIDTH-1:0] ctzResult; //trailing zeros result + logic [WIDTH-1:0] clzA, clzB; + logic [WIDTH-1:0] clzwA, clzwB; + logic [WIDTH-1:0] ctzA, ctzB; + logic [WIDTH-1:0] ctzwA, ctzwB; + logic [WIDTH-1:0] clzResult, ctzResult; + + //in both rv64, rv32 + assign clzA = A; + bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); + + //only in rv64 + assign clzwA = {A[31:0],{32{1'b1}}}; + bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + + //NOTE: Can be simplified to a single lzc with a 4-select mux. + lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); + lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); + lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); + lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + + if (WIDTH==64) begin + assign clzResult = W64 ? clzwB : clzB; + assign ctzResult = W64 ? ctzwB : ctzB; + end + else begin + assign clzResult = clzB; + assign ctzResult = ctzB; + end + + + + + + + + + + + + + //byte instructions logic [WIDTH-1:0] OrcBResult; logic [WIDTH-1:0] Rev8Result; @@ -52,6 +99,11 @@ module zbb #(parameter WIDTH=32) ( 15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; + 15'b0110000_001_00000: ZBBResult = clzResult; + 15'b0110000_001_00010: //cpopResult goes here + 15'b0110000_001_00001: ZBBResult = ctzResult; + 15'b0110101_101_11000: ZBBResult = Rev8Result; + 15'b0110101_101_11000: ZBBResult = Rev8Result; endcase end From 5200ed3d2ea64c792c555a3d2b9dd3f5d6519336 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 00:11:12 +0000 Subject: [PATCH 014/183] added population count in generic modules --- pipelined/src/generic/popcnt.sv | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 pipelined/src/generic/popcnt.sv diff --git a/pipelined/src/generic/popcnt.sv b/pipelined/src/generic/popcnt.sv new file mode 100644 index 00000000..a5135dd1 --- /dev/null +++ b/pipelined/src/generic/popcnt.sv @@ -0,0 +1,40 @@ + +/////////////////////////////////////////// +// +// Written: Kevin Kim +// Modified: 2/4/2023 +// +// Purpose: Population Count +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module popcnt #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] num, // number to count total ones + output logic [$clog2(WIDTH):0] PopCnt // the total number of ones +); + + logic [$clog2(WIDTH):0] sum; + genvar i; + for (i=0;i Date: Sun, 5 Feb 2023 00:11:24 +0000 Subject: [PATCH 015/183] zbb handles popcnt and passes lint --- pipelined/src/ieu/zbb.sv | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 62353067..1c10cdcc 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -40,35 +40,52 @@ module zbb #(parameter WIDTH=32) ( //count instructions logic [WIDTH-1:0] czResult; - logic [WIDTH-1:0] clzResult; //leading zeros result - logic [WIDTH-1:0] ctzResult; //trailing zeros result + logic [WIDTH-1:0] clzResult; //leading zeros result + logic [WIDTH-1:0] ctzResult; //trailing zeros result + logic [WIDTH-1:0] cpopResult; //population count result logic [WIDTH-1:0] clzA, clzB; logic [WIDTH-1:0] clzwA, clzwB; logic [WIDTH-1:0] ctzA, ctzB; logic [WIDTH-1:0] ctzwA, ctzwB; - logic [WIDTH-1:0] clzResult, ctzResult; + logic [WIDTH-1:0] cpopwA, cpopA; + logic [WIDTH-1:0] cpopwB, cpopB; //in both rv64, rv32 assign clzA = A; bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); //only in rv64 - assign clzwA = {A[31:0],{32{1'b1}}}; - bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + if (WIDTH==64) begin + assign clzwA = {A[31:0],{32{1'b1}}}; + bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + assign cpopwA = {{32{1'b0}},A}; - //NOTE: Can be simplified to a single lzc with a 4-select mux. + end + else begin + assign clzwA = 32'b0; + assign ctzwA = 32'b0; + assign cpopwA = 32'b0; + end + + //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. + //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); + popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); + if (WIDTH==64) begin assign clzResult = W64 ? clzwB : clzB; assign ctzResult = W64 ? ctzwB : ctzB; + assign cpopResult = W64 ? cpopwB : cpopB; end else begin assign clzResult = clzB; assign ctzResult = ctzB; + assign cpopResult = cpopB; end @@ -100,7 +117,7 @@ module zbb #(parameter WIDTH=32) ( 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110000_001_00000: ZBBResult = clzResult; - 15'b0110000_001_00010: //cpopResult goes here + 15'b0110000_001_00010: ZBBResult = cpopResult; 15'b0110000_001_00001: ZBBResult = ctzResult; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From b40b1fab5280cd0a9ee4738899a4c28a7804c69d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 00:48:26 +0000 Subject: [PATCH 016/183] modularized count into cnt.sv; passes lint --- pipelined/src/ieu/cnt.sv | 84 ++++++++++++++++++++++++++++++++++++++++ pipelined/src/ieu/zbb.sv | 67 ++++---------------------------- 2 files changed, 91 insertions(+), 60 deletions(-) create mode 100644 pipelined/src/ieu/cnt.sv diff --git a/pipelined/src/ieu/cnt.sv b/pipelined/src/ieu/cnt.sv new file mode 100644 index 00000000..84a30fc5 --- /dev/null +++ b/pipelined/src/ieu/cnt.sv @@ -0,0 +1,84 @@ + +/////////////////////////////////////////// +// cnt.sv +// +// Written: Kevin Kim +// Created: 4 February 2023 +// Modified: +// +// Purpose: Count Instruction Submodule +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module cnt #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] A, // Operand + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] clzResult, // leading zeros result + output logic [WIDTH-1:0] ctzResult, // trailing zeros result + output logic [WIDTH-1:0] cpopResult);// population count result + //count instructions + logic [WIDTH-1:0] clzA, clzB; + logic [WIDTH-1:0] clzwA, clzwB; + logic [WIDTH-1:0] ctzA, ctzB; + logic [WIDTH-1:0] ctzwA, ctzwB; + logic [WIDTH-1:0] cpopwA, cpopA; + logic [WIDTH-1:0] cpopwB, cpopB; + + //in both rv64, rv32 + assign clzA = A; + bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); + + //only in rv64 + if (WIDTH==64) begin + assign clzwA = {A[31:0],{32{1'b1}}}; + bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + assign cpopwA = {{32{1'b0}},A}; + + end + else begin + assign clzwA = 32'b0; + assign ctzwA = 32'b0; + assign cpopwA = 32'b0; + end + + //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. + //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. + lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); + lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); + lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); + lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + + popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); + popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); + + if (WIDTH==64) begin + assign clzResult = W64 ? clzwB : clzB; + assign ctzResult = W64 ? ctzwB : ctzB; + assign cpopResult = W64 ? cpopwB : cpopB; + end + else begin + assign clzResult = clzB; + assign ctzResult = ctzB; + assign cpopResult = cpopB; + end +endmodule \ No newline at end of file diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 1c10cdcc..e3803e17 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -34,70 +34,17 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] Funct3, // Indicates operation to perform input logic [6:0] Funct7, // Indicates operation to perform - input logic [6:0] W64, // Indicates word operation - output logic [WIDTH-1:0] ZBBResult); // ZBC result - - - //count instructions - logic [WIDTH-1:0] czResult; - logic [WIDTH-1:0] clzResult; //leading zeros result - logic [WIDTH-1:0] ctzResult; //trailing zeros result - logic [WIDTH-1:0] cpopResult; //population count result - logic [WIDTH-1:0] clzA, clzB; - logic [WIDTH-1:0] clzwA, clzwB; - logic [WIDTH-1:0] ctzA, ctzB; - logic [WIDTH-1:0] ctzwA, ctzwB; - logic [WIDTH-1:0] cpopwA, cpopA; - logic [WIDTH-1:0] cpopwB, cpopB; - - //in both rv64, rv32 - assign clzA = A; - bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); - - //only in rv64 - if (WIDTH==64) begin - assign clzwA = {A[31:0],{32{1'b1}}}; - bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); - assign cpopwA = {{32{1'b0}},A}; - - end - else begin - assign clzwA = 32'b0; - assign ctzwA = 32'b0; - assign cpopwA = 32'b0; - end - - //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. - //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. - lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); - lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); - lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); - lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); - - popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); - popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); - - if (WIDTH==64) begin - assign clzResult = W64 ? clzwB : clzB; - assign ctzResult = W64 ? ctzwB : ctzB; - assign cpopResult = W64 ? cpopwB : cpopB; - end - else begin - assign clzResult = clzB; - assign ctzResult = ctzB; - assign cpopResult = cpopB; - end - - - - - - - + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] ZBBResult); // ZBB result + //count results + logic [WIDTH-1:0] clzResult; // leading zeros result + logic [WIDTH-1:0] ctzResult; // trailing zeros result + logic [WIDTH-1:0] cpopResult; // population count result + cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); //byte instructions logic [WIDTH-1:0] OrcBResult; From 25d9d5299495ded8f68523b339cd753ab61b789c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 01:04:39 +0000 Subject: [PATCH 017/183] modularized byte instruction handling into byte.sv; passes lint --- pipelined/src/ieu/byte.sv | 44 +++++++++++++++++++++++++++++++++++++++ pipelined/src/ieu/zbb.sv | 11 +++------- 2 files changed, 47 insertions(+), 8 deletions(-) create mode 100644 pipelined/src/ieu/byte.sv diff --git a/pipelined/src/ieu/byte.sv b/pipelined/src/ieu/byte.sv new file mode 100644 index 00000000..17ab652f --- /dev/null +++ b/pipelined/src/ieu/byte.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// clmul.sv +// +// Written: Kevin Kim +// Created: 1 February 2023 +// Modified: +// +// Purpose: Carry-Less multiplication top-level unit +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module byteUnit #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, // Operands + output logic [WIDTH-1:0] OrcBResult, // OrcB result + output logic [WIDTH-1:0] Rev8Result); // Rev8 result + + genvar i; + + for (i=0;i Date: Sun, 5 Feb 2023 16:37:32 +0000 Subject: [PATCH 018/183] began sign/zero extend --- pipelined/src/ieu/ext.sv | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 pipelined/src/ieu/ext.sv diff --git a/pipelined/src/ieu/ext.sv b/pipelined/src/ieu/ext.sv new file mode 100644 index 00000000..c546d2c4 --- /dev/null +++ b/pipelined/src/ieu/ext.sv @@ -0,0 +1,44 @@ + +/////////////////////////////////////////// +// cnt.sv +// +// Written: Kevin Kim +// Created: 4 February 2023 +// Modified: +// +// Purpose: Sign/Zero Extension Submodule +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ext #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] A, // Operand + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] sexthResult, // sign extend halfword result + output logic [WIDTH-1:0] sextbResult, // sign extend byte result + output logic [WIDTH-1:0] zexthResult); // zero extend halfword result + + assign sexthResult = {{(XLEN-16){A[15]}},A[15:0]}; + assign zexthResult = {{(XLEN-16){1'b0}},A[15:0]}; + assign sextbResult = {{(XLEN-8){A[7]}},A[7:0]}; + +endmodule \ No newline at end of file From 95c91e4661ea157e89e3b925cff24d081eda1b43 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 16:50:13 +0000 Subject: [PATCH 019/183] zbb handles sign --- pipelined/src/ieu/ext.sv | 7 +++---- pipelined/src/ieu/zbb.sv | 30 +++++++++++++++++++----------- 2 files changed, 22 insertions(+), 15 deletions(-) diff --git a/pipelined/src/ieu/ext.sv b/pipelined/src/ieu/ext.sv index c546d2c4..c9f845e7 100644 --- a/pipelined/src/ieu/ext.sv +++ b/pipelined/src/ieu/ext.sv @@ -32,13 +32,12 @@ module ext #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, // Operand - input logic W64, // Indicates word operation output logic [WIDTH-1:0] sexthResult, // sign extend halfword result output logic [WIDTH-1:0] sextbResult, // sign extend byte result output logic [WIDTH-1:0] zexthResult); // zero extend halfword result - assign sexthResult = {{(XLEN-16){A[15]}},A[15:0]}; - assign zexthResult = {{(XLEN-16){1'b0}},A[15:0]}; - assign sextbResult = {{(XLEN-8){A[7]}},A[7:0]}; + assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]}; + assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; + assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; endmodule \ No newline at end of file diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 860fd2c4..caaa1985 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -31,26 +31,31 @@ `include "wally-config.vh" module zbb #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform - input logic [6:0] Funct7, // Indicates operation to perform - input logic W64, // Indicates word operation - output logic [WIDTH-1:0] ZBBResult); // ZBB result + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] Funct3, // Indicates operation to perform + input logic [6:0] Funct7, // Indicates operation to perform + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] ZBBResult); // ZBB result - //count results - logic [WIDTH-1:0] clzResult; // leading zeros result - logic [WIDTH-1:0] ctzResult; // trailing zeros result - logic [WIDTH-1:0] cpopResult; // population count result + // count results + logic [WIDTH-1:0] clzResult; // leading zeros result + logic [WIDTH-1:0] ctzResult; // trailing zeros result + logic [WIDTH-1:0] cpopResult; // population count result - //byte results + // byte results logic [WIDTH-1:0] OrcBResult; logic [WIDTH-1:0] Rev8Result; - cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); + // sign/zero extend results + logic [WIDTH-1:0] sexthResult; // sign extend halfword result + logic [WIDTH-1:0] sextbResult; // sign extend byte result + logic [WIDTH-1:0] zexthResult; // zero extend halfword result + cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); byteUnit bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); + ext ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin @@ -63,6 +68,9 @@ module zbb #(parameter WIDTH=32) ( 15'b0110000_001_00001: ZBBResult = ctzResult; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; + 15'b0000100_100_00000: ZBBResult = zexthResult; + 15'b0110000_001_00100: ZBBResult = sextbResult; + 15'b0110000_001_00101: ZBBResult = sexthResult; endcase end From e24ee033554613d0e19c401781f5dcc42a17ec0a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Feb 2023 17:55:37 +0000 Subject: [PATCH 020/183] modified shifter to configure for Zbb and handle rotates - alu handles rotates --- pipelined/src/ieu/alu.sv | 13 +++++- pipelined/src/ieu/shifter.sv | 79 ++++++++++++++++++++++++++++++++---- 2 files changed, 82 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 1d472268..e10591c1 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -48,6 +48,7 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic InvB; // Is Inverted Operand Instruction (ZBB) + logic Rotate; // Is rotate operation // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -74,6 +75,16 @@ module alu #(parameter WIDTH=32) ( default: InvB = 1'b0; endcase + casez ({Funct7, Funct3}) + 10'b0110000_101: Rotate = 1'b1; + 10'b011000?_101: Rotate = 1'b1; + 10'b000010?_001: Rotate = 1'b0; + 10'b0110000_001: Rotate = 1'b1; + 10'b0110000_101: Rotate = 1'b1; + 10'b0110000_001: Rotate = 1'b1; + 10'b0110000_101: Rotate = 1'b1; + default: Rotate = 1'b0; + endcase end else begin assign CondShiftA = A; @@ -85,7 +96,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Rotate(Rotate), .Y(Shift)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv index 77e4dab3..15c7b411 100644 --- a/pipelined/src/ieu/shifter.sv +++ b/pipelined/src/ieu/shifter.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // shifter.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu // Created: 9 January 2021 -// Modified: +// Modified: 6 February 2023 // // Purpose: RISC-V 32/64 bit shifter // @@ -30,18 +30,18 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN-1:0] A, // Source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, // Shift right, arithmetic, RV64 W-type shift - output logic [`XLEN-1:0] Y); // Shifted result + input logic [`XLEN-1:0] A, // Source + input logic [`LOG_XLEN-1:0] Amt, // Shift amount + input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount // Handle left and right shifts with a funnel shifter. // For RV32, only 32-bit shifts are needed. // For RV64, 32- and 64-bit shifts are needed, with sign extension. - + /* // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux @@ -65,6 +65,67 @@ module shifter ( end assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end + */ + + if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) + else + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else + if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw + else + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else + if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Rotate) z = {A[62:0], A[63:0]}; //ror + else + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else + if (Rotate) z = {A[63:0], A[63:1]}; //rol + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotFunnel + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; From 95ff9e91c584b6d5a707dafb7f006487fe2adc40 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 8 Feb 2023 13:57:09 +0000 Subject: [PATCH 021/183] moved files into bmu folder --- src/ieu/{ => bmu}/bitreverse.sv | 0 src/ieu/{ => bmu}/byte.sv | 0 src/ieu/{ => bmu}/clmul.sv | 0 src/ieu/{ => bmu}/cnt.sv | 0 src/ieu/{ => bmu}/ext.sv | 0 src/{generic => ieu/bmu}/popcnt.sv | 0 src/ieu/{ => bmu}/zbb.sv | 0 src/ieu/{ => bmu}/zbc.sv | 0 src/ieu/{ => bmu}/zbs.sv | 0 9 files changed, 0 insertions(+), 0 deletions(-) rename src/ieu/{ => bmu}/bitreverse.sv (100%) rename src/ieu/{ => bmu}/byte.sv (100%) rename src/ieu/{ => bmu}/clmul.sv (100%) rename src/ieu/{ => bmu}/cnt.sv (100%) rename src/ieu/{ => bmu}/ext.sv (100%) rename src/{generic => ieu/bmu}/popcnt.sv (100%) rename src/ieu/{ => bmu}/zbb.sv (100%) rename src/ieu/{ => bmu}/zbc.sv (100%) rename src/ieu/{ => bmu}/zbs.sv (100%) diff --git a/src/ieu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv similarity index 100% rename from src/ieu/bitreverse.sv rename to src/ieu/bmu/bitreverse.sv diff --git a/src/ieu/byte.sv b/src/ieu/bmu/byte.sv similarity index 100% rename from src/ieu/byte.sv rename to src/ieu/bmu/byte.sv diff --git a/src/ieu/clmul.sv b/src/ieu/bmu/clmul.sv similarity index 100% rename from src/ieu/clmul.sv rename to src/ieu/bmu/clmul.sv diff --git a/src/ieu/cnt.sv b/src/ieu/bmu/cnt.sv similarity index 100% rename from src/ieu/cnt.sv rename to src/ieu/bmu/cnt.sv diff --git a/src/ieu/ext.sv b/src/ieu/bmu/ext.sv similarity index 100% rename from src/ieu/ext.sv rename to src/ieu/bmu/ext.sv diff --git a/src/generic/popcnt.sv b/src/ieu/bmu/popcnt.sv similarity index 100% rename from src/generic/popcnt.sv rename to src/ieu/bmu/popcnt.sv diff --git a/src/ieu/zbb.sv b/src/ieu/bmu/zbb.sv similarity index 100% rename from src/ieu/zbb.sv rename to src/ieu/bmu/zbb.sv diff --git a/src/ieu/zbc.sv b/src/ieu/bmu/zbc.sv similarity index 100% rename from src/ieu/zbc.sv rename to src/ieu/bmu/zbc.sv diff --git a/src/ieu/zbs.sv b/src/ieu/bmu/zbs.sv similarity index 100% rename from src/ieu/zbs.sv rename to src/ieu/bmu/zbs.sv From ce9dca8aecbd0490a48e40af236d638b98bef7c5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 16:45:22 +0000 Subject: [PATCH 022/183] modified cnt for zbb to mux inputs --- src/ieu/bmu/cnt.sv | 66 ++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 35 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 84a30fc5..b0c44e06 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -31,54 +31,50 @@ `include "wally-config.vh" module cnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, // Operand + input logic [WIDTH-1:0] A, B, // Operands input logic W64, // Indicates word operation - output logic [WIDTH-1:0] clzResult, // leading zeros result - output logic [WIDTH-1:0] ctzResult, // trailing zeros result + output logic [WIDTH-1:0] czResult, // count zeros result output logic [WIDTH-1:0] cpopResult);// population count result + //count instructions - logic [WIDTH-1:0] clzA, clzB; - logic [WIDTH-1:0] clzwA, clzwB; - logic [WIDTH-1:0] ctzA, ctzB; - logic [WIDTH-1:0] ctzwA, ctzwB; - logic [WIDTH-1:0] cpopwA, cpopA; - logic [WIDTH-1:0] cpopwB, cpopB; + logic [WIDTH-1:0] lzcA, popcntA; + logic [WIDTH-1:0] revA; //in both rv64, rv32 - assign clzA = A; - bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); + bitreverse #(WIDTH) brtz(.a(A), .b(revA)); //only in rv64 if (WIDTH==64) begin - assign clzwA = {A[31:0],{32{1'b1}}}; - bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); - assign cpopwA = {{32{1'b0}},A}; + //NOTE: signal widths can be decreased + always_comb begin + //clz input select mux + case({B,W64}) + 5'b00000_0: lzcA = A; //clz + 5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw + 5'b00001_0: lzcA = revA; //ctz + 5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + endcase + //cpop select mux + case ({B,W64}) + 5'b00010_0: popcntA = A; + 5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; + endcase + end end else begin - assign clzwA = 32'b0; - assign ctzwA = 32'b0; - assign cpopwA = 32'b0; + assign popcntA = A; + always_comb begin + //clz input slect mux + case(B) + 5'b00000: lzcA = A; + 5'b00001: lzcA = revA; + endcase + end end - //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. - lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); - lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); - lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); - lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult)); + popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult)); - popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); - popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); - - if (WIDTH==64) begin - assign clzResult = W64 ? clzwB : clzB; - assign ctzResult = W64 ? ctzwB : ctzB; - assign cpopResult = W64 ? cpopwB : cpopB; - end - else begin - assign clzResult = clzB; - assign ctzResult = ctzB; - assign cpopResult = cpopB; - end endmodule \ No newline at end of file From e4bfa4c548cb5d1233e1cab1f0bcb29d9e642db5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 16:45:37 +0000 Subject: [PATCH 023/183] modified zbb to account for cnt module change --- src/ieu/bmu/zbb.sv | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index caaa1985..98996f3b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -40,8 +40,7 @@ module zbb #(parameter WIDTH=32) ( // count results - logic [WIDTH-1:0] clzResult; // leading zeros result - logic [WIDTH-1:0] ctzResult; // trailing zeros result + logic [WIDTH-1:0] czResult; // count zeros result (lzc or tzc) logic [WIDTH-1:0] cpopResult; // population count result // byte results @@ -53,7 +52,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] sextbResult; // sign extend byte result logic [WIDTH-1:0] zexthResult; // zero extend halfword result - cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); + cnt cnt(.A(A), .B(B), .W64(W64), .czResult(czResult), .cpopResult(cpopResult)); byteUnit bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); ext ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); @@ -63,9 +62,9 @@ module zbb #(parameter WIDTH=32) ( 15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110000_001_00000: ZBBResult = clzResult; + 15'b0110000_001_00000: ZBBResult = czResult; 15'b0110000_001_00010: ZBBResult = cpopResult; - 15'b0110000_001_00001: ZBBResult = ctzResult; + 15'b0110000_001_00001: ZBBResult = czResult; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0000100_100_00000: ZBBResult = zexthResult; From 847a4145f12a41917a3e103b9b5e981d9f13b6d1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 19:07:22 +0000 Subject: [PATCH 024/183] added W64 zbb input signal in alu --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index e10591c1..15a19f55 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -131,7 +131,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBB_SUPPORTED) - zbb zbb(.A, .B, .Funct7, .Funct3, .ZBBResult); + zbb zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits From 726722bec27d568b83043e944db7a5b571bae047 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 19:18:54 +0000 Subject: [PATCH 025/183] Include Funct7 in execute - Modifed datapath to support funct7 in execute - Modified controller to pass on Funct7 - all lints pass --- src/ieu/controller.sv | 7 ++++--- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 1819de17..95b5efe8 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -48,6 +48,7 @@ module controller( output logic ALUResultSrcE, // Selects result to pass on to Memory stage output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field + output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation @@ -214,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index e1202bb9..f715a5d5 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -9,6 +9,7 @@ module datapath ( input logic [`XLEN-1:0] PCE, // PC in Execute stage input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage + input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic [2:0] ALUControlE, // Indicate operation ALU performs @@ -80,7 +81,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 681bd982..02eebe0a 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -74,6 +74,7 @@ module ieu ( logic [2:0] ImmSrcD; // Select type of immediate extension logic [1:0] FlagsE; // Comparison flags ({eq, lt}) + logic [6:0] Funct7E; // Instruction's funct7 field in execute stage logic [2:0] ALUControlE; // ALU control indicates function to perform logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage @@ -95,14 +96,14 @@ module ieu ( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, + .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From f9d934e5ae01de4c197307cf6a983bc103b023ab Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 10 Feb 2023 10:35:19 -0800 Subject: [PATCH 026/183] Added necessary files to make bit make and run bit manipulation tests as part of regression --- config/rv64gc/wally-config.vh | 8 +- sim/sim-wally-batch | 2 +- testbench/testbench.sv | 1 + testbench/tests.vh | 1437 ++++++++++--------- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 13 + tests/riscof/spike/spike_rv64gc_isa.yaml | 4 +- 6 files changed, 763 insertions(+), 702 deletions(-) create mode 100644 tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index c3dd8729..c0ee1d5e 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -145,10 +145,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch index 46c35c75..95fc677c 100755 --- a/sim/sim-wally-batch +++ b/sim/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-batch.do rv32gc wally32priv" +vsim -c -do "do wally-batch.do rv64gc arch64b" diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 329d4c60..d10fed36 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -105,6 +105,7 @@ logic [3:0] dummy; "coremark": tests = coremark; "fpga": tests = fpga; "ahb" : tests = ahb; + "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 case (TEST) diff --git a/testbench/tests.vh b/testbench/tests.vh index 3f9417b5..5bf239ad 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -98,741 +98,741 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, - "rv32i_m/F/FSQRT-S-DYN-RDN-01", - "rv32i_m/F/FADD-S-DYN-RDN-01", - "rv32i_m/F/FADD-S-DYN-RMM-01", - "rv32i_m/F/FADD-S-DYN-RNE-01", - "rv32i_m/F/FADD-S-DYN-RTZ-01", - "rv32i_m/F/FADD-S-DYN-RUP-01", - "rv32i_m/F/FADD-S-RDN-01", - "rv32i_m/F/FADD-S-RMM-01", - "rv32i_m/F/FADD-S-RNE-01", - "rv32i_m/F/FADD-S-RTZ-01", - "rv32i_m/F/FADD-S-RUP-01", - "rv32i_m/F/FCLASS-S-01", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01", - "rv32i_m/F/FCVT-S-W-RDN-01", - "rv32i_m/F/FCVT-S-W-RMM-01", - "rv32i_m/F/FCVT-S-W-RNE-01", - "rv32i_m/F/FCVT-S-W-RTZ-01", - "rv32i_m/F/FCVT-S-W-RUP-01", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", - "rv32i_m/F/FCVT-S-WU-RDN-01", - "rv32i_m/F/FCVT-S-WU-RMM-01", - "rv32i_m/F/FCVT-S-WU-RNE-01", - "rv32i_m/F/FCVT-S-WU-RTZ-01", - "rv32i_m/F/FCVT-S-WU-RUP-01", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01", - "rv32i_m/F/FCVT-W-S-RDN-01", - "rv32i_m/F/FCVT-W-S-RMM-01", - "rv32i_m/F/FCVT-W-S-RNE-01", - "rv32i_m/F/FCVT-W-S-RTZ-01", - "rv32i_m/F/FCVT-W-S-RUP-01", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", - "rv32i_m/F/FCVT-WU-S-RDN-01", - "rv32i_m/F/FCVT-WU-S-RMM-01", - "rv32i_m/F/FCVT-WU-S-RNE-01", - "rv32i_m/F/FCVT-WU-S-RTZ-01", - "rv32i_m/F/FCVT-WU-S-RUP-01", - "rv32i_m/F/FDIV-S-DYN-RDN-01", - "rv32i_m/F/FDIV-S-DYN-RMM-01", - "rv32i_m/F/FDIV-S-DYN-RNE-01", - "rv32i_m/F/FDIV-S-DYN-RTZ-01", - "rv32i_m/F/FDIV-S-DYN-RUP-01", - "rv32i_m/F/FDIV-S-RDN-01", - "rv32i_m/F/FDIV-S-RMM-01", - "rv32i_m/F/FDIV-S-RNE-01", - "rv32i_m/F/FDIV-S-RTZ-01", - "rv32i_m/F/FDIV-S-RUP-01", - "rv32i_m/F/FEQ-S-01", - "rv32i_m/F/FLE-S-01", - "rv32i_m/F/FLT-S-01", - "rv32i_m/F/FLW-01", - "rv32i_m/F/FMADD-S-DYN-RDN-01", - "rv32i_m/F/FMADD-S-DYN-RMM-01", - "rv32i_m/F/FMADD-S-DYN-RNE-01", - "rv32i_m/F/FMADD-S-DYN-RTZ-01", - "rv32i_m/F/FMADD-S-DYN-RUP-01", - "rv32i_m/F/FMADD-S-RDN-01", - "rv32i_m/F/FMADD-S-RMM-01", - "rv32i_m/F/FMADD-S-RNE-01", - "rv32i_m/F/FMADD-S-RTZ-01", - "rv32i_m/F/FMADD-S-RUP-01", - "rv32i_m/F/FMAX-S-01", - "rv32i_m/F/FMIN-S-01", - "rv32i_m/F/FMSUB-S-DYN-RDN-01", - "rv32i_m/F/FMSUB-S-DYN-RMM-01", - "rv32i_m/F/FMSUB-S-DYN-RNE-01", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01", - "rv32i_m/F/FMSUB-S-DYN-RUP-01", - "rv32i_m/F/FMSUB-S-RDN-01", - "rv32i_m/F/FMSUB-S-RMM-01", - "rv32i_m/F/FMSUB-S-RNE-01", - "rv32i_m/F/FMSUB-S-RTZ-01", - "rv32i_m/F/FMSUB-S-RUP-01", - "rv32i_m/F/FMUL-S-DYN-RDN-01", - "rv32i_m/F/FMUL-S-DYN-RMM-01", - "rv32i_m/F/FMUL-S-DYN-RNE-01", - "rv32i_m/F/FMUL-S-DYN-RTZ-01", - "rv32i_m/F/FMUL-S-DYN-RUP-01", - "rv32i_m/F/FMUL-S-RDN-01", - "rv32i_m/F/FMUL-S-RMM-01", - "rv32i_m/F/FMUL-S-RNE-01", - "rv32i_m/F/FMUL-S-RTZ-01", - "rv32i_m/F/FMUL-S-RUP-01", - "rv32i_m/F/FMV-W-X-01", - "rv32i_m/F/FMV-X-W-01", - "rv32i_m/F/FNMADD-S-DYN-RDN-01", - "rv32i_m/F/FNMADD-S-DYN-RMM-01", - "rv32i_m/F/FNMADD-S-DYN-RNE-01", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01", - "rv32i_m/F/FNMADD-S-DYN-RUP-01", - "rv32i_m/F/FNMADD-S-RDN-01", - "rv32i_m/F/FNMADD-S-RMM-01", - "rv32i_m/F/FNMADD-S-RNE-01", - "rv32i_m/F/FNMADD-S-RTZ-01", - "rv32i_m/F/FNMADD-S-RUP-01", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01", - "rv32i_m/F/FNMSUB-S-RDN-01", - "rv32i_m/F/FNMSUB-S-RMM-01", - "rv32i_m/F/FNMSUB-S-RNE-01", - "rv32i_m/F/FNMSUB-S-RTZ-01", - "rv32i_m/F/FNMSUB-S-RUP-01", - "rv32i_m/F/FSGNJN-S-01", - "rv32i_m/F/FSGNJ-S-01", - "rv32i_m/F/FSGNJX-S-01", - "rv32i_m/F/FSQRT-S-DYN-RDN-01", - "rv32i_m/F/FSQRT-S-DYN-RMM-01", - "rv32i_m/F/FSQRT-S-DYN-RNE-01", - "rv32i_m/F/FSQRT-S-DYN-RTZ-01", - "rv32i_m/F/FSQRT-S-DYN-RUP-01", - "rv32i_m/F/FSQRT-S-RDN-01", - "rv32i_m/F/FSQRT-S-RMM-01", - "rv32i_m/F/FSQRT-S-RNE-01", - "rv32i_m/F/FSQRT-S-RTZ-01", - "rv32i_m/F/FSQRT-S-RUP-01", - "rv32i_m/F/FSUB-S-DYN-RDN-01", - "rv32i_m/F/FSUB-S-DYN-RMM-01", - "rv32i_m/F/FSUB-S-DYN-RNE-01", - "rv32i_m/F/FSUB-S-DYN-RTZ-01", - "rv32i_m/F/FSUB-S-DYN-RUP-01", - "rv32i_m/F/FSUB-S-RDN-01", - "rv32i_m/F/FSUB-S-RMM-01", - "rv32i_m/F/FSUB-S-RNE-01", - "rv32i_m/F/FSUB-S-RTZ-01", - "rv32i_m/F/FSUB-S-RUP-01", - "rv32i_m/F/FSW-01" + "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", + "rv32i_m/F/FADD-S-DYN-RDN-01.S", + "rv32i_m/F/FADD-S-DYN-RMM-01.S", + "rv32i_m/F/FADD-S-DYN-RNE-01.S", + "rv32i_m/F/FADD-S-DYN-RTZ-01.S", + "rv32i_m/F/FADD-S-DYN-RUP-01.S", + "rv32i_m/F/FADD-S-RDN-01.S", + "rv32i_m/F/FADD-S-RMM-01.S", + "rv32i_m/F/FADD-S-RNE-01.S", + "rv32i_m/F/FADD-S-RTZ-01.S", + "rv32i_m/F/FADD-S-RUP-01.S", + "rv32i_m/F/FCLASS-S-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01.S", + "rv32i_m/F/FCVT-S-W-RDN-01.S", + "rv32i_m/F/FCVT-S-W-RMM-01.S", + "rv32i_m/F/FCVT-S-W-RNE-01.S", + "rv32i_m/F/FCVT-S-W-RTZ-01.S", + "rv32i_m/F/FCVT-S-W-RUP-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01.S", + "rv32i_m/F/FCVT-S-WU-RDN-01.S", + "rv32i_m/F/FCVT-S-WU-RMM-01.S", + "rv32i_m/F/FCVT-S-WU-RNE-01.S", + "rv32i_m/F/FCVT-S-WU-RTZ-01.S", + "rv32i_m/F/FCVT-S-WU-RUP-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01.S", + "rv32i_m/F/FCVT-W-S-RDN-01.S", + "rv32i_m/F/FCVT-W-S-RMM-01.S", + "rv32i_m/F/FCVT-W-S-RNE-01.S", + "rv32i_m/F/FCVT-W-S-RTZ-01.S", + "rv32i_m/F/FCVT-W-S-RUP-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01.S", + "rv32i_m/F/FCVT-WU-S-RDN-01.S", + "rv32i_m/F/FCVT-WU-S-RMM-01.S", + "rv32i_m/F/FCVT-WU-S-RNE-01.S", + "rv32i_m/F/FCVT-WU-S-RTZ-01.S", + "rv32i_m/F/FCVT-WU-S-RUP-01.S", + "rv32i_m/F/FDIV-S-DYN-RDN-01.S", + "rv32i_m/F/FDIV-S-DYN-RMM-01.S", + "rv32i_m/F/FDIV-S-DYN-RNE-01.S", + "rv32i_m/F/FDIV-S-DYN-RTZ-01.S", + "rv32i_m/F/FDIV-S-DYN-RUP-01.S", + "rv32i_m/F/FDIV-S-RDN-01.S", + "rv32i_m/F/FDIV-S-RMM-01.S", + "rv32i_m/F/FDIV-S-RNE-01.S", + "rv32i_m/F/FDIV-S-RTZ-01.S", + "rv32i_m/F/FDIV-S-RUP-01.S", + "rv32i_m/F/FEQ-S-01.S", + "rv32i_m/F/FLE-S-01.S", + "rv32i_m/F/FLT-S-01.S", + "rv32i_m/F/FLW-01.S", + "rv32i_m/F/FMADD-S-DYN-RDN-01.S", + "rv32i_m/F/FMADD-S-DYN-RMM-01.S", + "rv32i_m/F/FMADD-S-DYN-RNE-01.S", + "rv32i_m/F/FMADD-S-DYN-RTZ-01.S", + "rv32i_m/F/FMADD-S-DYN-RUP-01.S", + "rv32i_m/F/FMADD-S-RDN-01.S", + "rv32i_m/F/FMADD-S-RMM-01.S", + "rv32i_m/F/FMADD-S-RNE-01.S", + "rv32i_m/F/FMADD-S-RTZ-01.S", + "rv32i_m/F/FMADD-S-RUP-01.S", + "rv32i_m/F/FMAX-S-01.S", + "rv32i_m/F/FMIN-S-01.S", + "rv32i_m/F/FMSUB-S-DYN-RDN-01.S", + "rv32i_m/F/FMSUB-S-DYN-RMM-01.S", + "rv32i_m/F/FMSUB-S-DYN-RNE-01.S", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01.S", + "rv32i_m/F/FMSUB-S-DYN-RUP-01.S", + "rv32i_m/F/FMSUB-S-RDN-01.S", + "rv32i_m/F/FMSUB-S-RMM-01.S", + "rv32i_m/F/FMSUB-S-RNE-01.S", + "rv32i_m/F/FMSUB-S-RTZ-01.S", + "rv32i_m/F/FMSUB-S-RUP-01.S", + "rv32i_m/F/FMUL-S-DYN-RDN-01.S", + "rv32i_m/F/FMUL-S-DYN-RMM-01.S", + "rv32i_m/F/FMUL-S-DYN-RNE-01.S", + "rv32i_m/F/FMUL-S-DYN-RTZ-01.S", + "rv32i_m/F/FMUL-S-DYN-RUP-01.S", + "rv32i_m/F/FMUL-S-RDN-01.S", + "rv32i_m/F/FMUL-S-RMM-01.S", + "rv32i_m/F/FMUL-S-RNE-01.S", + "rv32i_m/F/FMUL-S-RTZ-01.S", + "rv32i_m/F/FMUL-S-RUP-01.S", + "rv32i_m/F/FMV-W-X-01.S", + "rv32i_m/F/FMV-X-W-01.S", + "rv32i_m/F/FNMADD-S-DYN-RDN-01.S", + "rv32i_m/F/FNMADD-S-DYN-RMM-01.S", + "rv32i_m/F/FNMADD-S-DYN-RNE-01.S", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01.S", + "rv32i_m/F/FNMADD-S-DYN-RUP-01.S", + "rv32i_m/F/FNMADD-S-RDN-01.S", + "rv32i_m/F/FNMADD-S-RMM-01.S", + "rv32i_m/F/FNMADD-S-RNE-01.S", + "rv32i_m/F/FNMADD-S-RTZ-01.S", + "rv32i_m/F/FNMADD-S-RUP-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01.S", + "rv32i_m/F/FNMSUB-S-RDN-01.S", + "rv32i_m/F/FNMSUB-S-RMM-01.S", + "rv32i_m/F/FNMSUB-S-RNE-01.S", + "rv32i_m/F/FNMSUB-S-RTZ-01.S", + "rv32i_m/F/FNMSUB-S-RUP-01.S", + "rv32i_m/F/FSGNJN-S-01.S", + "rv32i_m/F/FSGNJ-S-01.S", + "rv32i_m/F/FSGNJX-S-01.S", + "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", + "rv32i_m/F/FSQRT-S-DYN-RMM-01.S", + "rv32i_m/F/FSQRT-S-DYN-RNE-01.S", + "rv32i_m/F/FSQRT-S-DYN-RTZ-01.S", + "rv32i_m/F/FSQRT-S-DYN-RUP-01.S", + "rv32i_m/F/FSQRT-S-RDN-01.S", + "rv32i_m/F/FSQRT-S-RMM-01.S", + "rv32i_m/F/FSQRT-S-RNE-01.S", + "rv32i_m/F/FSQRT-S-RTZ-01.S", + "rv32i_m/F/FSQRT-S-RUP-01.S", + "rv32i_m/F/FSUB-S-DYN-RDN-01.S", + "rv32i_m/F/FSUB-S-DYN-RMM-01.S", + "rv32i_m/F/FSUB-S-DYN-RNE-01.S", + "rv32i_m/F/FSUB-S-DYN-RTZ-01.S", + "rv32i_m/F/FSUB-S-DYN-RUP-01.S", + "rv32i_m/F/FSUB-S-RDN-01.S", + "rv32i_m/F/FSUB-S-RMM-01.S", + "rv32i_m/F/FSUB-S-RNE-01.S", + "rv32i_m/F/FSUB-S-RTZ-01.S", + "rv32i_m/F/FSUB-S-RUP-01.S", + "rv32i_m/F/FSW-01.S" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01", - "rv64i_m/F/FADD-S-DYN-RMM-01", - "rv64i_m/F/FADD-S-DYN-RNE-01", - "rv64i_m/F/FADD-S-DYN-RTZ-01", - "rv64i_m/F/FADD-S-DYN-RUP-01", - "rv64i_m/F/FADD-S-RDN-01", - "rv64i_m/F/FADD-S-RMM-01", - "rv64i_m/F/FADD-S-RNE-01", - "rv64i_m/F/FADD-S-RTZ-01", - "rv64i_m/F/FADD-S-RUP-01", - "rv64i_m/F/FCLASS-S-01", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01", - "rv64i_m/F/FCVT-L-S-RDN-01", - "rv64i_m/F/FCVT-L-S-RMM-01", - "rv64i_m/F/FCVT-L-S-RNE-01", - "rv64i_m/F/FCVT-L-S-RTZ-01", - "rv64i_m/F/FCVT-L-S-RUP-01", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", - "rv64i_m/F/FCVT-LU-S-RDN-01", - "rv64i_m/F/FCVT-LU-S-RMM-01", - "rv64i_m/F/FCVT-LU-S-RNE-01", - "rv64i_m/F/FCVT-LU-S-RTZ-01", - "rv64i_m/F/FCVT-LU-S-RUP-01", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01", - "rv64i_m/F/FCVT-S-L-RDN-01", - "rv64i_m/F/FCVT-S-L-RMM-01", - "rv64i_m/F/FCVT-S-L-RNE-01", - "rv64i_m/F/FCVT-S-L-RTZ-01", - "rv64i_m/F/FCVT-S-L-RUP-01", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", - "rv64i_m/F/FCVT-S-LU-RDN-01", - "rv64i_m/F/FCVT-S-LU-RMM-01", - "rv64i_m/F/FCVT-S-LU-RNE-01", - "rv64i_m/F/FCVT-S-LU-RTZ-01", - "rv64i_m/F/FCVT-S-LU-RUP-01", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01", - "rv64i_m/F/FCVT-S-W-RDN-01", - "rv64i_m/F/FCVT-S-W-RMM-01", - "rv64i_m/F/FCVT-S-W-RNE-01", - "rv64i_m/F/FCVT-S-W-RTZ-01", - "rv64i_m/F/FCVT-S-W-RUP-01", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", - "rv64i_m/F/FCVT-S-WU-RDN-01", - "rv64i_m/F/FCVT-S-WU-RMM-01", - "rv64i_m/F/FCVT-S-WU-RNE-01", - "rv64i_m/F/FCVT-S-WU-RTZ-01", - "rv64i_m/F/FCVT-S-WU-RUP-01", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01", - "rv64i_m/F/FCVT-W-S-RDN-01", - "rv64i_m/F/FCVT-W-S-RMM-01", - "rv64i_m/F/FCVT-W-S-RNE-01", - "rv64i_m/F/FCVT-W-S-RTZ-01", - "rv64i_m/F/FCVT-W-S-RUP-01", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", - "rv64i_m/F/FCVT-WU-S-RDN-01", - "rv64i_m/F/FCVT-WU-S-RMM-01", - "rv64i_m/F/FCVT-WU-S-RNE-01", - "rv64i_m/F/FCVT-WU-S-RTZ-01", - "rv64i_m/F/FCVT-WU-S-RUP-01", - "rv64i_m/F/FDIV-S-DYN-RDN-01", - "rv64i_m/F/FDIV-S-DYN-RMM-01", - "rv64i_m/F/FDIV-S-DYN-RNE-01", - "rv64i_m/F/FDIV-S-DYN-RTZ-01", - "rv64i_m/F/FDIV-S-DYN-RUP-01", - "rv64i_m/F/FDIV-S-RDN-01", - "rv64i_m/F/FDIV-S-RMM-01", - "rv64i_m/F/FDIV-S-RNE-01", - "rv64i_m/F/FDIV-S-RTZ-01", - "rv64i_m/F/FDIV-S-RUP-01", - "rv64i_m/F/FEQ-S-01", - "rv64i_m/F/FLE-S-01", - "rv64i_m/F/FLT-S-01", - "rv64i_m/F/FLW-01", - "rv64i_m/F/FMADD-S-DYN-RDN-01", - "rv64i_m/F/FMADD-S-DYN-RMM-01", - "rv64i_m/F/FMADD-S-DYN-RNE-01", - "rv64i_m/F/FMADD-S-DYN-RTZ-01", - "rv64i_m/F/FMADD-S-DYN-RUP-01", - "rv64i_m/F/FMADD-S-RDN-01", - "rv64i_m/F/FMADD-S-RMM-01", - "rv64i_m/F/FMADD-S-RNE-01", - "rv64i_m/F/FMADD-S-RTZ-01", - "rv64i_m/F/FMADD-S-RUP-01", - "rv64i_m/F/FMAX-S-01", - "rv64i_m/F/FMIN-S-01", - "rv64i_m/F/FMSUB-S-DYN-RDN-01", - "rv64i_m/F/FMSUB-S-DYN-RMM-01", - "rv64i_m/F/FMSUB-S-DYN-RNE-01", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01", - "rv64i_m/F/FMSUB-S-DYN-RUP-01", - "rv64i_m/F/FMSUB-S-RDN-01", - "rv64i_m/F/FMSUB-S-RMM-01", - "rv64i_m/F/FMSUB-S-RNE-01", - "rv64i_m/F/FMSUB-S-RTZ-01", - "rv64i_m/F/FMSUB-S-RUP-01", - "rv64i_m/F/FMUL-S-DYN-RDN-01", - "rv64i_m/F/FMUL-S-DYN-RMM-01", - "rv64i_m/F/FMUL-S-DYN-RNE-01", - "rv64i_m/F/FMUL-S-DYN-RTZ-01", - "rv64i_m/F/FMUL-S-DYN-RUP-01", - "rv64i_m/F/FMUL-S-RDN-01", - "rv64i_m/F/FMUL-S-RMM-01", - "rv64i_m/F/FMUL-S-RNE-01", - "rv64i_m/F/FMUL-S-RTZ-01", - "rv64i_m/F/FMUL-S-RUP-01", - "rv64i_m/F/FMV-W-X-01", - "rv64i_m/F/FMV-X-W-01", - "rv64i_m/F/FNMADD-S-DYN-RDN-01", - "rv64i_m/F/FNMADD-S-DYN-RMM-01", - "rv64i_m/F/FNMADD-S-DYN-RNE-01", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01", - "rv64i_m/F/FNMADD-S-DYN-RUP-01", - "rv64i_m/F/FNMADD-S-RDN-01", - "rv64i_m/F/FNMADD-S-RMM-01", - "rv64i_m/F/FNMADD-S-RNE-01", - "rv64i_m/F/FNMADD-S-RTZ-01", - "rv64i_m/F/FNMADD-S-RUP-01", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01", - "rv64i_m/F/FNMSUB-S-RDN-01", - "rv64i_m/F/FNMSUB-S-RMM-01", - "rv64i_m/F/FNMSUB-S-RNE-01", - "rv64i_m/F/FNMSUB-S-RTZ-01", - "rv64i_m/F/FNMSUB-S-RUP-01", - "rv64i_m/F/FSGNJN-S-01", - "rv64i_m/F/FSGNJ-S-01", - "rv64i_m/F/FSGNJX-S-01", - "rv64i_m/F/FSQRT-S-DYN-RDN-01", - "rv64i_m/F/FSQRT-S-DYN-RMM-01", - "rv64i_m/F/FSQRT-S-DYN-RNE-01", - "rv64i_m/F/FSQRT-S-DYN-RTZ-01", - "rv64i_m/F/FSQRT-S-DYN-RUP-01", - "rv64i_m/F/FSQRT-S-RDN-01", - "rv64i_m/F/FSQRT-S-RMM-01", - "rv64i_m/F/FSQRT-S-RNE-01", - "rv64i_m/F/FSQRT-S-RTZ-01", - "rv64i_m/F/FSQRT-S-RUP-01", - "rv64i_m/F/FSUB-S-DYN-RDN-01", - "rv64i_m/F/FSUB-S-DYN-RMM-01", - "rv64i_m/F/FSUB-S-DYN-RNE-01", - "rv64i_m/F/FSUB-S-DYN-RTZ-01", - "rv64i_m/F/FSUB-S-DYN-RUP-01", - "rv64i_m/F/FSUB-S-RDN-01", - "rv64i_m/F/FSUB-S-RMM-01", - "rv64i_m/F/FSUB-S-RNE-01", - "rv64i_m/F/FSUB-S-RTZ-01", - "rv64i_m/F/FSUB-S-RUP-01", - "rv64i_m/F/FSW-01" + "rv64i_m/F/FADD-S-DYN-RDN-01.S", + "rv64i_m/F/FADD-S-DYN-RMM-01.S", + "rv64i_m/F/FADD-S-DYN-RNE-01.S", + "rv64i_m/F/FADD-S-DYN-RTZ-01.S", + "rv64i_m/F/FADD-S-DYN-RUP-01.S", + "rv64i_m/F/FADD-S-RDN-01.S", + "rv64i_m/F/FADD-S-RMM-01.S", + "rv64i_m/F/FADD-S-RNE-01.S", + "rv64i_m/F/FADD-S-RTZ-01.S", + "rv64i_m/F/FADD-S-RUP-01.S", + "rv64i_m/F/FCLASS-S-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-L-S-RDN-01.S", + "rv64i_m/F/FCVT-L-S-RMM-01.S", + "rv64i_m/F/FCVT-L-S-RNE-01.S", + "rv64i_m/F/FCVT-L-S-RTZ-01.S", + "rv64i_m/F/FCVT-L-S-RUP-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-LU-S-RDN-01.S", + "rv64i_m/F/FCVT-LU-S-RMM-01.S", + "rv64i_m/F/FCVT-LU-S-RNE-01.S", + "rv64i_m/F/FCVT-LU-S-RTZ-01.S", + "rv64i_m/F/FCVT-LU-S-RUP-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-L-RDN-01.S", + "rv64i_m/F/FCVT-S-L-RMM-01.S", + "rv64i_m/F/FCVT-S-L-RNE-01.S", + "rv64i_m/F/FCVT-S-L-RTZ-01.S", + "rv64i_m/F/FCVT-S-L-RUP-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-LU-RDN-01.S", + "rv64i_m/F/FCVT-S-LU-RMM-01.S", + "rv64i_m/F/FCVT-S-LU-RNE-01.S", + "rv64i_m/F/FCVT-S-LU-RTZ-01.S", + "rv64i_m/F/FCVT-S-LU-RUP-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-W-RDN-01.S", + "rv64i_m/F/FCVT-S-W-RMM-01.S", + "rv64i_m/F/FCVT-S-W-RNE-01.S", + "rv64i_m/F/FCVT-S-W-RTZ-01.S", + "rv64i_m/F/FCVT-S-W-RUP-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-WU-RDN-01.S", + "rv64i_m/F/FCVT-S-WU-RMM-01.S", + "rv64i_m/F/FCVT-S-WU-RNE-01.S", + "rv64i_m/F/FCVT-S-WU-RTZ-01.S", + "rv64i_m/F/FCVT-S-WU-RUP-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-W-S-RDN-01.S", + "rv64i_m/F/FCVT-W-S-RMM-01.S", + "rv64i_m/F/FCVT-W-S-RNE-01.S", + "rv64i_m/F/FCVT-W-S-RTZ-01.S", + "rv64i_m/F/FCVT-W-S-RUP-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-WU-S-RDN-01.S", + "rv64i_m/F/FCVT-WU-S-RMM-01.S", + "rv64i_m/F/FCVT-WU-S-RNE-01.S", + "rv64i_m/F/FCVT-WU-S-RTZ-01.S", + "rv64i_m/F/FCVT-WU-S-RUP-01.S", + "rv64i_m/F/FDIV-S-DYN-RDN-01.S", + "rv64i_m/F/FDIV-S-DYN-RMM-01.S", + "rv64i_m/F/FDIV-S-DYN-RNE-01.S", + "rv64i_m/F/FDIV-S-DYN-RTZ-01.S", + "rv64i_m/F/FDIV-S-DYN-RUP-01.S", + "rv64i_m/F/FDIV-S-RDN-01.S", + "rv64i_m/F/FDIV-S-RMM-01.S", + "rv64i_m/F/FDIV-S-RNE-01.S", + "rv64i_m/F/FDIV-S-RTZ-01.S", + "rv64i_m/F/FDIV-S-RUP-01.S", + "rv64i_m/F/FEQ-S-01.S", + "rv64i_m/F/FLE-S-01.S", + "rv64i_m/F/FLT-S-01.S", + "rv64i_m/F/FLW-01.S", + "rv64i_m/F/FMADD-S-DYN-RDN-01.S", + "rv64i_m/F/FMADD-S-DYN-RMM-01.S", + "rv64i_m/F/FMADD-S-DYN-RNE-01.S", + "rv64i_m/F/FMADD-S-DYN-RTZ-01.S", + "rv64i_m/F/FMADD-S-DYN-RUP-01.S", + "rv64i_m/F/FMADD-S-RDN-01.S", + "rv64i_m/F/FMADD-S-RMM-01.S", + "rv64i_m/F/FMADD-S-RNE-01.S", + "rv64i_m/F/FMADD-S-RTZ-01.S", + "rv64i_m/F/FMADD-S-RUP-01.S", + "rv64i_m/F/FMAX-S-01.S", + "rv64i_m/F/FMIN-S-01.S", + "rv64i_m/F/FMSUB-S-DYN-RDN-01.S", + "rv64i_m/F/FMSUB-S-DYN-RMM-01.S", + "rv64i_m/F/FMSUB-S-DYN-RNE-01.S", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01.S", + "rv64i_m/F/FMSUB-S-DYN-RUP-01.S", + "rv64i_m/F/FMSUB-S-RDN-01.S", + "rv64i_m/F/FMSUB-S-RMM-01.S", + "rv64i_m/F/FMSUB-S-RNE-01.S", + "rv64i_m/F/FMSUB-S-RTZ-01.S", + "rv64i_m/F/FMSUB-S-RUP-01.S", + "rv64i_m/F/FMUL-S-DYN-RDN-01.S", + "rv64i_m/F/FMUL-S-DYN-RMM-01.S", + "rv64i_m/F/FMUL-S-DYN-RNE-01.S", + "rv64i_m/F/FMUL-S-DYN-RTZ-01.S", + "rv64i_m/F/FMUL-S-DYN-RUP-01.S", + "rv64i_m/F/FMUL-S-RDN-01.S", + "rv64i_m/F/FMUL-S-RMM-01.S", + "rv64i_m/F/FMUL-S-RNE-01.S", + "rv64i_m/F/FMUL-S-RTZ-01.S", + "rv64i_m/F/FMUL-S-RUP-01.S", + "rv64i_m/F/FMV-W-X-01.S", + "rv64i_m/F/FMV-X-W-01.S", + "rv64i_m/F/FNMADD-S-DYN-RDN-01.S", + "rv64i_m/F/FNMADD-S-DYN-RMM-01.S", + "rv64i_m/F/FNMADD-S-DYN-RNE-01.S", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01.S", + "rv64i_m/F/FNMADD-S-DYN-RUP-01.S", + "rv64i_m/F/FNMADD-S-RDN-01.S", + "rv64i_m/F/FNMADD-S-RMM-01.S", + "rv64i_m/F/FNMADD-S-RNE-01.S", + "rv64i_m/F/FNMADD-S-RTZ-01.S", + "rv64i_m/F/FNMADD-S-RUP-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01.S", + "rv64i_m/F/FNMSUB-S-RDN-01.S", + "rv64i_m/F/FNMSUB-S-RMM-01.S", + "rv64i_m/F/FNMSUB-S-RNE-01.S", + "rv64i_m/F/FNMSUB-S-RTZ-01.S", + "rv64i_m/F/FNMSUB-S-RUP-01.S", + "rv64i_m/F/FSGNJN-S-01.S", + "rv64i_m/F/FSGNJ-S-01.S", + "rv64i_m/F/FSGNJX-S-01.S", + "rv64i_m/F/FSQRT-S-DYN-RDN-01.S", + "rv64i_m/F/FSQRT-S-DYN-RMM-01.S", + "rv64i_m/F/FSQRT-S-DYN-RNE-01.S", + "rv64i_m/F/FSQRT-S-DYN-RTZ-01.S", + "rv64i_m/F/FSQRT-S-DYN-RUP-01.S", + "rv64i_m/F/FSQRT-S-RDN-01.S", + "rv64i_m/F/FSQRT-S-RMM-01.S", + "rv64i_m/F/FSQRT-S-RNE-01.S", + "rv64i_m/F/FSQRT-S-RTZ-01.S", + "rv64i_m/F/FSQRT-S-RUP-01.S", + "rv64i_m/F/FSUB-S-DYN-RDN-01.S", + "rv64i_m/F/FSUB-S-DYN-RMM-01.S", + "rv64i_m/F/FSUB-S-DYN-RNE-01.S", + "rv64i_m/F/FSUB-S-DYN-RTZ-01.S", + "rv64i_m/F/FSUB-S-DYN-RUP-01.S", + "rv64i_m/F/FSUB-S-RDN-01.S", + "rv64i_m/F/FSUB-S-RMM-01.S", + "rv64i_m/F/FSUB-S-RNE-01.S", + "rv64i_m/F/FSUB-S-RTZ-01.S", + "rv64i_m/F/FSUB-S-RUP-01.S", + "rv64i_m/F/FSW-01.S" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01", - "rv64i_m/D/FADD-D-DYN-RMM-01", - "rv64i_m/D/FADD-D-DYN-RNE-01", - "rv64i_m/D/FADD-D-DYN-RTZ-01", - "rv64i_m/D/FADD-D-DYN-RUP-01", - "rv64i_m/D/FADD-D-RDN-01", - "rv64i_m/D/FADD-D-RMM-01", - "rv64i_m/D/FADD-D-RNE-01", - "rv64i_m/D/FADD-D-RTZ-01", - "rv64i_m/D/FADD-D-RUP-01", - "rv64i_m/D/FCLASS-D-01", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01", - "rv64i_m/D/FCVT-D-L-RDN-01", - "rv64i_m/D/FCVT-D-L-RMM-01", - "rv64i_m/D/FCVT-D-L-RNE-01", - "rv64i_m/D/FCVT-D-L-RTZ-01", - "rv64i_m/D/FCVT-D-L-RUP-01", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", - "rv64i_m/D/FCVT-D-LU-RDN-01", - "rv64i_m/D/FCVT-D-LU-RMM-01", - "rv64i_m/D/FCVT-D-LU-RNE-01", - "rv64i_m/D/FCVT-D-LU-RTZ-01", - "rv64i_m/D/FCVT-D-LU-RUP-01", - "rv64i_m/D/FCVT-D-S-01", - "rv64i_m/D/FCVT-D-W-01", - "rv64i_m/D/FCVT-D-WU-01", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01", - "rv64i_m/D/FCVT-L-D-RDN-01", - "rv64i_m/D/FCVT-L-D-RMM-01", - "rv64i_m/D/FCVT-L-D-RNE-01", - "rv64i_m/D/FCVT-L-D-RTZ-01", - "rv64i_m/D/FCVT-L-D-RUP-01", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", - "rv64i_m/D/FCVT-LU-D-RDN-01", - "rv64i_m/D/FCVT-LU-D-RMM-01", - "rv64i_m/D/FCVT-LU-D-RNE-01", - "rv64i_m/D/FCVT-LU-D-RTZ-01", - "rv64i_m/D/FCVT-LU-D-RUP-01", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01", - "rv64i_m/D/FCVT-S-D-RDN-01", - "rv64i_m/D/FCVT-S-D-RMM-01", - "rv64i_m/D/FCVT-S-D-RNE-01", - "rv64i_m/D/FCVT-S-D-RTZ-01", - "rv64i_m/D/FCVT-S-D-RUP-01", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01", - "rv64i_m/D/FCVT-W-D-RDN-01", - "rv64i_m/D/FCVT-W-D-RMM-01", - "rv64i_m/D/FCVT-W-D-RNE-01", - "rv64i_m/D/FCVT-W-D-RTZ-01", - "rv64i_m/D/FCVT-W-D-RUP-01", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", - "rv64i_m/D/FCVT-WU-D-RDN-01", - "rv64i_m/D/FCVT-WU-D-RMM-01", - "rv64i_m/D/FCVT-WU-D-RNE-01", - "rv64i_m/D/FCVT-WU-D-RTZ-01", - "rv64i_m/D/FCVT-WU-D-RUP-01", - "rv64i_m/D/FDIV-D-DYN-RDN-01", - "rv64i_m/D/FDIV-D-DYN-RMM-01", - "rv64i_m/D/FDIV-D-DYN-RNE-01", - "rv64i_m/D/FDIV-D-DYN-RTZ-01", - "rv64i_m/D/FDIV-D-DYN-RUP-01", - "rv64i_m/D/FDIV-D-RDN-01", - "rv64i_m/D/FDIV-D-RMM-01", - "rv64i_m/D/FDIV-D-RNE-01", - "rv64i_m/D/FDIV-D-RTZ-01", - "rv64i_m/D/FDIV-D-RUP-01", - "rv64i_m/D/FEQ-D-01", - "rv64i_m/D/FLD-01", - "rv64i_m/D/FLE-D-01", - "rv64i_m/D/FLT-D-01", - "rv64i_m/D/FMADD-D-DYN-RDN-01", - "rv64i_m/D/FMADD-D-DYN-RMM-01", - "rv64i_m/D/FMADD-D-DYN-RNE-01", - "rv64i_m/D/FMADD-D-DYN-RTZ-01", - "rv64i_m/D/FMADD-D-DYN-RUP-01", - "rv64i_m/D/FMADD-D-RDN-01", - "rv64i_m/D/FMADD-D-RMM-01", - "rv64i_m/D/FMADD-D-RNE-01", - "rv64i_m/D/FMADD-D-RTZ-01", - "rv64i_m/D/FMADD-D-RUP-01", - "rv64i_m/D/FMAX-D-01", - "rv64i_m/D/FMIN-D-01", - "rv64i_m/D/FMSUB-D-DYN-RDN-01", - "rv64i_m/D/FMSUB-D-DYN-RMM-01", - "rv64i_m/D/FMSUB-D-DYN-RNE-01", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01", - "rv64i_m/D/FMSUB-D-DYN-RUP-01", - "rv64i_m/D/FMSUB-D-RDN-01", - "rv64i_m/D/FMSUB-D-RMM-01", - "rv64i_m/D/FMSUB-D-RNE-01", - "rv64i_m/D/FMSUB-D-RTZ-01", - "rv64i_m/D/FMSUB-D-RUP-01", - "rv64i_m/D/FMUL-D-DYN-RDN-01", - "rv64i_m/D/FMUL-D-DYN-RMM-01", - "rv64i_m/D/FMUL-D-DYN-RNE-01", - "rv64i_m/D/FMUL-D-DYN-RTZ-01", - "rv64i_m/D/FMUL-D-DYN-RUP-01", - "rv64i_m/D/FMUL-D-RDN-01", - "rv64i_m/D/FMUL-D-RMM-01", - "rv64i_m/D/FMUL-D-RNE-01", - "rv64i_m/D/FMUL-D-RTZ-01", - "rv64i_m/D/FMUL-D-RUP-01", - "rv64i_m/D/FMV-D-X-01", - "rv64i_m/D/FMV-X-D-01", - "rv64i_m/D/FNMADD-D-DYN-RDN-01", - "rv64i_m/D/FNMADD-D-DYN-RMM-01", - "rv64i_m/D/FNMADD-D-DYN-RNE-01", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01", - "rv64i_m/D/FNMADD-D-DYN-RUP-01", - "rv64i_m/D/FNMADD-D-RDN-01", - "rv64i_m/D/FNMADD-D-RMM-01", - "rv64i_m/D/FNMADD-D-RNE-01", - "rv64i_m/D/FNMADD-D-RTZ-01", - "rv64i_m/D/FNMADD-D-RUP-01", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01", - "rv64i_m/D/FNMSUB-D-RDN-01", - "rv64i_m/D/FNMSUB-D-RMM-01", - "rv64i_m/D/FNMSUB-D-RNE-01", - "rv64i_m/D/FNMSUB-D-RTZ-01", - "rv64i_m/D/FNMSUB-D-RUP-01", - "rv64i_m/D/FSD-01", - "rv64i_m/D/FSGNJ-D-01", - "rv64i_m/D/FSGNJN-D-01", - "rv64i_m/D/FSGNJX-D-01", - "rv64i_m/D/FSQRT-D-DYN-RDN-01", - "rv64i_m/D/FSQRT-D-DYN-RMM-01", - "rv64i_m/D/FSQRT-D-DYN-RNE-01", - "rv64i_m/D/FSQRT-D-DYN-RTZ-01", - "rv64i_m/D/FSQRT-D-DYN-RUP-01", - "rv64i_m/D/FSQRT-D-RDN-01", - "rv64i_m/D/FSQRT-D-RMM-01", - "rv64i_m/D/FSQRT-D-RNE-01", - "rv64i_m/D/FSQRT-D-RTZ-01", - "rv64i_m/D/FSQRT-D-RUP-01", - "rv64i_m/D/FSUB-D-DYN-RDN-01", - "rv64i_m/D/FSUB-D-DYN-RMM-01", - "rv64i_m/D/FSUB-D-DYN-RNE-01", - "rv64i_m/D/FSUB-D-DYN-RTZ-01", - "rv64i_m/D/FSUB-D-DYN-RUP-01", - "rv64i_m/D/FSUB-D-RDN-01", - "rv64i_m/D/FSUB-D-RMM-01", - "rv64i_m/D/FSUB-D-RNE-01", - "rv64i_m/D/FSUB-D-RTZ-01", - "rv64i_m/D/FSUB-D-RUP-01" + "rv64i_m/D/FADD-D-DYN-RDN-01.S", + "rv64i_m/D/FADD-D-DYN-RMM-01.S", + "rv64i_m/D/FADD-D-DYN-RNE-01.S", + "rv64i_m/D/FADD-D-DYN-RTZ-01.S", + "rv64i_m/D/FADD-D-DYN-RUP-01.S", + "rv64i_m/D/FADD-D-RDN-01.S", + "rv64i_m/D/FADD-D-RMM-01.S", + "rv64i_m/D/FADD-D-RNE-01.S", + "rv64i_m/D/FADD-D-RTZ-01.S", + "rv64i_m/D/FADD-D-RUP-01.S", + "rv64i_m/D/FCLASS-D-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01.S", + "rv64i_m/D/FCVT-D-L-RDN-01.S", + "rv64i_m/D/FCVT-D-L-RMM-01.S", + "rv64i_m/D/FCVT-D-L-RNE-01.S", + "rv64i_m/D/FCVT-D-L-RTZ-01.S", + "rv64i_m/D/FCVT-D-L-RUP-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01.S", + "rv64i_m/D/FCVT-D-LU-RDN-01.S", + "rv64i_m/D/FCVT-D-LU-RMM-01.S", + "rv64i_m/D/FCVT-D-LU-RNE-01.S", + "rv64i_m/D/FCVT-D-LU-RTZ-01.S", + "rv64i_m/D/FCVT-D-LU-RUP-01.S", + "rv64i_m/D/FCVT-D-S-01.S", + "rv64i_m/D/FCVT-D-W-01.S", + "rv64i_m/D/FCVT-D-WU-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-L-D-RDN-01.S", + "rv64i_m/D/FCVT-L-D-RMM-01.S", + "rv64i_m/D/FCVT-L-D-RNE-01.S", + "rv64i_m/D/FCVT-L-D-RTZ-01.S", + "rv64i_m/D/FCVT-L-D-RUP-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-LU-D-RDN-01.S", + "rv64i_m/D/FCVT-LU-D-RMM-01.S", + "rv64i_m/D/FCVT-LU-D-RNE-01.S", + "rv64i_m/D/FCVT-LU-D-RTZ-01.S", + "rv64i_m/D/FCVT-LU-D-RUP-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-S-D-RDN-01.S", + "rv64i_m/D/FCVT-S-D-RMM-01.S", + "rv64i_m/D/FCVT-S-D-RNE-01.S", + "rv64i_m/D/FCVT-S-D-RTZ-01.S", + "rv64i_m/D/FCVT-S-D-RUP-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-W-D-RDN-01.S", + "rv64i_m/D/FCVT-W-D-RMM-01.S", + "rv64i_m/D/FCVT-W-D-RNE-01.S", + "rv64i_m/D/FCVT-W-D-RTZ-01.S", + "rv64i_m/D/FCVT-W-D-RUP-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-WU-D-RDN-01.S", + "rv64i_m/D/FCVT-WU-D-RMM-01.S", + "rv64i_m/D/FCVT-WU-D-RNE-01.S", + "rv64i_m/D/FCVT-WU-D-RTZ-01.S", + "rv64i_m/D/FCVT-WU-D-RUP-01.S", + "rv64i_m/D/FDIV-D-DYN-RDN-01.S", + "rv64i_m/D/FDIV-D-DYN-RMM-01.S", + "rv64i_m/D/FDIV-D-DYN-RNE-01.S", + "rv64i_m/D/FDIV-D-DYN-RTZ-01.S", + "rv64i_m/D/FDIV-D-DYN-RUP-01.S", + "rv64i_m/D/FDIV-D-RDN-01.S", + "rv64i_m/D/FDIV-D-RMM-01.S", + "rv64i_m/D/FDIV-D-RNE-01.S", + "rv64i_m/D/FDIV-D-RTZ-01.S", + "rv64i_m/D/FDIV-D-RUP-01.S", + "rv64i_m/D/FEQ-D-01.S", + "rv64i_m/D/FLD-01.S", + "rv64i_m/D/FLE-D-01.S", + "rv64i_m/D/FLT-D-01.S", + "rv64i_m/D/FMADD-D-DYN-RDN-01.S", + "rv64i_m/D/FMADD-D-DYN-RMM-01.S", + "rv64i_m/D/FMADD-D-DYN-RNE-01.S", + "rv64i_m/D/FMADD-D-DYN-RTZ-01.S", + "rv64i_m/D/FMADD-D-DYN-RUP-01.S", + "rv64i_m/D/FMADD-D-RDN-01.S", + "rv64i_m/D/FMADD-D-RMM-01.S", + "rv64i_m/D/FMADD-D-RNE-01.S", + "rv64i_m/D/FMADD-D-RTZ-01.S", + "rv64i_m/D/FMADD-D-RUP-01.S", + "rv64i_m/D/FMAX-D-01.S", + "rv64i_m/D/FMIN-D-01.S", + "rv64i_m/D/FMSUB-D-DYN-RDN-01.S", + "rv64i_m/D/FMSUB-D-DYN-RMM-01.S", + "rv64i_m/D/FMSUB-D-DYN-RNE-01.S", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01.S", + "rv64i_m/D/FMSUB-D-DYN-RUP-01.S", + "rv64i_m/D/FMSUB-D-RDN-01.S", + "rv64i_m/D/FMSUB-D-RMM-01.S", + "rv64i_m/D/FMSUB-D-RNE-01.S", + "rv64i_m/D/FMSUB-D-RTZ-01.S", + "rv64i_m/D/FMSUB-D-RUP-01.S", + "rv64i_m/D/FMUL-D-DYN-RDN-01.S", + "rv64i_m/D/FMUL-D-DYN-RMM-01.S", + "rv64i_m/D/FMUL-D-DYN-RNE-01.S", + "rv64i_m/D/FMUL-D-DYN-RTZ-01.S", + "rv64i_m/D/FMUL-D-DYN-RUP-01.S", + "rv64i_m/D/FMUL-D-RDN-01.S", + "rv64i_m/D/FMUL-D-RMM-01.S", + "rv64i_m/D/FMUL-D-RNE-01.S", + "rv64i_m/D/FMUL-D-RTZ-01.S", + "rv64i_m/D/FMUL-D-RUP-01.S", + "rv64i_m/D/FMV-D-X-01.S", + "rv64i_m/D/FMV-X-D-01.S", + "rv64i_m/D/FNMADD-D-DYN-RDN-01.S", + "rv64i_m/D/FNMADD-D-DYN-RMM-01.S", + "rv64i_m/D/FNMADD-D-DYN-RNE-01.S", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01.S", + "rv64i_m/D/FNMADD-D-DYN-RUP-01.S", + "rv64i_m/D/FNMADD-D-RDN-01.S", + "rv64i_m/D/FNMADD-D-RMM-01.S", + "rv64i_m/D/FNMADD-D-RNE-01.S", + "rv64i_m/D/FNMADD-D-RTZ-01.S", + "rv64i_m/D/FNMADD-D-RUP-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01.S", + "rv64i_m/D/FNMSUB-D-RDN-01.S", + "rv64i_m/D/FNMSUB-D-RMM-01.S", + "rv64i_m/D/FNMSUB-D-RNE-01.S", + "rv64i_m/D/FNMSUB-D-RTZ-01.S", + "rv64i_m/D/FNMSUB-D-RUP-01.S", + "rv64i_m/D/FSD-01.S", + "rv64i_m/D/FSGNJ-D-01.S", + "rv64i_m/D/FSGNJN-D-01.S", + "rv64i_m/D/FSGNJX-D-01.S", + "rv64i_m/D/FSQRT-D-DYN-RDN-01.S", + "rv64i_m/D/FSQRT-D-DYN-RMM-01.S", + "rv64i_m/D/FSQRT-D-DYN-RNE-01.S", + "rv64i_m/D/FSQRT-D-DYN-RTZ-01.S", + "rv64i_m/D/FSQRT-D-DYN-RUP-01.S", + "rv64i_m/D/FSQRT-D-RDN-01.S", + "rv64i_m/D/FSQRT-D-RMM-01.S", + "rv64i_m/D/FSQRT-D-RNE-01.S", + "rv64i_m/D/FSQRT-D-RTZ-01.S", + "rv64i_m/D/FSQRT-D-RUP-01.S", + "rv64i_m/D/FSUB-D-DYN-RDN-01.S", + "rv64i_m/D/FSUB-D-DYN-RMM-01.S", + "rv64i_m/D/FSUB-D-DYN-RNE-01.S", + "rv64i_m/D/FSUB-D-DYN-RTZ-01.S", + "rv64i_m/D/FSUB-D-DYN-RUP-01.S", + "rv64i_m/D/FSUB-D-RDN-01.S", + "rv64i_m/D/FSUB-D-RMM-01.S", + "rv64i_m/D/FSUB-D-RNE-01.S", + "rv64i_m/D/FSUB-D-RTZ-01.S", + "rv64i_m/D/FSUB-D-RUP-01.S" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01", - "rv64i_m/M/DIVU-01", - "rv64i_m/M/DIVUW-01", - "rv64i_m/M/DIVW-01", - "rv64i_m/M/MUL-01", - "rv64i_m/M/MULH-01", - "rv64i_m/M/MULHSU-01", - "rv64i_m/M/MULHU-01", - "rv64i_m/M/MULW-01", - "rv64i_m/M/REM-01", - "rv64i_m/M/REMU-01", - "rv64i_m/M/REMUW-01", - "rv64i_m/M/REMW-01" + "rv64i_m/M/DIV-01.S", + "rv64i_m/M/DIVU-01.S", + "rv64i_m/M/DIVUW-01.S", + "rv64i_m/M/DIVW-01.S", + "rv64i_m/M/MUL-01.S", + "rv64i_m/M/MULH-01.S", + "rv64i_m/M/MULHSU-01.S", + "rv64i_m/M/MULHU-01.S", + "rv64i_m/M/MULW-01.S", + "rv64i_m/M/REM-01.S", + "rv64i_m/M/REMU-01.S", + "rv64i_m/M/REMUW-01.S", + "rv64i_m/M/REMW-01.S" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01", - "rv64i_m/C/C-ADDI-01", - "rv64i_m/C/C-ADDI16SP-01", - "rv64i_m/C/C-ADDI4SPN-01", - "rv64i_m/C/C-ADDIW-01", - "rv64i_m/C/C-ADDW-01", - "rv64i_m/C/C-AND-01", - "rv64i_m/C/C-ANDI-01", - "rv64i_m/C/C-BEQZ-01", - "rv64i_m/C/C-BNEZ-01", - "rv64i_m/C/C-J-01", - "rv64i_m/C/C-JALR-01", - "rv64i_m/C/C-JR-01", - "rv64i_m/C/C-LD-01", - "rv64i_m/C/C-LDSP-01", - "rv64i_m/C/C-LI-01", - "rv64i_m/C/C-LUI-01", - "rv64i_m/C/C-LW-01", - "rv64i_m/C/C-LWSP-01", - "rv64i_m/C/C-MV-01", - "rv64i_m/C/C-OR-01", - "rv64i_m/C/C-SD-01", - "rv64i_m/C/C-SDSP-01", - "rv64i_m/C/C-SLLI-01", - "rv64i_m/C/C-SRAI-01", - "rv64i_m/C/C-SRLI-01", - "rv64i_m/C/C-SUB-01", - "rv64i_m/C/C-SUBW-01", - "rv64i_m/C/C-SW-01", - "rv64i_m/C/C-SWSP-01", - "rv64i_m/C/C-XOR-01", - "rv64i_m/C/I-C-EBREAK-01", - "rv64i_m/C/I-C-NOP-01" + "rv64i_m/C/C-ADD-01.S", + "rv64i_m/C/C-ADDI-01.S", + "rv64i_m/C/C-ADDI16SP-01.S", + "rv64i_m/C/C-ADDI4SPN-01.S", + "rv64i_m/C/C-ADDIW-01.S", + "rv64i_m/C/C-ADDW-01.S", + "rv64i_m/C/C-AND-01.S", + "rv64i_m/C/C-ANDI-01.S", + "rv64i_m/C/C-BEQZ-01.S", + "rv64i_m/C/C-BNEZ-01.S", + "rv64i_m/C/C-J-01.S", + "rv64i_m/C/C-JALR-01.S", + "rv64i_m/C/C-JR-01.S", + "rv64i_m/C/C-LD-01.S", + "rv64i_m/C/C-LDSP-01.S", + "rv64i_m/C/C-LI-01.S", + "rv64i_m/C/C-LUI-01.S", + "rv64i_m/C/C-LW-01.S", + "rv64i_m/C/C-LWSP-01.S", + "rv64i_m/C/C-MV-01.S", + "rv64i_m/C/C-OR-01.S", + "rv64i_m/C/C-SD-01.S", + "rv64i_m/C/C-SDSP-01.S", + "rv64i_m/C/C-SLLI-01.S", + "rv64i_m/C/C-SRAI-01.S", + "rv64i_m/C/C-SRLI-01.S", + "rv64i_m/C/C-SUB-01.S", + "rv64i_m/C/C-SUBW-01.S", + "rv64i_m/C/C-SW-01.S", + "rv64i_m/C/C-SWSP-01.S", + "rv64i_m/C/C-XOR-01.S", + "rv64i_m/C/I-C-EBREAK-01.S", + "rv64i_m/C/I-C-NOP-01.S" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01" + "rv64i_m/I/I-MISALIGN_JMP-01.S" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01", - "rv64i_m/I/ADD-01", - "rv64i_m/I/ADDI-01", - "rv64i_m/I/ADDIW-01", - "rv64i_m/I/ADDW-01", - "rv64i_m/I/AND-01", - "rv64i_m/I/ANDI-01", - "rv64i_m/I/AUIPC-01", - "rv64i_m/I/BEQ-01", - "rv64i_m/I/BGE-01", - "rv64i_m/I/BGEU-01", - "rv64i_m/I/BLT-01", - "rv64i_m/I/BLTU-01", - "rv64i_m/I/BNE-01", - "rv64i_m/I/I-DELAY_SLOTS-01", - "rv64i_m/I/I-EBREAK-01", - "rv64i_m/I/I-ECALL-01", - "rv64i_m/I/I-ENDIANESS-01", - "rv64i_m/I/I-IO-01", -// "rv64i_m/I/I-MISALIGN_JMP-01", - "rv64i_m/I/I-MISALIGN_LDST-01", - "rv64i_m/I/I-NOP-01", - "rv64i_m/I/I-RF_size-01", - "rv64i_m/I/I-RF_width-01", - "rv64i_m/I/I-RF_x0-01", - "rv64i_m/I/JAL-01", - "rv64i_m/I/JALR-01", - "rv64i_m/I/LB-01", - "rv64i_m/I/LBU-01", - "rv64i_m/I/LD-01", - "rv64i_m/I/LH-01", - "rv64i_m/I/LHU-01", - "rv64i_m/I/LUI-01", - "rv64i_m/I/LW-01", - "rv64i_m/I/LWU-01", - "rv64i_m/I/OR-01", - "rv64i_m/I/ORI-01", - "rv64i_m/I/SB-01", - "rv64i_m/I/SD-01", - "rv64i_m/I/SH-01", - "rv64i_m/I/SLL-01", - "rv64i_m/I/SLLI-01", - "rv64i_m/I/SLLIW-01", - "rv64i_m/I/SLLW-01", - "rv64i_m/I/SLT-01", - "rv64i_m/I/SLTI-01", - "rv64i_m/I/SLTIU-01", - "rv64i_m/I/SLTU-01", - "rv64i_m/I/SRA-01", - "rv64i_m/I/SRAI-01", - "rv64i_m/I/SRAIW-01", - "rv64i_m/I/SRAW-01", - "rv64i_m/I/SRL-01", - "rv64i_m/I/SRLI-01", - "rv64i_m/I/SRLIW-01", - "rv64i_m/I/SRLW-01", - "rv64i_m/I/SUB-01", - "rv64i_m/I/SUBW-01", - "rv64i_m/I/SW-01", - "rv64i_m/I/XOR-01", - "rv64i_m/I/XORI-01" + "rv64i_m/I/I-DELAY_SLOTS-01.S", + "rv64i_m/I/ADD-01.S", + "rv64i_m/I/ADDI-01.S", + "rv64i_m/I/ADDIW-01.S", + "rv64i_m/I/ADDW-01.S", + "rv64i_m/I/AND-01.S", + "rv64i_m/I/ANDI-01.S", + "rv64i_m/I/AUIPC-01.S", + "rv64i_m/I/BEQ-01.S", + "rv64i_m/I/BGE-01.S", + "rv64i_m/I/BGEU-01.S", + "rv64i_m/I/BLT-01.S", + "rv64i_m/I/BLTU-01.S", + "rv64i_m/I/BNE-01.S", + "rv64i_m/I/I-DELAY_SLOTS-01.S", + "rv64i_m/I/I-EBREAK-01.S", + "rv64i_m/I/I-ECALL-01.S", + "rv64i_m/I/I-ENDIANESS-01.S", + "rv64i_m/I/I-IO-01.S", +// "rv64i_m/I/I-MISALIGN_JMP-01.S", + "rv64i_m/I/I-MISALIGN_LDST-01.S", + "rv64i_m/I/I-NOP-01.S", + "rv64i_m/I/I-RF_size-01.S", + "rv64i_m/I/I-RF_width-01.S", + "rv64i_m/I/I-RF_x0-01.S", + "rv64i_m/I/JAL-01.S", + "rv64i_m/I/JALR-01.S", + "rv64i_m/I/LB-01.S", + "rv64i_m/I/LBU-01.S", + "rv64i_m/I/LD-01.S", + "rv64i_m/I/LH-01.S", + "rv64i_m/I/LHU-01.S", + "rv64i_m/I/LUI-01.S", + "rv64i_m/I/LW-01.S", + "rv64i_m/I/LWU-01.S", + "rv64i_m/I/OR-01.S", + "rv64i_m/I/ORI-01.S", + "rv64i_m/I/SB-01.S", + "rv64i_m/I/SD-01.S", + "rv64i_m/I/SH-01.S", + "rv64i_m/I/SLL-01.S", + "rv64i_m/I/SLLI-01.S", + "rv64i_m/I/SLLIW-01.S", + "rv64i_m/I/SLLW-01.S", + "rv64i_m/I/SLT-01.S", + "rv64i_m/I/SLTI-01.S", + "rv64i_m/I/SLTIU-01.S", + "rv64i_m/I/SLTU-01.S", + "rv64i_m/I/SRA-01.S", + "rv64i_m/I/SRAI-01.S", + "rv64i_m/I/SRAIW-01.S", + "rv64i_m/I/SRAW-01.S", + "rv64i_m/I/SRL-01.S", + "rv64i_m/I/SRLI-01.S", + "rv64i_m/I/SRLIW-01.S", + "rv64i_m/I/SRLW-01.S", + "rv64i_m/I/SUB-01.S", + "rv64i_m/I/SUBW-01.S", + "rv64i_m/I/SW-01.S", + "rv64i_m/I/XOR-01.S", + "rv64i_m/I/XORI-01.S" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01", - "rv32i_m/M/DIVU-01", - "rv32i_m/M/MUL-01", - "rv32i_m/M/MULH-01", - "rv32i_m/M/MULHSU-01", - "rv32i_m/M/MULHU-01", - "rv32i_m/M/REM-01", - "rv32i_m/M/REMU-01" + "rv32i_m/M/DIV-01.S", + "rv32i_m/M/DIVU-01.S", + "rv32i_m/M/MUL-01.S", + "rv32i_m/M/MULH-01.S", + "rv32i_m/M/MULHSU-01.S", + "rv32i_m/M/MULHU-01.S", + "rv32i_m/M/REM-01.S", + "rv32i_m/M/REMU-01.S" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01", - "rv32i_m/C/C-ADDI-01", - "rv32i_m/C/C-ADDI16SP-01", - "rv32i_m/C/C-ADDI4SPN-01", - "rv32i_m/C/C-AND-01", - "rv32i_m/C/C-ANDI-01", - "rv32i_m/C/C-BEQZ-01", - "rv32i_m/C/C-BNEZ-01", - "rv32i_m/C/C-J-01", - "rv32i_m/C/C-JAL-01", - "rv32i_m/C/C-JALR-01", - "rv32i_m/C/C-JR-01", - "rv32i_m/C/C-LI-01", - "rv32i_m/C/C-LUI-01", - "rv32i_m/C/C-LW-01", - "rv32i_m/C/C-LWSP-01", - "rv32i_m/C/C-MV-01", - "rv32i_m/C/C-OR-01", - "rv32i_m/C/C-SLLI-01", - "rv32i_m/C/C-SRAI-01", - "rv32i_m/C/C-SRLI-01", - "rv32i_m/C/C-SUB-01", - "rv32i_m/C/C-SW-01", - "rv32i_m/C/C-SWSP-01", - "rv32i_m/C/C-XOR-01", - "rv32i_m/C/I-C-EBREAK-01", - "rv32i_m/C/I-C-NOP-01" + "rv32i_m/C/C-ADD-01.S", + "rv32i_m/C/C-ADDI-01.S", + "rv32i_m/C/C-ADDI16SP-01.S", + "rv32i_m/C/C-ADDI4SPN-01.S", + "rv32i_m/C/C-AND-01.S", + "rv32i_m/C/C-ANDI-01.S", + "rv32i_m/C/C-BEQZ-01.S", + "rv32i_m/C/C-BNEZ-01.S", + "rv32i_m/C/C-J-01.S", + "rv32i_m/C/C-JAL-01.S", + "rv32i_m/C/C-JALR-01.S", + "rv32i_m/C/C-JR-01.S", + "rv32i_m/C/C-LI-01.S", + "rv32i_m/C/C-LUI-01.S", + "rv32i_m/C/C-LW-01.S", + "rv32i_m/C/C-LWSP-01.S", + "rv32i_m/C/C-MV-01.S", + "rv32i_m/C/C-OR-01.S", + "rv32i_m/C/C-SLLI-01.S", + "rv32i_m/C/C-SRAI-01.S", + "rv32i_m/C/C-SRLI-01.S", + "rv32i_m/C/C-SUB-01.S", + "rv32i_m/C/C-SW-01.S", + "rv32i_m/C/C-SWSP-01.S", + "rv32i_m/C/C-XOR-01.S", + "rv32i_m/C/I-C-EBREAK-01.S", + "rv32i_m/C/I-C-NOP-01.S" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01" + "rv32i_m/I/I-MISALIGN_JMP-01.S" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01", - "rv32i_m/I/ADDI-01", - "rv32i_m/I/AND-01", - "rv32i_m/I/ANDI-01", - "rv32i_m/I/AUIPC-01", - "rv32i_m/I/BEQ-01", - "rv32i_m/I/BGE-01", - "rv32i_m/I/BGEU-01", - "rv32i_m/I/BLT-01", - "rv32i_m/I/BLTU-01", - "rv32i_m/I/BNE-01", - "rv32i_m/I/I-DELAY_SLOTS-01", - "rv32i_m/I/I-EBREAK-01", - "rv32i_m/I/I-ECALL-01", - "rv32i_m/I/I-ENDIANESS-01", - "rv32i_m/I/I-IO-01", -// "rv32i_m/I/I-MISALIGN_JMP-01", - "rv32i_m/I/I-MISALIGN_LDST-01", - "rv32i_m/I/I-NOP-01", - "rv32i_m/I/I-RF_size-01", - "rv32i_m/I/I-RF_width-01", - "rv32i_m/I/I-RF_x0-01", - "rv32i_m/I/JAL-01", - "rv32i_m/I/JALR-01", - "rv32i_m/I/LB-01", - "rv32i_m/I/LBU-01", - "rv32i_m/I/LH-01", - "rv32i_m/I/LHU-01", - "rv32i_m/I/LUI-01", - "rv32i_m/I/LW-01", - "rv32i_m/I/OR-01", - "rv32i_m/I/ORI-01", - "rv32i_m/I/SB-01", - "rv32i_m/I/SH-01", - "rv32i_m/I/SLL-01", - "rv32i_m/I/SLLI-01", - "rv32i_m/I/SLT-01", - "rv32i_m/I/SLTI-01", - "rv32i_m/I/SLTIU-01", - "rv32i_m/I/SLTU-01", - "rv32i_m/I/SRA-01", - "rv32i_m/I/SRAI-01", - "rv32i_m/I/SRL-01", - "rv32i_m/I/SRLI-01", - "rv32i_m/I/SUB-01", - "rv32i_m/I/SW-01", - "rv32i_m/I/XOR-01", - "rv32i_m/I/XORI-01" + "rv32i_m/I/ADD-01.S", + "rv32i_m/I/ADDI-01.S", + "rv32i_m/I/AND-01.S", + "rv32i_m/I/ANDI-01.S", + "rv32i_m/I/AUIPC-01.S", + "rv32i_m/I/BEQ-01.S", + "rv32i_m/I/BGE-01.S", + "rv32i_m/I/BGEU-01.S", + "rv32i_m/I/BLT-01.S", + "rv32i_m/I/BLTU-01.S", + "rv32i_m/I/BNE-01.S", + "rv32i_m/I/I-DELAY_SLOTS-01.S", + "rv32i_m/I/I-EBREAK-01.S", + "rv32i_m/I/I-ECALL-01.S", + "rv32i_m/I/I-ENDIANESS-01.S", + "rv32i_m/I/I-IO-01.S", +// "rv32i_m/I/I-MISALIGN_JMP-01.S", + "rv32i_m/I/I-MISALIGN_LDST-01.S", + "rv32i_m/I/I-NOP-01.S", + "rv32i_m/I/I-RF_size-01.S", + "rv32i_m/I/I-RF_width-01.S", + "rv32i_m/I/I-RF_x0-01.S", + "rv32i_m/I/JAL-01.S", + "rv32i_m/I/JALR-01.S", + "rv32i_m/I/LB-01.S", + "rv32i_m/I/LBU-01.S", + "rv32i_m/I/LH-01.S", + "rv32i_m/I/LHU-01.S", + "rv32i_m/I/LUI-01.S", + "rv32i_m/I/LW-01.S", + "rv32i_m/I/OR-01.S", + "rv32i_m/I/ORI-01.S", + "rv32i_m/I/SB-01.S", + "rv32i_m/I/SH-01.S", + "rv32i_m/I/SLL-01.S", + "rv32i_m/I/SLLI-01.S", + "rv32i_m/I/SLT-01.S", + "rv32i_m/I/SLTI-01.S", + "rv32i_m/I/SLTIU-01.S", + "rv32i_m/I/SLTU-01.S", + "rv32i_m/I/SRA-01.S", + "rv32i_m/I/SRAI-01.S", + "rv32i_m/I/SRL-01.S", + "rv32i_m/I/SRLI-01.S", + "rv32i_m/I/SUB-01.S", + "rv32i_m/I/SW-01.S", + "rv32i_m/I/XOR-01.S", + "rv32i_m/I/XORI-01.S" }; @@ -1326,6 +1326,53 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; +string arch64b[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S", + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/rol-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh3add.uw-01.S", + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/zext.h_64-01.S" +}; string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py new file mode 100644 index 00000000..c9681aee --- /dev/null +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -0,0 +1,13 @@ +import os + +os.chdir("/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src") + +filenames = [] + +for testname in os.listdir(): + print( +f"""cd /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/link.ld -I /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/ -I /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature=/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; +riscv64-unknown-elf-elf2hex --bit-width 64 --input /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile +extractFunctionRadix.sh /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump +""") + diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 8037ad6f..e6bfc72e 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,7 +1,7 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDCSUZicsr_Zifencei -# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs +# ISA: RV64IMAFDCSUZicsr_Zifencei + ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From a7237baa87e3de82c4b813ae7aa96ea5a6215b20 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 10 Feb 2023 10:37:06 -0800 Subject: [PATCH 027/183] fixed small errors to get regression to run with bit manip supported. --- src/ieu/bmu/clmul.sv | 19 ++++++++----------- src/ieu/bmu/popcnt.sv | 10 +++++++--- src/ieu/bmu/zbs.sv | 2 +- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 5557283f..a83d014a 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -34,20 +34,17 @@ module clmul #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ClmulResult); // ZBS result logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products + // Note: only generates the bottom WIDTH bits of the carryless multiply. + // To get the high bits or the reversed bits, the inputs can be shifted and reversed + // as they are in zbc where this is instantiated - genvar i,j; - for (i=1; i Date: Sat, 11 Feb 2023 00:30:56 +0000 Subject: [PATCH 028/183] changed python file to use WALLY env variable --- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py index c9681aee..78879962 100644 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -1,13 +1,15 @@ +#Kip Macsai-Goren and Kevin Kim import os -os.chdir("/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src") +WALLY = os.getenv("WALLY") +os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") filenames = [] for testname in os.listdir(): print( -f"""cd /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/link.ld -I /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/ -I /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature=/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -riscv64-unknown-elf-elf2hex --bit-width 64 --input /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile -extractFunctionRadix.sh /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump +f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; +riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile +extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump """) From 6d4f1dd9285208f4f8317b44461d20e0c681226d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 11:08:11 -0800 Subject: [PATCH 029/183] updated python script to generate bash file --- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py index 78879962..e7ec07d3 100644 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -1,15 +1,19 @@ #Kip Macsai-Goren and Kevin Kim +#Purpose is to manually make the B extension tests import os +f = open("genBScript.sh", "w") WALLY = os.getenv("WALLY") os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") filenames = [] +lines = "" for testname in os.listdir(): - print( -f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; + lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump -""") +""" +f.write(lines) +f.close() From d7c540d047ddf6118ef0908329ebedb80ada8310 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 12:14:00 -0800 Subject: [PATCH 030/183] edited rv64i convig to support bit manipulation --- config/rv64i/wally-config.vh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 90d7b404..b865da26 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -145,10 +145,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 From 76bc1b5999a085ada770c57181643c431a4fa6e1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 19:16:13 -0800 Subject: [PATCH 031/183] clmul passes lint --- src/ieu/bmu/clmul.sv | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index a83d014a..3b7daadb 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -37,14 +37,26 @@ module clmul #(parameter WIDTH=32) ( // Note: only generates the bottom WIDTH bits of the carryless multiply. // To get the high bits or the reversed bits, the inputs can be shifted and reversed // as they are in zbc where this is instantiated - + /* genvar i; for (i=0; i Date: Sat, 11 Feb 2023 19:19:38 -0800 Subject: [PATCH 032/183] popcnt passes lint --- src/ieu/bmu/popcnt.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 57f8c9e3..456e0774 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -31,12 +31,18 @@ module popcnt #(parameter WIDTH = 32) ( logic [$clog2(WIDTH):0] sum; - always_comb begin + /*always_comb begin sum = 0; for (int i=0;i Date: Sat, 11 Feb 2023 20:22:42 -0800 Subject: [PATCH 033/183] fixed lints in cnt --- src/ieu/bmu/cnt.sv | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index b0c44e06..dd72cd5d 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -48,25 +48,26 @@ module cnt #(parameter WIDTH = 32) ( //NOTE: signal widths can be decreased always_comb begin //clz input select mux - case({B,W64}) - 5'b00000_0: lzcA = A; //clz - 5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw - 5'b00001_0: lzcA = revA; //ctz - 5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + case({B[4:0],W64}) + 6'b00000_0: lzcA = A; //clz + 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw + 6'b00001_0: lzcA = revA; //ctz + 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw endcase //cpop select mux - case ({B,W64}) - 5'b00010_0: popcntA = A; - 5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; + case ({B[4:0],W64}) + 6'b00010_0: popcntA = A; + 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; endcase end end else begin + //rv32 assign popcntA = A; always_comb begin //clz input slect mux - case(B) + case(B[4:0]) 5'b00000: lzcA = A; 5'b00001: lzcA = revA; endcase From 61b46e0639d2c871b605d3283f2a2053843326bd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 20:25:34 -0800 Subject: [PATCH 034/183] fixed byte unit lints --- src/ieu/bmu/byte.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 17ab652f..6a076b7d 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -38,7 +38,7 @@ module byteUnit #(parameter WIDTH=32) ( for (i=0;i Date: Sat, 11 Feb 2023 20:41:52 -0800 Subject: [PATCH 035/183] zbb, zbs, cnt lint fixes --- src/ieu/bmu/cnt.sv | 3 +++ src/ieu/bmu/zbb.sv | 4 +--- src/ieu/bmu/zbs.sv | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index dd72cd5d..430d2d38 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -53,12 +53,14 @@ module cnt #(parameter WIDTH = 32) ( 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw 6'b00001_0: lzcA = revA; //ctz 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + default: lzcA = A; endcase //cpop select mux case ({B[4:0],W64}) 6'b00010_0: popcntA = A; 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; + default: popcntA = A; endcase end end @@ -70,6 +72,7 @@ module cnt #(parameter WIDTH = 32) ( case(B[4:0]) 5'b00000: lzcA = A; 5'b00001: lzcA = revA; + default: lzcA = A; endcase end end diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 98996f3b..e469fcef 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -58,15 +58,13 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin - case ({Funct7, Funct3, B}) + case ({Funct7, Funct3, B[4:0]}) 15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110000_001_00000: ZBBResult = czResult; 15'b0110000_001_00010: ZBBResult = cpopResult; 15'b0110000_001_00001: ZBBResult = czResult; - 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0000100_100_00000: ZBBResult = zexthResult; 15'b0110000_001_00100: ZBBResult = sextbResult; 15'b0110000_001_00101: ZBBResult = sexthResult; diff --git a/src/ieu/bmu/zbs.sv b/src/ieu/bmu/zbs.sv index 740c684b..214d6e2c 100644 --- a/src/ieu/bmu/zbs.sv +++ b/src/ieu/bmu/zbs.sv @@ -43,7 +43,7 @@ module zbs #(parameter WIDTH=32) ( assign InvResult = A ^ BMask; assign ClrResult = A & ~BMask; assign SetResult = A | BMask; - assign ExtResult = |(A & BMask); + assign ExtResult = {{(WIDTH-1){1'b0}},{|(A & BMask)}}; always_comb begin casez ({Funct7, Funct3}) From 5f08322e99cc51c6fdd8706f5fd2499784090db8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 21:13:10 -0800 Subject: [PATCH 036/183] lint fixes --- src/ieu/alu.sv | 24 ++++++++++-------------- src/ieu/bmu/popcnt.sv | 12 +++--------- src/ieu/bmu/zbb.sv | 7 ++++--- 3 files changed, 17 insertions(+), 26 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 15a19f55..97cda872 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -57,14 +57,14 @@ module alu #(parameter WIDTH=32) ( // Addition if (`ZBB_SUPPORTED) always_comb begin - case({Funct7, Funct3}) - 10'b0010000_010: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add - 10'b0010000_100: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add - 10'b0010000_110: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add - 10'b0000100_000: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw - 10'b0010000_010: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw - 10'b0010000_100: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw - 10'b0010000_110: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw + case({Funct7, Funct3, W64}) + 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add + 11'b0010000_100_0: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add + 11'b0010000_110_0: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add + 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw + 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw + 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw default: CondShiftA = A; endcase @@ -76,13 +76,9 @@ module alu #(parameter WIDTH=32) ( endcase casez ({Funct7, Funct3}) - 10'b0110000_101: Rotate = 1'b1; 10'b011000?_101: Rotate = 1'b1; 10'b000010?_001: Rotate = 1'b0; 10'b0110000_001: Rotate = 1'b1; - 10'b0110000_101: Rotate = 1'b1; - 10'b0110000_001: Rotate = 1'b1; - 10'b0110000_101: Rotate = 1'b1; default: Rotate = 1'b0; endcase end @@ -126,12 +122,12 @@ module alu #(parameter WIDTH=32) ( endcase if (`ZBS_SUPPORTED) - zbs zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); + zbs #(WIDTH) zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); else assign ZBSResult = 0; if (`ZBB_SUPPORTED) - zbb zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); + zbb #(WIDTH) zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 456e0774..c82476a6 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -31,20 +31,14 @@ module popcnt #(parameter WIDTH = 32) ( logic [$clog2(WIDTH):0] sum; - /*always_comb begin + always_comb begin sum = 0; for (int i=0;i Date: Sat, 11 Feb 2023 21:22:33 -0800 Subject: [PATCH 037/183] simulation runs-- clmul doesn't pass lint with xor tree --- src/ieu/bmu/clmul.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 3b7daadb..f1917f55 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -47,14 +47,16 @@ module clmul #(parameter WIDTH=32) ( */ genvar i,j; for (i=1; i Date: Mon, 13 Feb 2023 13:49:35 -0800 Subject: [PATCH 038/183] alu add.uw needs w64 to be false --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 97cda872..dd7b1bb1 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -61,7 +61,7 @@ module alu #(parameter WIDTH=32) ( 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add 11'b0010000_100_0: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add 11'b0010000_110_0: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add - 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 11'b0000100_000_0: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw From 12911440d0152591b603f2f026492cdbbe14821a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 13:49:46 -0800 Subject: [PATCH 039/183] edited controller so that add.uw passes tests --- src/ieu/controller.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index c4afa86c..4d8ba0c6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -161,7 +161,10 @@ module controller( else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction + if (Funct7D == 7'b0000100 & `ZBA_SUPPORTED) + ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // adduw + else + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal From 29d03dbfc70e99fd5e598d171fdac4d3799b472c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 14:00:06 -0800 Subject: [PATCH 040/183] ALU configurability changes -stuff that was ZBA supported was in ZBB so I changed that --- src/ieu/alu.sv | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index dd7b1bb1..49ab5404 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -55,7 +55,7 @@ module alu #(parameter WIDTH=32) ( // Addition - if (`ZBB_SUPPORTED) + if (`ZBA_SUPPORTED) always_comb begin case({Funct7, Funct3, W64}) 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add @@ -67,7 +67,12 @@ module alu #(parameter WIDTH=32) ( 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw default: CondShiftA = A; endcase + else begin + assign CondShiftA = A; + end + if (`ZBB_SUPPORTED) + always_comb begin case ({Funct7,Funct3}) 10'b0100000_111: InvB = 1'b1; //andn 10'b0100000_110: InvB = 1'b1; //orn @@ -83,8 +88,8 @@ module alu #(parameter WIDTH=32) ( endcase end else begin - assign CondShiftA = A; - assign InvB = 1'b0; + InvB = 1'b0; + Rotate = 1'b0; end assign CondInvB = (SubArith | InvB) ? ~B : B; From 27223a05e2f3b4ca6ee120e25fb60321495ee49c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 14:01:51 -0800 Subject: [PATCH 041/183] ALU lint fixes --- src/ieu/alu.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 49ab5404..911fc087 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -67,6 +67,7 @@ module alu #(parameter WIDTH=32) ( 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw default: CondShiftA = A; endcase + end else begin assign CondShiftA = A; end @@ -88,8 +89,8 @@ module alu #(parameter WIDTH=32) ( endcase end else begin - InvB = 1'b0; - Rotate = 1'b0; + assign InvB = 1'b0; + assign Rotate = 1'b0; end assign CondInvB = (SubArith | InvB) ? ~B : B; From 29abec24096c84526dcf29caea58665bb2102cfa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 16:36:17 -0800 Subject: [PATCH 042/183] Shadd instructions pass tests --- src/ieu/alu.sv | 21 +++++++++++++-------- src/ieu/controller.sv | 30 ++++++++++++++++++++---------- 2 files changed, 33 insertions(+), 18 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 911fc087..7e06ee6e 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -49,27 +49,32 @@ module alu #(parameter WIDTH=32) ( logic Asign, Bsign; // Sign bits of A, B logic InvB; // Is Inverted Operand Instruction (ZBB) logic Rotate; // Is rotate operation + logic ZbaAdd; // Is ZBA Add Operation // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + + // Addition if (`ZBA_SUPPORTED) always_comb begin + ZbaAdd = (Funct7 == 7'b0010000 | Funct7 == 7'b0000100); case({Funct7, Funct3, W64}) - 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add - 11'b0010000_100_0: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add - 11'b0010000_110_0: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add - 11'b0000100_000_0: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 11'b0010000_010_0: CondShiftA = {A[WIDTH-2:0], {1'b0}}; //sh1add + 11'b0010000_100_0: CondShiftA = {A[WIDTH-3:0], {2'b00}}; //sh2add + 11'b0010000_110_0: CondShiftA = {A[WIDTH-4:0], {3'b000}}; //sh3add + 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw - 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw - 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw + 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b00}}; //sh2add.uw + 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b000}}; //sh3add.uw default: CondShiftA = A; endcase end else begin assign CondShiftA = A; + assign ZbaAdd = 0; end if (`ZBB_SUPPORTED) @@ -116,7 +121,7 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + if (~ALUOp | ZbaAdd) FullResult = Sum; // Always add for ALUOp = 0 (address generation) and ZBA else casez (Funct3) // Otherwise check Funct3 3'b000: FullResult = Sum; // add or sub 3'b?01: FullResult = Shift; // sll, sra, or srl @@ -137,7 +142,7 @@ module alu #(parameter WIDTH=32) ( else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + if (WIDTH == 64) assign Result = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign Result = FullResult; endmodule diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4d8ba0c6..1188fe0a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED)) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -161,8 +161,8 @@ module controller( else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else - if (Funct7D == 7'b0000100 & `ZBA_SUPPORTED) - ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // adduw + if ((Funct7D == 7'b0000100 | Funct7D == 7'b0010000) & `ZBA_SUPPORTED) + ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // adduw, sh1adduw, sh2adduw, sh3adduw else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches @@ -193,13 +193,23 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra - assign sltD = (Funct3D == 3'b010); - assign sltuD = (Funct3D == 3'b011); - assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi - assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu - assign ALUControlD = {W64D, SubArithD, ALUOpD}; + if (`ZBA_SUPPORTED) begin + // ALU Decoding is more comprehensive when ZBA is supported + assign sltD = (Funct3D == 3'b010 & OpD == 7'b0010011); + assign sltuD = (Funct3D == 3'b011 & OpD == 7'b0010011); + assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi + assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign ALUControlD = {W64D, SubArithD, ALUOpD}; + end else begin + // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra + assign sltD = (Funct3D == 3'b010); + assign sltuD = (Funct3D == 3'b011); + assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi + assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign ALUControlD = {W64D, SubArithD, ALUOpD}; + end // Fences // Ordinary fence is presently a nop From 84ca2cab9cb80715482d5e08583c73f9f4d41328 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 16:57:05 -0800 Subject: [PATCH 043/183] controller handles bclr --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 1188fe0a..c6879ffd 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED)) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED) | (Funct7D == 7'b0100100 & `ZBS_SUPPORTED)) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide From fd46e0080cbbb28218aaff2afde5661dc4ba1f10 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 17:38:00 -0800 Subject: [PATCH 044/183] added ALU result select mux for B instructions --- src/ieu/alu.sv | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 7e06ee6e..7b381a0f 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -40,7 +40,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. logic [WIDTH-1:0] ZBBResult, ZBSResult; - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA, ALUResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -142,7 +142,21 @@ module alu #(parameter WIDTH=32) ( else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign Result = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign Result = FullResult; + if (WIDTH == 64) assign ALUResult = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; + + if (`ZBB_SUPPORTED | `ZBA_SUPPORTED | `ZBS_SUPPORTED | `ZBC_SUPPORTED) begin + always_comb + casez({Funct7}) + 7'b010010?: Result = ZBSResult; + 7'b001010?: Result = ZBSResult; + default: Result = ALUResult; + endcase + end else begin + assign Result = ALUResult; + end + + + endmodule From 405bbcc6a403df6917e27a7cd22c3b4d4340fe1c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 14 Feb 2023 10:40:29 -0800 Subject: [PATCH 045/183] added critical rsync command to python script and builds I-ext tests -rsync copies the stuff from riscof_work to work/riscv-arch-test - --- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py index e7ec07d3..4a728a47 100644 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -6,14 +6,29 @@ f = open("genBScript.sh", "w") WALLY = os.getenv("WALLY") os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") -filenames = [] lines = "" +#BUILDS B TESTS for testname in os.listdir(): lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile -extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump +rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; +riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile; +extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump; """ + +os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/I/src") + +#BUILDS I TESTS +for testname in os.listdir(): + lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; +rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; +riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.memfile; +extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.objdump; +""" + + + + f.write(lines) f.close() From 8e371864e4a9402c9f67d2eb9272109dbb8a8819 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 14 Feb 2023 13:06:31 -0800 Subject: [PATCH 046/183] reverted back to I tests working --- src/ieu/alu.sv | 6 ++-- src/ieu/bmu/clmul.sv.bak | 64 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 3 deletions(-) create mode 100644 src/ieu/bmu/clmul.sv.bak diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 97cda872..daf60f23 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -69,9 +69,9 @@ module alu #(parameter WIDTH=32) ( endcase case ({Funct7,Funct3}) - 10'b0100000_111: InvB = 1'b1; //andn - 10'b0100000_110: InvB = 1'b1; //orn - 10'b0100000_100: InvB = 1'b1; //xnor + 10'b0100000_111: InvB = 1'b0; //andn + 10'b0100000_110: InvB = 1'b0; //orn + 10'b0100000_100: InvB = 1'b0; //xnor default: InvB = 1'b0; endcase diff --git a/src/ieu/bmu/clmul.sv.bak b/src/ieu/bmu/clmul.sv.bak new file mode 100644 index 00000000..36f1dea2 --- /dev/null +++ b/src/ieu/bmu/clmul.sv.bak @@ -0,0 +1,64 @@ +/////////////////////////////////////////// +// clmul.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 1 February 2023 +// Modified: +// +// Purpose: Carry-Less multiplication top-level unit +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module clmul #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] ClmulResult); // ZBS result + + logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products + // Note: only generates the bottom WIDTH bits of the carryless multiply. + // To get the high bits or the reversed bits, the inputs can be shifted and reversed + // as they are in zbc where this is instantiated + /* + genvar i; + for (i=0; i Date: Tue, 14 Feb 2023 13:07:03 -0800 Subject: [PATCH 047/183] removed unncessary stuff --- src/ieu/bmu/clmul.sv.bak | 64 ---------------------------------------- 1 file changed, 64 deletions(-) delete mode 100644 src/ieu/bmu/clmul.sv.bak diff --git a/src/ieu/bmu/clmul.sv.bak b/src/ieu/bmu/clmul.sv.bak deleted file mode 100644 index 36f1dea2..00000000 --- a/src/ieu/bmu/clmul.sv.bak +++ /dev/null @@ -1,64 +0,0 @@ -/////////////////////////////////////////// -// clmul.sv -// -// Written: Kevin Kim and Kip Macsai-Goren -// Created: 1 February 2023 -// Modified: -// -// Purpose: Carry-Less multiplication top-level unit -// -// Documentation: RISC-V System on Chip Design Chapter *** -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module clmul #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - output logic [WIDTH-1:0] ClmulResult); // ZBS result - - logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products - // Note: only generates the bottom WIDTH bits of the carryless multiply. - // To get the high bits or the reversed bits, the inputs can be shifted and reversed - // as they are in zbc where this is instantiated - /* - genvar i; - for (i=0; i Date: Sat, 11 Feb 2023 21:22:33 -0800 Subject: [PATCH 048/183] git --- src/ieu/alu.sv | 109 ++++++++---------------------------------- src/ieu/controller.sv | 39 +++++---------- 2 files changed, 32 insertions(+), 116 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index ddead973..6c52432d 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -32,78 +32,31 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, + input logic [6:0] Funct7, // Funct7 from execute stage input logic [2:0] Funct3, // With ALUControl, indicates operation to perform output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands - // CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. + // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] ZBBResult, ZBSResult; - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA, ALUResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic InvB; // Is Inverted Operand Instruction (ZBB) - logic Rotate; // Is rotate operation - logic ZbaAdd; // Is ZBA Add Operation + logic rotate; // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; - - - // Addition - if (`ZBA_SUPPORTED) - always_comb begin - ZbaAdd = (Funct7 == 7'b0010000 | Funct7 == 7'b0000100); - case({Funct7, Funct3, W64}) - 11'b0010000_010_0: CondShiftA = {A[WIDTH-2:0], {1'b0}}; //sh1add - 11'b0010000_100_0: CondShiftA = {A[WIDTH-3:0], {2'b00}}; //sh2add - 11'b0010000_110_0: CondShiftA = {A[WIDTH-4:0], {3'b000}}; //sh3add - 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw - 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw - 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b00}}; //sh2add.uw - 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b000}}; //sh3add.uw - default: CondShiftA = A; - endcase - end - else begin - assign CondShiftA = A; - assign ZbaAdd = 0; - end - - if (`ZBB_SUPPORTED) - always_comb begin - case ({Funct7,Funct3}) - 10'b0100000_111: InvB = 1'b0; //andn - 10'b0100000_110: InvB = 1'b0; //orn - 10'b0100000_100: InvB = 1'b0; //xnor - default: InvB = 1'b0; - endcase - - casez ({Funct7, Funct3}) - 10'b011000?_101: Rotate = 1'b1; - 10'b000010?_001: Rotate = 1'b0; - 10'b0110000_001: Rotate = 1'b1; - default: Rotate = 1'b0; - endcase - end - else begin - assign InvB = 1'b0; - assign Rotate = 1'b0; - end - - assign CondInvB = (SubArith | InvB) ? ~B : B; - - assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + assign CondInvB = SubArith ? ~B : B; + assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Rotate(Rotate), .Y(Shift)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -121,42 +74,18 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb - if (~ALUOp | ZbaAdd) FullResult = Sum; // Always add for ALUOp = 0 (address generation) and ZBA - else casez (Funct3) // Otherwise check Funct3 - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ CondInvB; // xor - 3'b110: FullResult = A | CondInvB; // or - 3'b111: FullResult = A & CondInvB; // and + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (Funct3) // Otherwise check Funct3 + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor + 3'b110: FullResult = A | B; // or + 3'b111: FullResult = A & B; // and endcase - if (`ZBS_SUPPORTED) - zbs #(WIDTH) zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); - else assign ZBSResult = 0; - - - if (`ZBB_SUPPORTED) - zbb #(WIDTH) zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); - else assign ZBBResult = 0; - // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; - - if (`ZBB_SUPPORTED | `ZBA_SUPPORTED | `ZBS_SUPPORTED | `ZBC_SUPPORTED) begin - always_comb - casez({Funct7}) - 7'b010010?: Result = ZBSResult; - 7'b001010?: Result = ZBSResult; - default: Result = ALUResult; - endcase - end else begin - assign Result = ALUResult; - end - - - -endmodule - + if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign Result = FullResult; +endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index c6879ffd..aff09482 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED) | (Funct7D == 7'b0100100 & `ZBS_SUPPORTED)) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -161,10 +161,7 @@ module controller( else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else - if ((Funct7D == 7'b0000100 | Funct7D == 7'b0010000) & `ZBA_SUPPORTED) - ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // adduw, sh1adduw, sh2adduw, sh3adduw - else - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal @@ -193,23 +190,13 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - if (`ZBA_SUPPORTED) begin - // ALU Decoding is more comprehensive when ZBA is supported - assign sltD = (Funct3D == 3'b010 & OpD == 7'b0010011); - assign sltuD = (Funct3D == 3'b011 & OpD == 7'b0010011); - assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi - assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu - assign ALUControlD = {W64D, SubArithD, ALUOpD}; - end else begin - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra - assign sltD = (Funct3D == 3'b010); - assign sltuD = (Funct3D == 3'b011); - assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi - assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu - assign ALUControlD = {W64D, SubArithD, ALUOpD}; - end + // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra + assign sltD = (Funct3D == 3'b010); + assign sltuD = (Funct3D == 3'b011); + assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi + assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign ALUControlD = {W64D, SubArithD, ALUOpD}; // Fences // Ordinary fence is presently a nop @@ -228,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE @@ -264,4 +251,4 @@ module controller( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD)); -endmodule +endmodule \ No newline at end of file From 9cec59ea2c268d54adbe349bfcac6f5e8cb7c47c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 14 Feb 2023 16:06:10 -0800 Subject: [PATCH 049/183] controller passes funct7 from decode to execute --- src/ieu/controller.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index aff09482..5f6e33f1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -215,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE From 5426dd61842f6d41fd79a2666c884b5973d1565a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 09:13:10 -0800 Subject: [PATCH 050/183] added ALUResult Signal --- src/ieu/alu.sv | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 6c52432d..9d945ef8 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -39,13 +39,13 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate results + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B logic rotate; // Extract control signals from ALUControl. @@ -86,6 +86,10 @@ module alu #(parameter WIDTH=32) ( endcase // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign Result = FullResult; + if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; + + if (`ZBC_SUPPORTED) begin + + end else assign Result = ALUResult; endmodule \ No newline at end of file From cf8392cbd8122ad8ebf4cd588338804c6028c1c2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 09:35:07 -0800 Subject: [PATCH 051/183] continued ZBC integration into ALU --- src/ieu/alu.sv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9d945ef8..088eefb5 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -39,7 +39,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -90,6 +90,16 @@ module alu #(parameter WIDTH=32) ( else assign ALUResult = FullResult; if (`ZBC_SUPPORTED) begin - + zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + end + + if (`ZBC_SUPPORTED) begin + always_comb + case ({Funct7, Funct3}) + 10'b0000101_001: Result = ZBCResult; + 10'b0000101_011: Result = ZBCResult; + 10'b0000101_010: Result = ZBCResult; + default: Result = ALUResult; + endcase end else assign Result = ALUResult; endmodule \ No newline at end of file From 6ac54a180ea09d5547943e3648a32de970dd3604 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:37:09 -0800 Subject: [PATCH 052/183] zbc and carry-less multiply work properly --- src/ieu/bmu/clmul.sv | 41 +++++++++++++++-------------------------- src/ieu/bmu/zbc.sv | 34 ++++++++++++++-------------------- 2 files changed, 29 insertions(+), 46 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index f1917f55..280c3fbd 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// clmul.sv +// clmul.sv (carry-less multiplier) // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 @@ -30,35 +30,24 @@ `include "wally-config.vh" module clmul #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result - logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products - // Note: only generates the bottom WIDTH bits of the carryless multiply. - // To get the high bits or the reversed bits, the inputs can be shifted and reversed - // as they are in zbc where this is instantiated - /* - genvar i; - for (i=0; i CLMUL -> MUX -> RESULT - //alternate could have CLMUL * 3 -> MUX -> MUX always_comb begin casez (Funct3) 3'b001: begin //clmul - X = A; - Y = B; + x = A; + y = B; end 3'b011: begin //clmulh - X = {RevA[WIDTH-2:0], {1'b0}}; - Y = {{1'b0}, RevB[WIDTH-2:0]}; + x = {RevA[WIDTH-2:0], {1'b0}}; + y = {{1'b0}, RevB[WIDTH-2:0]}; end 3'b010: begin //clmulr - X = {A[WIDTH-2:0], {1'b0}}; - Y = B; + x = RevA; + y = RevB; end default: begin - X = 0; - Y = 0; + x = 0; + y = 0; end endcase end - clmul clm(.A(X), .B(Y), .ClmulResult(ClmulResult)); - bitreverse brClmulResult(.a(ClmulResult), .b(RevClmulResult)); + clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); + bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3 == 3'b011) ? RevClmulResult : ClmulResult; + assign ZBCResult = (Funct3 == 3'b011 || Funct3 == 3'b010) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From 068ddc3e0dc4cdc4240ce2af24ceb6661813562a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:38:12 -0800 Subject: [PATCH 053/183] controller forwards funct7 - started the bmu controll register --- src/ieu/controller.sv | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 5f6e33f1..51f27ef7 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0000101 & `ZBC_SUPPORTED)) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -215,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE @@ -239,6 +239,9 @@ module controller( {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE}, {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM}); + // BMU control register + flopenrc#(7) controlregBMU(clk, reset, FlushM, ~StallM, {Funct7D}, {Funct7E}); + // Writeback stage pipeline control register flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, {RegWriteM, ResultSrcM, IntDivM}, From aad4d136032a6cc6e0ecd72308461b7790f5e6e7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:39:37 -0800 Subject: [PATCH 054/183] zbc configurability and select mux --- src/ieu/alu.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 088eefb5..3026765b 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -89,11 +89,12 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; - if (`ZBC_SUPPORTED) begin + if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); - end + end else assign ZBCResult = 0; + - if (`ZBC_SUPPORTED) begin + if (`ZBC_SUPPORTED) begin : zbcdecoder always_comb case ({Funct7, Funct3}) 10'b0000101_001: Result = ZBCResult; From 465aad372a1a5069740e71f66952b847ca8c81ce Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:42:32 -0800 Subject: [PATCH 055/183] added comments to zbc units --- src/ieu/alu.sv | 2 ++ src/ieu/bmu/clmul.sv | 3 +-- src/ieu/bmu/zbc.sv | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3026765b..60bcf552 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -89,11 +89,13 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; + //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; + //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU if (`ZBC_SUPPORTED) begin : zbcdecoder always_comb case ({Funct7, Funct3}) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 280c3fbd..46893573 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -33,8 +33,7 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result - logic [(WIDTH*WIDTH)-1:0] s; - logic [WIDTH-1:0] intial; + logic [(WIDTH*WIDTH)-1:0] s; // intermediary signals for carry-less multiply integer i; integer j; diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 400aaf53..580cdacc 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -38,10 +38,10 @@ module zbc #(parameter WIDTH=32) ( logic [WIDTH-1:0] RevA, RevB; logic [WIDTH-1:0] x,y; - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); + //NOTE: Optimize this when doing decoder stuff. always_comb begin casez (Funct3) 3'b001: begin //clmul From 25c0811d3d778fbb6f42f5af3db770779a5c2366 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:50:45 -0800 Subject: [PATCH 056/183] Added ALUSelect signal into datapath, ieu, controller --- src/ieu/controller.sv | 18 +++++++++++++----- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 5 +++-- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 51f27ef7..7e054b5d 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -46,6 +46,7 @@ module controller( output logic [2:0] ALUControlE, // ALU operation to perform output logic ALUSrcAE, ALUSrcBE, // ALU operands output logic ALUResultSrcE, // Selects result to pass on to Memory stage + output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field output logic [6:0] Funct7E, // Instruction's funct7 field @@ -90,6 +91,7 @@ module controller( logic BranchD, BranchE; // Branch instruction logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic [2:0] ALUControlD; // Determines ALU operation + logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR @@ -102,7 +104,7 @@ module controller( logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu - logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions + logic subD, sraD, sltD, sltuD, bextD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -195,9 +197,18 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & bextD)); // TRUE for R-type subtracts and sra, slt, sltu assign ALUControlD = {W64D, SubArithD, ALUOpD}; + if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .bextD, .StallE, .FlushE, .Funct7E, .ALUSelectE); + end else begin: bitmanipi + assign ALUSelectD = Funct3D; + assign ALUSelectE = Funct3E; + assign bextD = 1'b0; + assign Funct7E = 7'b0; + end + // Fences // Ordinary fence is presently a nop // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented @@ -239,9 +250,6 @@ module controller( {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE}, {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM}); - // BMU control register - flopenrc#(7) controlregBMU(clk, reset, FlushM, ~StallM, {Funct7D}, {Funct7E}); - // Writeback stage pipeline control register flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, {RegWriteM, ResultSrcM, IntDivM}, diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index f715a5d5..3cf12b37 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -15,6 +15,7 @@ module datapath ( input logic [2:0] ALUControlE, // Indicate operation ALU performs input logic ALUSrcAE, ALUSrcBE, // ALU operands input logic ALUResultSrcE, // Selects result to pass on to Memory stage + input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) @@ -81,7 +82,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index f7a20152..b8ee90d0 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -79,6 +79,7 @@ module ieu ( logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage + logic [2:0] ALUSelectE; // ALU select mux signal logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction @@ -95,7 +96,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -103,7 +104,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, + .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From 9128ac5409ac8ae5399b93ecaf4bffac508ce8a0 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:50:59 -0800 Subject: [PATCH 057/183] added BMU controll --- src/ieu/bmu/bmuctrl.sv | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 src/ieu/bmu/bmuctrl.sv diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv new file mode 100644 index 00000000..3b93cd14 --- /dev/null +++ b/src/ieu/bmu/bmuctrl.sv @@ -0,0 +1,86 @@ +/////////////////////////////////////////// +// controller.sv +// +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Created: 9 January 2021 +// Modified: +// +// Purpose: Top level controller module +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// NOTE: DO we want to make this XLEN parameterized? +module bmuctrl( + input logic clk, reset, + // Decode stage control signals + input logic StallD, FlushD, // Stall, flush Decode stage + input logic [31:0] InstrD, // Instruction in Decode stage + output logic [2:0] ALUSelectD, // ALU Mux select signal + output logic bextD, // Indicates if bit extract instruction + // Execute stage control signals + input logic StallE, FlushE, // Stall, flush Execute stage + output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) + output logic [2:0] ALUSelectE +); + + logic [6:0] OpD; // Opcode in Decode stage + logic [2:0] Funct3D; // Funct3 field in Decode stage + logic [6:0] Funct7D; // Funct7 field in Decode stage + logic [4:0] Rs1D; // Rs1 source register in Decode stage + + `define BMUCTRLW 4 + + logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals + + + // Extract fields + assign OpD = InstrD[6:0]; + assign Funct3D = InstrD[14:12]; + assign Funct7D = InstrD[31:25]; + assign Rs1D = InstrD[19:15]; + + // Main Instruction Decoder + always_comb + casez({OpD, Funct7D, Funct3D}) + // ALUSelect_bextD + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclri + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bexti + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binvi + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bseti + 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclr + 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bext + 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binv + 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bset + 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0; // sra, srl, sll + default: BMUControlsD = {Funct3D, {1'b0}};// not B instruction or shift + endcase + + // Unpack Control Signals + + assign {ALUSelectD,bextD} = BMUControlsD; + + + + // BMU Execute stage pipieline control register + flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD}, {Funct7E, ALUSelectE}); +endmodule \ No newline at end of file From 9ab8183e8007002d0507ebb67bc35c5f924b2b2d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:51:10 -0800 Subject: [PATCH 058/183] alu handles ALU select instead of funct3 --- src/ieu/alu.sv | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 60bcf552..2ef9df8a 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -32,8 +32,9 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, // Funct7 from execute stage - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform + input logic [2:0] ALUSelect, // ALU mux select signal + input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) + input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -46,7 +47,7 @@ module alu #(parameter WIDTH=32) ( logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic rotate; + logic Rotate; // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -56,7 +57,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(rotate)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(1'b0)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -75,7 +76,7 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (Funct3) // Otherwise check Funct3 + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect 3'b000: FullResult = Sum; // add or sub 3'b?01: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt From 256d362e0d74ab9def58d80753358d2894ae3c17 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:51:28 -0800 Subject: [PATCH 059/183] comment formatting --- src/ieu/shifter.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 15c7b411..e898edde 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -32,7 +32,7 @@ module shifter ( input logic [`XLEN-1:0] A, // Source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits From 505f3bf42f72dbb27ced6352b872fa707682504f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:52:54 -0800 Subject: [PATCH 060/183] comments --- src/ieu/bmu/bmuctrl.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 3b93cd14..9f0e2b76 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // controller.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu -// Created: 9 January 2021 +// Written: Kevin Kim +// Created: 16 February 2023 // Modified: // // Purpose: Top level controller module From 81cb00aaee102829ed75d546f16f1b7f9b253826 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:53:14 -0800 Subject: [PATCH 061/183] comments --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 9f0e2b76..2b0bb63f 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -5,7 +5,7 @@ // Created: 16 February 2023 // Modified: // -// Purpose: Top level controller module +// Purpose: Top level B instrution controller module // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // From ec2421ead477d9acb7921baaf7a98057f872d354 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 08:21:55 -0800 Subject: [PATCH 062/183] added BSelect Signal - BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction --- src/ieu/alu.sv | 18 +++++++++++------- src/ieu/bmu/bmuctrl.sv | 33 +++++++++++++++++---------------- src/ieu/controller.sv | 9 +++++---- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 5 +++-- 5 files changed, 38 insertions(+), 30 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 2ef9df8a..e69335ce 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,6 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal + input logic [3:0] BSelect, // One-Hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result @@ -40,15 +41,18 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B logic Rotate; + + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], CondMaskB); + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 2b0bb63f..7c95f06c 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,19 +36,20 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal - output logic bextD, // Indicates if bit extract instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) - output logic [2:0] ALUSelectE + output logic [2:0] ALUSelectE, + output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs1D; // Rs1 source register in Decode stage + logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction decode stage - `define BMUCTRLW 4 + `define BMUCTRLW 7 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -62,25 +63,25 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_bextD - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclri - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bexti - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binvi - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bseti - 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclr - 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bext - 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binv - 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bset - 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0; // sra, srl, sll - default: BMUControlsD = {Funct3D, {1'b0}};// not B instruction or shift + // ALUSelect_zbsD + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr + 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext + 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv + 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset + 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,bextD} = BMUControlsD; + assign {ALUSelectD,BSelectD} = BMUControlsD; // BMU Execute stage pipieline control register - flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD}, {Funct7E, ALUSelectE}); + flopenrc#(14) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD, BSelectD}, {Funct7E, ALUSelectE, BSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 7e054b5d..0ed3d727 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -56,6 +56,7 @@ module controller( output logic JumpE, // jump instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) + output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -104,7 +105,7 @@ module controller( logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu - logic subD, sraD, sltD, sltuD, bextD; // Indicates if is one of these instructions + logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -197,15 +198,15 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & bextD)); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectE[0] & ALUSelectD == 3'b101)); // TRUE for R-type subtracts and sra, slt, sltu, bext assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .bextD, .StallE, .FlushE, .Funct7E, .ALUSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign bextD = 1'b0; + assign BSelectE = 4'b000; assign Funct7E = 7'b0; end diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 3cf12b37..604eab8d 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -18,6 +18,7 @@ module datapath ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) + input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -82,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index b8ee90d0..ba1d8756 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -83,6 +83,7 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -96,7 +97,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -105,7 +106,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From 890c54bc0ba6bec992a298453930084a4cb3f904 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 08:22:13 -0800 Subject: [PATCH 063/183] added alu changes to previous commit --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index e69335ce..9311c1bc 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,7 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal - input logic [3:0] BSelect, // One-Hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result From ee3a520a1fb6c9c27f2df648df25afa209ed944c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 09:51:49 -0800 Subject: [PATCH 064/183] alu looks at BSelect, added BSelect one hot signal --- src/ieu/alu.sv | 61 ++++++++++++++++++++++++++++-------------- src/ieu/bmu/bmuctrl.sv | 3 ++- src/ieu/controller.sv | 7 ++--- 3 files changed, 47 insertions(+), 24 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9311c1bc..3bb6ba34 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -42,6 +42,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results + logic [WIDTH-1:0] MaskB; logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -51,13 +52,16 @@ module alu #(parameter WIDTH=32) ( logic Rotate; - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], CondMaskB); + if (`ZBS_SUPPORTED) begin: zbsdec + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); + assign CondMaskB = (BSelect[0]) ? MaskB : B; + end else assign CondMaskB = B; // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; // Addition - assign CondInvB = SubArith ? ~B : B; + assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts @@ -78,17 +82,35 @@ module alu #(parameter WIDTH=32) ( assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; // Select appropriate ALU Result - always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor - 3'b110: FullResult = A | B; // or - 3'b111: FullResult = A & B; // and - endcase + if (`ZBS_SUPPORTED) begin + always_comb + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect + 3'b000: FullResult = Sum; // add or sub + 3'b001: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor, binv + 3'b110: FullResult = A | B; // or, bset + 3'b111: FullResult = A & B; // and, bclr + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & B)}};// bext + endcase + end + else begin + always_comb + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor + 3'b110: FullResult = A | B; // or + 3'b111: FullResult = A & B; // and + endcase + + end + // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; @@ -99,15 +121,14 @@ module alu #(parameter WIDTH=32) ( zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; - //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU - if (`ZBC_SUPPORTED) begin : zbcdecoder + if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder always_comb - case ({Funct7, Funct3}) - 10'b0000101_001: Result = ZBCResult; - 10'b0000101_011: Result = ZBCResult; - 10'b0000101_010: Result = ZBCResult; - default: Result = ALUResult; + case (BSelect) + //ZBA_ZBB_ZBC_ZBS + 4'b0001: Result = FullResult; + 4'b0010: Result = ZBCResult; + default: Result = ALUResult; endcase end else assign Result = ALUResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 7c95f06c..8b051e73 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,6 +36,7 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal + output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) @@ -47,7 +48,6 @@ module bmuctrl( logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs1D; // Rs1 source register in Decode stage - logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction decode stage `define BMUCTRLW 7 @@ -73,6 +73,7 @@ module bmuctrl( 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + 17'b0110011_0000101_???: BMUControlsD = `BMUCTRLW'b001_0010; // ZBC instruction default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0ed3d727..e24a5e5f 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -116,6 +116,7 @@ module controller( logic FenceD, FenceE, FenceM; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction + logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage // Extract fields @@ -152,7 +153,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0000101 & `ZBC_SUPPORTED)) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (BSelectD[1] | BSelectD[0])) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -198,11 +199,11 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectE[0] & ALUSelectD == 3'b101)); // TRUE for R-type subtracts and sra, slt, sltu, bext + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectD[0] && (ALUSelectD == 3'b101 | ALUSelectD == 3'b111))); // TRUE for R-type subtracts and sra, slt, sltu, bext assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, BSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, .BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From b9434700491aa8fa7f99fdce6b4b48b3b9d0ca61 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 17 Feb 2023 09:51:55 -0800 Subject: [PATCH 065/183] Modified arch64 tests to remove floating point and double tests from hanging make --- tests/riscof/Makefile | 6 +++--- tests/riscof/spike/spike_rv64gc_isa.yaml | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index d963e4f0..00b7c3ba 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,8 +8,8 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 -#all: root wally32 wally64 -all: root arch32 wally32 wally32e arch64 wally64 +all: root arch64 +#all: root arch32 wally32 wally32e arch64 wally64 root: mkdir -p $(work_dir) @@ -25,7 +25,7 @@ arch32: rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed" arch64: - riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" # Also copy F and D tests to RV64 rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index e6bfc72e..ad745f47 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zifencei - ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV64IMACSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000014112D + reset-val: 0x8000000000141105 rv32: accessible: false rv64: From 02bc03af42c3a80c58962ee710430378ff6d97ee Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 17 Feb 2023 09:57:56 -0800 Subject: [PATCH 066/183] fixed makefile for 32 bit arch tests, restored original make for all others --- tests/riscof/Makefile | 6 +++--- tests/riscof/spike/spike_rv32gc_isa.yaml | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 00b7c3ba..24b499d1 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,8 +8,8 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 -all: root arch64 -#all: root arch32 wally32 wally32e arch64 wally64 +#all: root wally32 wally64 +all: root arch32 wally32 wally32e arch64 wally64 root: mkdir -p $(work_dir) @@ -25,7 +25,7 @@ arch32: rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed" arch64: - riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" # Also copy F and D tests to RV64 rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 478bbe56..4a593524 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zifencei -# ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + #ISA: RV32IMAFDCZicsr_Zifencei + ISA: RV32IMACZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x4000112D + reset-val: 0x40001105 rv32: accessible: true mxl: From bb79b57cc1534060514e624bdaa3dbfe7c4a9a31 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 11:02:07 -0800 Subject: [PATCH 067/183] alu bug fix - condmaskb piped in correctly instead of b --- src/ieu/alu.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3bb6ba34..420cc0a3 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -90,10 +90,10 @@ module alu #(parameter WIDTH=32) ( 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor, binv - 3'b110: FullResult = A | B; // or, bset - 3'b111: FullResult = A & B; // and, bclr - 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & B)}};// bext + 3'b100: FullResult = A ^ CondMaskB; // xor, binv + 3'b110: FullResult = A | CondMaskB; // or, bset + 3'b111: FullResult = A & CondInvB; // and, bclr + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase end else begin From 0bab3bec3dfdbc88e2e7cf8d8a330bc6c01cdf3f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 11:16:29 -0800 Subject: [PATCH 068/183] bctrl bug fix - bctrl decodes shift immediate instructions properly --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 8b051e73..4e0f1efc 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -72,7 +72,7 @@ module bmuctrl( 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset - 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli 17'b0110011_0000101_???: BMUControlsD = `BMUCTRLW'b001_0010; // ZBC instruction default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From 9bf11471aa9084eb58260276502eb979ed5527cf Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 12:54:08 -0800 Subject: [PATCH 069/183] bmuctrl checks for illegal zbs-style instructions --- src/ieu/bmu/bmuctrl.sv | 45 +++++++++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4e0f1efc..4217f643 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -63,18 +63,39 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_zbsD - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti - 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr - 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext - 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv - 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli - 17'b0110011_0000101_???: BMUControlsD = `BMUCTRLW'b001_0010; // ZBC instruction - default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift + // ALUSelect_BSelect + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_0100101_001: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b111_0001; // bclri (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + 17'b0010011_0100101_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b101_0001; // bexti (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + 17'b0010011_0110101_001: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b100_0001; // binvi (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + 17'b0010011_0010101_001: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b110_0001; // bseti + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010; // ZBC instruction + 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add + 17'b0110011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase // Unpack Control Signals From fcae58fcc720b356f2b5ed009cde89f022e9b976 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 16:12:09 -0800 Subject: [PATCH 070/183] removed Funct7 in Execute Stage --- src/ieu/alu.sv | 1 - src/ieu/bmu/bmuctrl.sv | 3 +-- src/ieu/controller.sv | 4 +--- src/ieu/datapath.sv | 3 +-- src/ieu/ieu.sv | 5 ++--- 5 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 420cc0a3..41891bd2 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -34,7 +34,6 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4217f643..8782d982 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -39,7 +39,6 @@ module bmuctrl( output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage - output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) output logic [2:0] ALUSelectE, output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding ); @@ -105,5 +104,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(14) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD, BSelectD}, {Funct7E, ALUSelectE, BSelectE}); + flopenrc#(7) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD}, {ALUSelectE, BSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e24a5e5f..6996b455 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -49,7 +49,6 @@ module controller( output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field - output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation @@ -203,12 +202,11 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, .BSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b000; - assign Funct7E = 7'b0; end // Fences diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 604eab8d..b81e43ee 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -9,7 +9,6 @@ module datapath ( input logic [`XLEN-1:0] PCE, // PC in Execute stage input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage - input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic [2:0] ALUControlE, // Indicate operation ALU performs @@ -83,7 +82,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index ba1d8756..236178bc 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -74,7 +74,6 @@ module ieu ( logic [2:0] ImmSrcD; // Select type of immediate extension logic [1:0] FlagsE; // Comparison flags ({eq, lt}) - logic [6:0] Funct7E; // Instruction's funct7 field in execute stage logic [2:0] ALUControlE; // ALU control indicates function to perform logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage @@ -98,14 +97,14 @@ module ieu ( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, - .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, + .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From 750882455fcb3d7438b303a20fddd71dae2dcc2b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 16:44:16 -0800 Subject: [PATCH 071/183] controller supports ZBA instructions --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 6996b455..cbc7ffde 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -152,7 +152,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (BSelectD[1] | BSelectD[0])) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide From cd92d6e5d1def986be1632c5c1c23a5bf3b50b94 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 20:14:13 -0800 Subject: [PATCH 072/183] bmuctrl handles .uw instructions --- src/ieu/bmu/bmuctrl.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 8782d982..e25d8ffc 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -93,7 +93,11 @@ module bmuctrl( 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add - 17'b0110011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From e2d90a9422c7494ce11fb9e0c10df0b51629c125 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 20:14:47 -0800 Subject: [PATCH 073/183] more elegant ZBA logic in controller --- src/ieu/controller.sv | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index cbc7ffde..192e16e4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -105,6 +105,7 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions + logic bclrD, bextD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -159,7 +160,7 @@ module controller( else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64) + 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide @@ -193,12 +194,25 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i + if (`ZBA_SUPPORTED) begin + // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb + assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); + end else begin + assign sltD = (Funct3D == 3'b010); + end + + if (`ZBS_SUPPORTED) begin + assign bclrD = (ALUSelectD == 3'b111 & BSelectD[0]); + assign bextD = (ALUSelectD == 3'b101 & BSelectD[0]); + end else begin + assign bclrD = 1'b0; + assign bextD = 1'b0; + end // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra - assign sltD = (Funct3D == 3'b010); - assign sltuD = (Funct3D == 3'b011); + assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectD[0] && (ALUSelectD == 3'b101 | ALUSelectD == 3'b111))); // TRUE for R-type subtracts and sra, slt, sltu, bext + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD))); // TRUE for R-type subtracts and sra, slt, sltu assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags @@ -206,7 +220,7 @@ module controller( end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign BSelectE = 4'b000; + assign BSelectE = 4'b0000; end // Fences From 50ec6baa0766e68290d03a19d35ae8d27ffdaa41 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 20:15:12 -0800 Subject: [PATCH 074/183] added zero extend, pre-shift mux to ALU --- src/ieu/alu.sv | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 41891bd2..d880e653 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -40,8 +40,11 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results - logic [WIDTH-1:0] MaskB; + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results + logic [WIDTH-1:0] MaskB; // BitMask of B + logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux + logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux + logic [WIDTH-1:0] CondZextA; // Result of Zero Extend A select mux logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -56,12 +59,28 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; + if (`ZBA_SUPPORTED) begin: zbamuxes + // Zero Extend Mux + if (WIDTH == 64) begin + assign CondZextA = (BSelect[3] & (W64 | Funct3[0])) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? + end else assign CondZextA = A; + + // Pre-Shift Mux + always_comb + case (Funct3[2:1] & {2{BSelect[3]}}) + 2'b00: CondShiftA = CondZextA; + 2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}}; // sh1add + 2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}}; // sh2add + 2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add + endcase + end else assign CondShiftA = A; + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; - assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(1'b0)); @@ -120,13 +139,14 @@ module alu #(parameter WIDTH=32) ( zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; - //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU + // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS 4'b0001: Result = FullResult; 4'b0010: Result = ZBCResult; + 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. default: Result = ALUResult; endcase end else assign Result = ALUResult; From 4a52b570023d63514b599d281404e38738e64a6f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:57:19 -0800 Subject: [PATCH 075/183] bmuctrl supports some rotates --- src/ieu/bmu/bmuctrl.sv | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e25d8ffc..6d16036b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -98,6 +98,15 @@ module bmuctrl( 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add.uw 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv32) + 17'b0010011_0110001_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From c353378da817f034f75409c3de0a01fbfa777294 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:57:34 -0800 Subject: [PATCH 076/183] controller supports some rotates --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 192e16e4..9c48b26e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -153,14 +153,14 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBB_SUPPORTED & BSelectD[2]) | (`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3])) & `XLEN == 64) + 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3]) | (`ZBB_SUPPORTED & BSelectD[2])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide From 182b27dfc83d69378b6c1ad791bb5c556b4e4799 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:58:26 -0800 Subject: [PATCH 077/183] shifter bug fix - roli not passing unless I keep the MSB (instead of inverting) of truncated offset --- src/ieu/shifter.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index e898edde..feb346ef 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -36,7 +36,7 @@ module shifter ( output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount // Handle left and right shifts with a funnel shifter. // For RV32, only 32-bit shifts are needed. @@ -129,9 +129,11 @@ module shifter ( // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; + if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; + else assign CondOffsetTrunc = offset; // Funnel operation - assign zshift = z >> offset; + assign zshift = z >> CondOffsetTrunc; assign Y = zshift[`XLEN-1:0]; endmodule From 92c0d3a4ede09dfad55f6e7caf6b8355920cf4cd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:58:49 -0800 Subject: [PATCH 078/183] configured shifter in alu --- src/ieu/alu.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index d880e653..fa5df225 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -75,6 +75,10 @@ module alu #(parameter WIDTH=32) ( endcase end else assign CondShiftA = A; + if (`ZBB_SUPPORTED) begin: rotatelogic + assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? + end else assign Rotate = 1'b0; + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -83,7 +87,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(1'b0)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign From 7780cbd47a46ee045aa5ed0e9cbff9a7a3b075be Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 16:26:16 -0800 Subject: [PATCH 079/183] bmuctrl handles roriw --- src/ieu/bmu/bmuctrl.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 6d16036b..816b5dc3 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -107,6 +107,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv64) else BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + 17'b0011011_0110000_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b001_0100; // roriw + else + BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From 9203b0cc2f5e7e962ed5bc69cf10deeecda88bba Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:44:14 -0800 Subject: [PATCH 080/183] began ZBB integration into ieu --- src/ieu/alu.sv | 7 +++- src/ieu/bmu/bmuctrl.sv | 92 ++++++++++++++++++++++-------------------- src/ieu/bmu/cnt.sv | 10 +++-- src/ieu/bmu/zbb.sv | 16 ++++---- src/ieu/controller.sv | 6 ++- src/ieu/datapath.sv | 3 +- src/ieu/ieu.sv | 7 ++-- 7 files changed, 80 insertions(+), 61 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index fa5df225..69602059 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -34,13 +34,14 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -142,6 +143,10 @@ module alu #(parameter WIDTH=32) ( if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; + + if (`ZBB_SUPPORTED) begin: zbb + zbb #(WIDTH) ZBB(.A(A), .B(B), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + end else assign ZBBResult = 0; // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 816b5dc3..e7ddd14e 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -37,18 +37,20 @@ module bmuctrl( input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, - output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [2:0] ZBBSelectE // ZBB mux select signal ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage - logic [4:0] Rs1D; // Rs1 source register in Decode stage + logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 7 + `define BMUCTRLW 10 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -57,70 +59,74 @@ module bmuctrl( assign OpD = InstrD[6:0]; assign Funct3D = InstrD[14:12]; assign Funct7D = InstrD[31:25]; - assign Rs1D = InstrD[19:15]; + assign Rs2D = InstrD[24:20]; // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001; // bseti + BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010; // ZBC instruction - 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv32) + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0110000_001: if (Rs2D[2]) + BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction + else + BMUControlsD = `BMUCTRLW'b000_0100_100; // sign ext instruction - default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD} = BMUControlsD; // BMU Execute stage pipieline control register - flopenrc#(7) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD}, {ALUSelectE, BSelectE}); + flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 430d2d38..a0bee434 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -31,12 +31,14 @@ `include "wally-config.vh" module cnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, B, // Operands input logic W64, // Indicates word operation - output logic [WIDTH-1:0] czResult, // count zeros result - output logic [WIDTH-1:0] cpopResult);// population count result + output logic [WIDTH-1:0] CntResult // count result +); //count instructions + logic [WIDTH-1:0] czResult; // count zeros result + logic [WIDTH-1:0] cpopResult; // population count result logic [WIDTH-1:0] lzcA, popcntA; logic [WIDTH-1:0] revA; @@ -81,4 +83,6 @@ module cnt #(parameter WIDTH = 32) ( lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult)); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult)); + assign CntResult = (B[1]) ? cpopResult : czResult; + endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 296d15d5..58cfccc5 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,16 +32,14 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform - input logic [6:0] Funct7, // Indicates operation to perform input logic W64, // Indicates word operation + input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result - // count results - logic [WIDTH-1:0] czResult; // count zeros result (lzc or tzc) - logic [WIDTH-1:0] cpopResult; // population count result + // count result + logic [WIDTH-1:0] CntResult; // byte results logic [WIDTH-1:0] OrcBResult; @@ -52,14 +50,14 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] sextbResult; // sign extend byte result logic [WIDTH-1:0] zexthResult; // zero extend halfword result - cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .czResult(czResult), .cpopResult(cpopResult)); + cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); ext #(WIDTH) ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin - case ({Funct7, Funct3, B[4:0]}) - 15'b0010100_101_00111: ZBBResult = OrcBResult; + case (ZBBSelect) + /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110000_001_00000: ZBBResult = czResult; @@ -67,7 +65,7 @@ module zbb #(parameter WIDTH=32) ( 15'b0110000_001_00001: ZBBResult = czResult; 15'b0000100_100_00000: ZBBResult = zexthResult; 15'b0110000_001_00100: ZBBResult = sextbResult; - 15'b0110000_001_00101: ZBBResult = sexthResult; + 15'b0110000_001_00101: ZBBResult = sexthResult;*/ default: ZBBResult = {(WIDTH){1'b0}}; endcase end diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 9c48b26e..70d5f598 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -56,6 +56,7 @@ module controller( output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction + output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -117,6 +118,7 @@ module controller( logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage + logic [2:0] ZBBSelectD; // ZBB Mux Select Signal // Extract fields @@ -216,11 +218,13 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b0000; + assign BSelectD = 4'b0000; + assign ZBBSelectE = 3'b000; end // Fences diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index b81e43ee..ff25309f 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -18,6 +18,7 @@ module datapath ( input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelectE, // ZBB mux select signal output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -82,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 236178bc..2a23dcd5 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -82,7 +82,8 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction - logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [2:0] ZBBSelectE; // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -96,7 +97,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .ZBBSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -105,7 +106,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From e47cc222a6afddd4ea37dd0a983a7aec0dd28078 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:50:36 -0800 Subject: [PATCH 081/183] removed redundant decode logic in bmuctrl --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e7ddd14e..0d56e329 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -91,7 +91,6 @@ module bmuctrl( 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction - 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add @@ -100,6 +99,7 @@ module bmuctrl( 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + // ZBB 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror From bec2905ee508a254c3d801f66112c03db3211257 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:56:54 -0800 Subject: [PATCH 082/183] rotate instructions now handled in ZBB unit --- src/ieu/alu.sv | 3 ++- src/ieu/bmu/zbb.sv | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 69602059..164a2810 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -145,7 +145,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -156,6 +156,7 @@ module alu #(parameter WIDTH=32) ( 4'b0001: Result = FullResult; 4'b0010: Result = ZBCResult; 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. + 4'b0100: Result = ZBBResult; default: Result = ALUResult; endcase end else assign Result = ALUResult; diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 58cfccc5..02591dd4 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,6 +32,7 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result @@ -57,6 +58,7 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) + 3'b111: ZBBResult = ALUResult; /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From 84ddb6fb54c9e4902b9380c831a890930b7dff8f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:57:10 -0800 Subject: [PATCH 083/183] updated comments in bmuctrl --- src/ieu/bmu/bmuctrl.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 0d56e329..0d3516a8 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -64,7 +64,8 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect + // ALUSelect_BSelect_ZBBSelect + // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) @@ -90,7 +91,9 @@ module bmuctrl( 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + // ZBC 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + // ZBA 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add From 9760f0ccfd510f7ca78e07286b8ea6c9979720f1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:11:50 -0800 Subject: [PATCH 084/183] fixed bmuctrl decode bug --- src/ieu/bmu/bmuctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 0d3516a8..b45a13ff 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -117,9 +117,10 @@ module bmuctrl( else BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction + BMUControlsD = `BMUCTRLW'b000_0100_100; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_100; // sign ext instruction + BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase From 6d60268240eb63d1812c12399411e7db905509d1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:12:17 -0800 Subject: [PATCH 085/183] zbb handles count instructions --- src/ieu/bmu/zbb.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 02591dd4..1be801f4 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -58,7 +58,8 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; + 3'b111: ZBBResult = ALUResult; // rotate + 3'b000: ZBBResult = CntResult; // count /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From 5c563bef43d406a7d7ca0a60f55788a43c52d0b4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:12:30 -0800 Subject: [PATCH 086/183] fixed ctlzw bug in count unit --- src/ieu/bmu/cnt.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index a0bee434..540d5e91 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -54,7 +54,7 @@ module cnt #(parameter WIDTH = 32) ( 6'b00000_0: lzcA = A; //clz 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw 6'b00001_0: lzcA = revA; //ctz - 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + 6'b00001_1: lzcA = {revA[63:32],{32{1'b1}}}; //ctzw default: lzcA = A; endcase From ba968ed95e43099136601376fe86e71a871631d1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:32:40 -0800 Subject: [PATCH 087/183] added logic to handle sign/zero extend instructions --- src/ieu/bmu/bmuctrl.sv | 10 +++++++++- src/ieu/bmu/ext.sv | 16 ++++++++++++---- src/ieu/bmu/zbb.sv | 7 +++---- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b45a13ff..ef021db0 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -121,8 +121,16 @@ module bmuctrl( else BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction + 17'b0111011_0000100_100: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0110011_0000100_100: if (`XLEN == 32) + BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase // Unpack Control Signals diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index c9f845e7..05cb24c0 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -31,13 +31,21 @@ `include "wally-config.vh" module ext #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, // Operand - output logic [WIDTH-1:0] sexthResult, // sign extend halfword result - output logic [WIDTH-1:0] sextbResult, // sign extend byte result - output logic [WIDTH-1:0] zexthResult); // zero extend halfword result + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] ExtResult); // Extend Result + logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]}; assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; + + always_comb + case({B[2],B[0]}) + 2'b00: ExtResult = zexthResult; + 2'b10: ExtResult = sextbResult; + 2'b11: ExtResult = sexthResult; + default: ExtResult = 0; + endcase + endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1be801f4..d5198d48 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -47,19 +47,18 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] Rev8Result; // sign/zero extend results - logic [WIDTH-1:0] sexthResult; // sign extend halfword result - logic [WIDTH-1:0] sextbResult; // sign extend byte result - logic [WIDTH-1:0] zexthResult; // zero extend halfword result + logic [WIDTH-1:0] ExtResult; // sign/zero extend result cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); - ext #(WIDTH) ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); + ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) 3'b111: ZBBResult = ALUResult; // rotate 3'b000: ZBBResult = CntResult; // count + 3'b100: ZBBResult = ExtResult; // sign/zero extend /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From 27581f8d28d1ac2e1d2a86ff2b45dfda63c9b594 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:57:07 -0800 Subject: [PATCH 088/183] alu and controllers handle andn, orn, xnor --- src/ieu/alu.sv | 4 ++-- src/ieu/bmu/bmuctrl.sv | 3 +++ src/ieu/bmu/zbb.sv | 2 +- src/ieu/controller.sv | 14 +++++++++++++- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 164a2810..97400f44 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -113,8 +113,8 @@ module alu #(parameter WIDTH=32) ( 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ CondMaskB; // xor, binv - 3'b110: FullResult = A | CondMaskB; // or, bset + 3'b100: FullResult = A ^ CondInvB; // xor, xnor, binv + 3'b110: FullResult = A | CondInvB; // or, orn, bset 3'b111: FullResult = A & CondInvB; // and, bclr 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ef021db0..abaf3655 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -129,6 +129,9 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) else BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index d5198d48..bacbef81 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -56,7 +56,7 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; // rotate + 3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn 3'b000: ZBBResult = CntResult; // count 3'b100: ZBBResult = ExtResult; // sign/zero extend /*15'b0010100_101_00111: ZBBResult = OrcBResult; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 70d5f598..74d0e4f1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -107,6 +107,7 @@ module controller( logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic bclrD, bextD; // Indicates if is one of these instructions + logic andnD, ornD, xnorD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -210,11 +211,22 @@ module controller( assign bclrD = 1'b0; assign bextD = 1'b0; end + + if (`ZBB_SUPPORTED) begin + assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]); + assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]); + assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]); + end else begin + assign andnD = 0; + assign ornD = 0; + assign xnorD = 0; + end + // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD))); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags From 888f4318bc62db6da7db7a1b2d8879a85f139e99 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 21:06:55 -0800 Subject: [PATCH 089/183] controlleres and zbb handle byte instructions --- src/ieu/bmu/bmuctrl.sv | 9 +++++++++ src/ieu/bmu/byte.sv | 8 +++++--- src/ieu/bmu/zbb.sv | 6 +++--- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index abaf3655..ab275047 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -132,6 +132,15 @@ module bmuctrl( 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor + 17'b0010011_0110101_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0110100_101: if (`XLEN == 32) + BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv32) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 6a076b7d..efd43d84 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" module byteUnit #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, // Operands - output logic [WIDTH-1:0] OrcBResult, // OrcB result - output logic [WIDTH-1:0] Rev8Result); // Rev8 result + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] ByteResult); // rev8, orcb result + logic [WIDTH-1:0] OrcBResult, Rev8Result; genvar i; for (i=0;i Date: Sat, 18 Feb 2023 22:12:55 -0800 Subject: [PATCH 090/183] B DONE (for now) - datapath passes along comparator flag to alu - controllers and zbb handle min/max instructions --- src/ieu/alu.sv | 3 ++- src/ieu/bmu/bmuctrl.sv | 4 ++++ src/ieu/bmu/zbb.sv | 11 +++++++++++ src/ieu/controller.sv | 13 ++++++++++++- src/ieu/datapath.sv | 2 +- 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 97400f44..0e7487eb 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -36,6 +36,7 @@ module alu #(parameter WIDTH=32) ( input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [1:0] CompFlags, // Comparator flags output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -145,7 +146,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ab275047..097ee27e 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -141,6 +141,10 @@ module bmuctrl( else BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 2342fe0c..3289d13a 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -34,6 +34,7 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation + input logic lt, // lt flag input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result @@ -41,6 +42,10 @@ module zbb #(parameter WIDTH=32) ( // count result logic [WIDTH-1:0] CntResult; + + // min,max result + logic [WIDTH-1:0] MaxResult; + logic [WIDTH-1:0] MinResult; // byte results logic [WIDTH-1:0] ByteResult; @@ -52,6 +57,10 @@ module zbb #(parameter WIDTH=32) ( byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); + + assign MaxResult = (lt) ? B : A; + assign MinResult = (lt) ? A : B; + //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) @@ -59,6 +68,8 @@ module zbb #(parameter WIDTH=32) ( 3'b000: ZBBResult = CntResult; // count 3'b100: ZBBResult = ExtResult; // sign/zero extend 3'b011: ZBBResult = ByteResult; // byte instructions + 3'b110: ZBBResult = MinResult; // min, minu + 3'b101: ZBBResult = MaxResult; // max, maxu /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 74d0e4f1..d6e0c191 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -108,6 +108,7 @@ module controller( logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic bclrD, bextD; // Indicates if is one of these instructions logic andnD, ornD, xnorD; // Indicates if is one of these instructions + logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -216,10 +217,19 @@ module controller( assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]); assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]); assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]); + // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator. + assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]); + assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]); + assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]); + assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]); end else begin assign andnD = 0; assign ornD = 0; assign xnorD = 0; + assign maxE = 0; + assign maxuE = 0; + assign minE = 0; + assign minuE = 0; end // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra @@ -263,7 +273,8 @@ module controller( // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE // Hence, only eq and lt flags are needed - assign BranchSignedE = ~(Funct3E[2:1] == 2'b11); + assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & ~BSelectE[2]) | (`ZBB_SUPPORTED & (maxE | minE)) ; + //assign BranchSignedE = ~(Funct3E[2:1] == 2'b11); assign {eqE, ltE} = FlagsE; mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE); assign BranchTakenE = BranchFlagE ^ Funct3E[0]; diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index ff25309f..d0f6f039 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -83,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); From d863f779964e7aac5cc8bc488e2db792ba72672a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Feb 2023 14:39:34 -0800 Subject: [PATCH 091/183] added arch32b tests (giving errors in sim however) --- config/rv32i/wally-config.vh | 8 +- testbench/testbench.sv | 1 + testbench/tests.vh | 251 ++++++++++++++++++++++++++++++----- 3 files changed, 223 insertions(+), 37 deletions(-) diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index d400cebe..f377468f 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -144,10 +144,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 681d6bb9..463ab0c4 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -131,6 +131,7 @@ logic [3:0] dummy; "embench": tests = embench; "coremark": tests = coremark; "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; + "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 5bf239ad..311a0741 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1326,10 +1326,103 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; + string arch64b[] = '{ `RISCVARCHTEST, - "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S", + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S", + "rv64i_m/I/src/add-01.S", + "rv64i_m/I/src/addi-01.S", + "rv64i_m/I/src/addiw-01.S", + "rv64i_m/I/src/addw-01.S", + "rv64i_m/I/src/and-01.S", + "rv64i_m/I/src/andi-01.S", + "rv64i_m/I/src/auipc-01.S", + "rv64i_m/I/src/beq-01.S", + "rv64i_m/I/src/bge-01.S", + "rv64i_m/I/src/bgeu-01.S", + "rv64i_m/I/src/blt-01.S", + "rv64i_m/I/src/bltu-01.S", + "rv64i_m/I/src/bne-01.S", + "rv64i_m/I/src/fence-01.S", + "rv64i_m/I/src/jal-01.S", + "rv64i_m/I/src/jalr-01.S", + "rv64i_m/I/src/lb-align-01.S", + "rv64i_m/I/src/lbu-align-01.S", + "rv64i_m/I/src/ld-align-01.S", + "rv64i_m/I/src/lh-align-01.S", + "rv64i_m/I/src/lhu-align-01.S", + "rv64i_m/I/src/lui-01.S", + "rv64i_m/I/src/lw-align-01.S", + "rv64i_m/I/src/lwu-align-01.S", + "rv64i_m/I/src/or-01.S", + "rv64i_m/I/src/ori-01.S", + "rv64i_m/I/src/sb-align-01.S", + "rv64i_m/I/src/sd-align-01.S", + "rv64i_m/I/src/sh-align-01.S", + "rv64i_m/I/src/sll-01.S", + "rv64i_m/I/src/slli-01.S", + "rv64i_m/I/src/slliw-01.S", + "rv64i_m/I/src/sllw-01.S", + "rv64i_m/I/src/slt-01.S", + "rv64i_m/I/src/slti-01.S", + "rv64i_m/I/src/sltiu-01.S", + "rv64i_m/I/src/sltu-01.S", + "rv64i_m/I/src/sra-01.S", + "rv64i_m/I/src/srai-01.S", + "rv64i_m/I/src/sraiw-01.S", + "rv64i_m/I/src/sraw-01.S", + "rv64i_m/I/src/srl-01.S", + "rv64i_m/I/src/srli-01.S", + "rv64i_m/I/src/srliw-01.S", + "rv64i_m/I/src/srlw-01.S", + "rv64i_m/I/src/sub-01.S", + "rv64i_m/I/src/subw-01.S", + "rv64i_m/I/src/sw-align-01.S", + "rv64i_m/I/src/xor-01.S", + "rv64i_m/I/src/xori-01.S", + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S" + /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bext-01.S", @@ -1339,39 +1432,131 @@ string arch64b[] = '{ "rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bseti-01.S", "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/rev8-01.S", + + + "rv64i_m/B/src/rol-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh3add.uw-01.S", - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/zext.h_64-01.S" + + + + + */ +}; + +string arch32b[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_64-01.S", + "rv32i_m/B/src/rev8-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/clzw-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/cpopw-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ctzw-01.S", + "rv32i_m/B/src/rolw-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/roriw-01.S", + "rv32i_m/B/src/rorw-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/slli.uw-01.S", + "rv32i_m/B/src/add.uw-01.S", + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S", + "rv32i_m/B/src/sh1add.uw-01.S", + "rv32i_m/B/src/sh2add.uw-01.S", + "rv32i_m/B/src/sh3add.uw-01.S", + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/addiw-01.S", + "rv32i_m/I/src/addw-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/ld-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/lwu-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sd-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slliw-01.S", + "rv32i_m/I/src/sllw-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/sraiw-01.S", + "rv32i_m/I/src/sraw-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/srliw-01.S", + "rv32i_m/I/src/srlw-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/subw-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S", + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S" + /*"rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S", + "rv64i_m/B/src/clmul-01.S", + + + + "rv64i_m/B/src/rol-01.S", + + + + + */ }; string arch32priv[] = '{ `RISCVARCHTEST, From 73833d55768ee2503488990a7ff7c3e217430fe6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Feb 2023 18:05:37 -0800 Subject: [PATCH 092/183] removed incompatible rv32 tests out of arch32b tests list --- testbench/tests.vh | 54 ++++++++++++++-------------------------------- 1 file changed, 16 insertions(+), 38 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 311a0741..f894d58f 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1445,42 +1445,40 @@ string arch64b[] = '{ string arch32b[] = '{ `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S", "rv32i_m/B/src/max-01.S", "rv32i_m/B/src/maxu-01.S", "rv32i_m/B/src/min-01.S", "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_64-01.S", - "rv32i_m/B/src/rev8-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", "rv32i_m/B/src/andn-01.S", "rv32i_m/B/src/orn-01.S", "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h-01.S", + "rv32i_m/B/src/zext.h_32-01.S", "rv32i_m/B/src/sext.b-01.S", "rv32i_m/B/src/sext.h-01.S", "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/clzw-01.S", "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/cpopw-01.S", "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ctzw-01.S", - "rv32i_m/B/src/rolw-01.S", "rv32i_m/B/src/ror-01.S", "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/roriw-01.S", - "rv32i_m/B/src/rorw-01.S", "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/slli.uw-01.S", - "rv32i_m/B/src/add.uw-01.S", "rv32i_m/B/src/sh1add-01.S", "rv32i_m/B/src/sh2add-01.S", "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/B/src/sh1add.uw-01.S", - "rv32i_m/B/src/sh2add.uw-01.S", - "rv32i_m/B/src/sh3add.uw-01.S", "rv32i_m/I/src/add-01.S", "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/addiw-01.S", - "rv32i_m/I/src/addw-01.S", "rv32i_m/I/src/and-01.S", "rv32i_m/I/src/andi-01.S", "rv32i_m/I/src/auipc-01.S", @@ -1495,49 +1493,29 @@ string arch32b[] = '{ "rv32i_m/I/src/jalr-01.S", "rv32i_m/I/src/lb-align-01.S", "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/ld-align-01.S", "rv32i_m/I/src/lh-align-01.S", "rv32i_m/I/src/lhu-align-01.S", "rv32i_m/I/src/lui-01.S", "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/lwu-align-01.S", "rv32i_m/I/src/or-01.S", "rv32i_m/I/src/ori-01.S", "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sd-align-01.S", "rv32i_m/I/src/sh-align-01.S", "rv32i_m/I/src/sll-01.S", "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slliw-01.S", - "rv32i_m/I/src/sllw-01.S", "rv32i_m/I/src/slt-01.S", "rv32i_m/I/src/slti-01.S", "rv32i_m/I/src/sltiu-01.S", "rv32i_m/I/src/sltu-01.S", "rv32i_m/I/src/sra-01.S", "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/sraiw-01.S", - "rv32i_m/I/src/sraw-01.S", "rv32i_m/I/src/srl-01.S", "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/srliw-01.S", - "rv32i_m/I/src/srlw-01.S", "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/subw-01.S", "rv32i_m/I/src/sw-align-01.S", "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S", - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S" + "rv32i_m/I/src/xori-01.S" + /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", From bb252acfbe2cd7599acfa69a104cc18ce8e7d8fa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 21 Feb 2023 11:52:05 -0800 Subject: [PATCH 093/183] added individual zb tests in tests.vh and testbench - also minor alu/controller configurability changes --- src/ieu/alu.sv | 4 +- src/ieu/controller.sv | 2 +- testbench/testbench.sv | 9 +- testbench/tests.vh | 285 +++++++++++++++++++++++++---------------- 4 files changed, 186 insertions(+), 114 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 0e7487eb..b6e8d0b4 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -106,7 +106,7 @@ module alu #(parameter WIDTH=32) ( assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; // Select appropriate ALU Result - if (`ZBS_SUPPORTED) begin + if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin always_comb if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect @@ -150,7 +150,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBBResult = 0; // Final Result B instruction select mux - if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder + if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d6e0c191..ff5bafa6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -239,7 +239,7 @@ module controller( assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; - if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags + if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 463ab0c4..9126f09c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -105,6 +105,10 @@ logic [3:0] dummy; "coremark": tests = coremark; "fpga": tests = fpga; "ahb" : tests = ahb; + "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; + "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; + "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; + "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 @@ -130,7 +134,10 @@ logic [3:0] dummy; "wally32periph": tests = wally32periph; "embench": tests = embench; "coremark": tests = coremark; - "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; + "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; + "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; + "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; + "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end diff --git a/testbench/tests.vh b/testbench/tests.vh index f894d58f..631775ae 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -836,17 +836,17 @@ string imperas32f[] = '{ }; - string wally64a[] = '{ + string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; - string wally32a[] = '{ + string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", "rv32i_m/privilege/src/WALLY-lrsc-01.S" - }; + }; string arch64priv[] = '{ `RISCVARCHTEST, @@ -881,14 +881,128 @@ string imperas32f[] = '{ "rv32i_m/Zifencei/src/Fencei.S" }; - string arch32ba[] = '{ + string arch32zba[] = '{ `RISCVARCHTEST, - // *** unclear why add.uw isn't in the list "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh1add-02.S", - "rv32i_m/B/src/sh1add-013.S" + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S" }; + string arch32zbb[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h_32-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/rol-01.S" + }; + + string arch32zbc[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S" + }; + + string arch32zbs[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S" + }; + + string arch32b[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S", + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h_32-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S", + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S" +}; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1422,101 +1536,59 @@ string arch64b[] = '{ "rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bseti-01.S" - /*"rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S", - "rv64i_m/B/src/clmul-01.S", - - - - "rv64i_m/B/src/rol-01.S", - - - - - */ }; -string arch32b[] = '{ + string arch64zba[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S" + }; + + + +string arch64zbb[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S" +}; + +string arch64zbc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S" +}; + +string arch64zbs[] = '{ `RISCVARCHTEST, - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S", - "rv32i_m/B/src/max-01.S", - "rv32i_m/B/src/maxu-01.S", - "rv32i_m/B/src/min-01.S", - "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_32-01.S", - "rv32i_m/B/src/rev8_32-01.S", - "rv32i_m/B/src/andn-01.S", - "rv32i_m/B/src/orn-01.S", - "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h_32-01.S", - "rv32i_m/B/src/sext.b-01.S", - "rv32i_m/B/src/sext.h-01.S", - "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ror-01.S", - "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh2add-01.S", - "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/I/src/add-01.S", - "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/and-01.S", - "rv32i_m/I/src/andi-01.S", - "rv32i_m/I/src/auipc-01.S", - "rv32i_m/I/src/beq-01.S", - "rv32i_m/I/src/bge-01.S", - "rv32i_m/I/src/bgeu-01.S", - "rv32i_m/I/src/blt-01.S", - "rv32i_m/I/src/bltu-01.S", - "rv32i_m/I/src/bne-01.S", - "rv32i_m/I/src/fence-01.S", - "rv32i_m/I/src/jal-01.S", - "rv32i_m/I/src/jalr-01.S", - "rv32i_m/I/src/lb-align-01.S", - "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/lh-align-01.S", - "rv32i_m/I/src/lhu-align-01.S", - "rv32i_m/I/src/lui-01.S", - "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/or-01.S", - "rv32i_m/I/src/ori-01.S", - "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sh-align-01.S", - "rv32i_m/I/src/sll-01.S", - "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slt-01.S", - "rv32i_m/I/src/slti-01.S", - "rv32i_m/I/src/sltiu-01.S", - "rv32i_m/I/src/sltu-01.S", - "rv32i_m/I/src/sra-01.S", - "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/srl-01.S", - "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/sw-align-01.S", - "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S" - - /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bext-01.S", @@ -1524,18 +1596,11 @@ string arch32b[] = '{ "rv64i_m/B/src/binv-01.S", "rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S", - "rv64i_m/B/src/clmul-01.S", - - - - "rv64i_m/B/src/rol-01.S", - - - - - */ + "rv64i_m/B/src/bseti-01.S" }; + + + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From 3b50909ab20ae23c3c758021968e4d3123eb0420 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 21 Feb 2023 15:26:47 -0800 Subject: [PATCH 094/183] added extra commands to make dut run work with spike for bit manip tests --- tests/riscof/spike/riscof_spike.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index d7d65c0b..308d55f2 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -105,6 +105,14 @@ class spike(pluginTemplate): self.isa += 'd' if "C" in ispec["ISA"]: self.isa += 'c' + if "Zba" in ispec["ISA"]: + self.isa += '_Zba' + if "Zbb" in ispec["ISA"]: + self.isa += '_Zbb' + if "Zbc" in ispec["ISA"]: + self.isa += '_Zbc' + if "Zbs" in ispec["ISA"]: + self.isa += '_Zbs' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately From 82611ba8893649f3cd8c94359e44bff27462e3ad Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 19:42:30 -0800 Subject: [PATCH 095/183] Manual attempt to merge with upstream changes --- sim/imperas.ic | 1 - sim/wally-imperas.do | 1 + src/generic/lzc.sv | 2 +- src/generic/mem/ram1p1rwbe.sv | 4 +- src/ieu/controller.sv | 4 +- src/ieu/datapath.sv | 29 ++++++++ src/ieu/ieu.sv | 9 +-- src/ifu/bpred/RASPredictor.sv | 7 +- src/ifu/bpred/bpred.sv | 75 ++++++++------------- src/ifu/bpred/btb.sv | 1 - src/ifu/bpred/gshare.sv | 4 +- src/ifu/ifu.sv | 2 + src/wally/wallypipelinedcore.sv | 3 + synthDC/.synopsys_dc.setup | 4 ++ synthDC/Makefile | 5 +- synthDC/wallySynth.py | 2 +- testbench/testbench_imperas.sv | 1 + testbench/tests.vh | 1 - tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 34 ---------- tests/riscof/spike/spike_rv32gc_isa.yaml | 4 +- tests/riscof/spike/spike_rv64gc_isa.yaml | 4 +- 21 files changed, 88 insertions(+), 109 deletions(-) delete mode 100644 tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py diff --git a/sim/imperas.ic b/sim/imperas.ic index 302773d0..d28234bb 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,6 +1,5 @@ --override cpu/show_c_prefix=T --override cpu/unaligned=F ---override cpu/mstatus_FS=1 --override cpu/ignore_non_leaf_DAU=1 # Enable the Imperas instruction coverage diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 821b9e54..985739cb 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -35,6 +35,7 @@ vlog +incdir+../config/$1 \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ ../src/*/*.sv \ diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index 60719c49..ecfd6796 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -33,6 +33,6 @@ module lzc #(parameter WIDTH = 1) ( always_comb begin i = 0; while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one - ZeroCnt = i[$clog2(WIDTH)-1:0]; + ZeroCnt = i[$clog2(WIDTH+1)-1:0]; end endmodule diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 81142a17..f3c98873 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -55,7 +55,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); @@ -75,7 +75,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 95ebe7dc..02ef3eea 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -66,6 +66,8 @@ module controller( output logic RegWriteM, // Instruction writes a register (needed for Hazard unit) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals @@ -88,8 +90,6 @@ module controller( logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) - logic JumpD; // Jump instruction - logic BranchD, BranchE; // Branch instruction logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index d0f6f039..9f09efe7 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -1,3 +1,32 @@ +/////////////////////////////////////////// +// datapath.sv +// +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Created: 9 January 2021 +// Modified: +// +// Purpose: Wally Integer Datapath +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + `include "wally-config.vh" module datapath ( diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 0b2fbf84..43c16554 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -55,6 +55,8 @@ module ieu ( input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, JumpE, // Writeback stage signals input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) input logic [`XLEN-1:0] CSRReadValW, // CSR read value, @@ -90,15 +92,14 @@ module ieu ( logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic JumpE; // Jump instruction logic BranchSignedE; // Branch does signed comparison on operands logic MDUE; // Multiply/divide instruction - controller c( +controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 0a841ae1..330607af 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -34,7 +34,9 @@ module RASPredictor #(parameter int StackSize = 16 )( input logic reset, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong - input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class + input logic [3:0] InstrClassD, + input logic [3:0] InstrClassE, // Instr class + input logic [3:0] PredInstrClassF, input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal output logic [`XLEN-1:0] RASPCF // Top of the stack ); @@ -93,6 +95,3 @@ module RASPredictor #(parameter int StackSize = 16 )( endmodule - - - diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index f6f82611..71077596 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -52,6 +52,8 @@ module bpred ( // Branch and jump outcome input logic InstrValidD, InstrValidE, + input logic BranchD, BranchE, + input logic JumpD, JumpE, input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address @@ -74,7 +76,8 @@ module bpred ( logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; - logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; + logic [3:0] InstrClassD; + logic [3:0] InstrClassE; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; logic SelBPPredF; @@ -83,9 +86,9 @@ module bpred ( logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; - logic BTBTargetWrongE; - logic RASTargetWrongE; - logic JumpOrTakenBranchE; + logic BTBTargetWrongE; + logic RASTargetWrongE; + logic JumpOrTakenBranchE; logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; @@ -113,29 +116,11 @@ module bpred ( .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); -<<<<<<< HEAD - end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); - - end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor - gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - - end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor - speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); - -======= end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); ->>>>>>> upstream/main end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me /* -----\/----- EXCLUDED -----\/----- @@ -167,7 +152,8 @@ module bpred ( if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode logic [4:0] CompressedOpcF; logic [3:0] InstrClassF; - logic cjal, cj, cjr, cjalr; + logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; + logic JumpF, BranchF; assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; @@ -175,24 +161,23 @@ module bpred ( assign cj = CompressedOpcF == 5'h0d; assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign CJumpF = cjal | cj | cjr | cjalr; + assign CBranchF = CompressedOpcF[4:1] == 4'h7; + + assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; + assign BranchF = PostSpillInstrRawF[6:0] == 7'h63; - assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); - - assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 - (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); - - assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF); + assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (cjal | cj | cj | cjalr)); + assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5 (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); - assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[2] | - PredInstrClassF[1] | - PredInstrClassF[3]; + PredInstrClassF[1]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | @@ -206,15 +191,13 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; - assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 - assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 - assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + assign InstrClassD[0] = BranchD; + assign InstrClassD[1] = JumpD ; + assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 + assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); - flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); // branch predictor @@ -235,13 +218,10 @@ module bpred ( assign PredictionPCWrongE = PCCorrectE != PCD; // branch class prediction wrong. - assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; + assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[3:0]; assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. -<<<<<<< HEAD - assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; -======= //assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE)); assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; @@ -249,7 +229,6 @@ module bpred ( logic NotMatch; assign BPPredWrongEAlt = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark assign NotMatch = BPPredWrongE != BPPredWrongEAlt; ->>>>>>> upstream/main // Output the predicted PC or corrected PC on miss-predict. // Selects the BP or PC+2/4. @@ -274,10 +253,10 @@ module bpred ( // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; - assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1]; flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index a6201d4c..8e2d0e25 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -52,7 +52,6 @@ module btb #(parameter Depth = 10 ) ( logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; - logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; // hashing function for indexing the PC diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 7ab6f714..5332ce5c 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -33,8 +33,8 @@ module gshare #(parameter k = 10, parameter integer TYPE = 1) ( input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 73e4c7e7..71221ef6 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -36,6 +36,8 @@ module ifu ( input logic InvalidateICacheM, // Clears all instruction cache valid bits input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) input logic InstrValidD, InstrValidE, InstrValidM, + input logic BranchD, BranchE, + input logic JumpD, JumpE, // Bus interface output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 71bad10a..02074f97 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -161,11 +161,13 @@ module wallypipelinedcore ( logic FCvtIntE; logic CommittedF; logic JumpOrTakenBranchM; + logic BranchD, BranchE, JumpD, JumpE; // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidM, .InstrValidE, .InstrValidD, + .BranchD, .BranchE, .JumpD, .JumpE, // Fetch .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, @@ -199,6 +201,7 @@ module wallypipelinedcore ( .Funct3M, // size and signedness to LSU .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + .BranchD, .BranchE, .JumpD, .JumpE, // Writeback stage .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW, diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 310b45c0..5c6b7f6b 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -52,6 +52,10 @@ if {$tech == "sky130"} { lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db } elseif {$tech == "tsmc28"} { lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db +} elseif {$tech == "tsmc28psyn"} { + set mw_reference_library [list ] + lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db + lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140 } # Set up DesignWare cache read and write directories to speed up compile. diff --git a/synthDC/Makefile b/synthDC/Makefile index 208fabaa..136e610d 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -30,8 +30,6 @@ export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/config export CONFIGDIR ?= $(OUTPUTDIR)/config - - default: @echo " Basic synthesis procedure for Wally:" @echo " Invoke with make synth" @@ -130,7 +128,6 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped - synth: mkdirecs configs rundc clean rundc: @@ -150,4 +147,4 @@ clean: rm -f filenames*.log rm -f power.saif rm -f Synopsys_stack_trace_*.txt - rm -f crte_*.txt \ No newline at end of file + rm -f crte_*.txt diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index c1ea7b9c..139bcdd6 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -16,7 +16,7 @@ def mask(command): if __name__ == '__main__': - techs = ['sky90', 'tsmc28'] + techs = ['sky90', 'tsmc28', 'tsmc28psyn'] allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] # freqVaryPct = [-20, -10, 0, 10, 20] diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index cbd08c3b..f2633900 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -126,6 +126,7 @@ module testbench; `ifdef USE_IMPERAS_DV trace2log idv_trace2log(rvvi); + trace2cov idv_trace2cov(rvvi); // enabling of comparison types trace2api #(.CMP_PC (1), diff --git a/testbench/tests.vh b/testbench/tests.vh index cb15a5ee..e86b83f9 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -54,7 +54,6 @@ string tvpaths[] = '{ "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py deleted file mode 100644 index 4a728a47..00000000 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ /dev/null @@ -1,34 +0,0 @@ -#Kip Macsai-Goren and Kevin Kim -#Purpose is to manually make the B extension tests -import os - -f = open("genBScript.sh", "w") -WALLY = os.getenv("WALLY") -os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") - -lines = "" - -#BUILDS B TESTS -for testname in os.listdir(): - lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; -riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile; -extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump; -""" - -os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/I/src") - -#BUILDS I TESTS -for testname in os.listdir(): - lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; -riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.memfile; -extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.objdump; -""" - - - - -f.write(lines) -f.close() - diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 4a593524..05fc6f60 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: #ISA: RV32IMAFDCZicsr_Zifencei - ISA: RV32IMACZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001105 + reset-val: 0x4000112D rv32: accessible: true mxl: diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index ad745f47..e6bfc72e 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zifencei - ISA: RV64IMACSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x8000000000141105 + reset-val: 0x800000000014112D rv32: accessible: false rv64: From a61b1dca23f4fbeb1b8377780c751609c6db3a84 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:17:52 -0800 Subject: [PATCH 096/183] added 32 bit tests for bit manipulation --- config/rv32gc/wally-config.vh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index 57857f3b..1fb89abf 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -144,10 +144,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 From 57b7f66be5be84e00867a0a0aac5f4eafeea8f63 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:18:05 -0800 Subject: [PATCH 097/183] added bit manipulation tests to regression --- sim/regression-wally | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 07603120..82cb4eff 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -66,7 +66,7 @@ tc = TestCase( configs.append(tc) tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused -tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "wally64a", "wally64periph", "wally64priv"] for test in tests64gc: tc = TestCase( name=test, @@ -85,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( name=test, From f8f89e692e7766ecb52563221e2102fad9a45237 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:25:51 -0800 Subject: [PATCH 098/183] Fixed lint errors on zero and pop count. All of regression passes --- src/ieu/bmu/cnt.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 540d5e91..32be6b2e 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -79,9 +79,12 @@ module cnt #(parameter WIDTH = 32) ( end end - //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. - lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult)); - popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult)); + + lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0])); + popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0])); + // zero extend these results to fit into width *** There may be a more elegant way to do this + assign czResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; + assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; assign CntResult = (B[1]) ? cpopResult : czResult; From b658329118ed7a5afe9dc7616a98b40cc6780360 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:35:01 -0800 Subject: [PATCH 099/183] Cleaned up consolidated arch_b tests from tests.vh --- testbench/testbench.sv | 4 +- testbench/tests.vh | 176 ----------------------------------------- 2 files changed, 1 insertion(+), 179 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ec282957..eb501499 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -109,7 +109,6 @@ logic [3:0] dummy; "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; - "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 case (TEST) @@ -138,7 +137,6 @@ logic [3:0] dummy; "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; - "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end if (tests.size() == 0) begin @@ -364,7 +362,7 @@ logic [3:0] dummy; errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - $stop;//***debug + //$stop;//***debug end i = i + 1; end diff --git a/testbench/tests.vh b/testbench/tests.vh index e86b83f9..e00ae7d7 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -929,80 +929,6 @@ string imperas32f[] = '{ "rv32i_m/B/src/bseti-01.S" }; - string arch32b[] = '{ - `RISCVARCHTEST, - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S", - "rv32i_m/B/src/max-01.S", - "rv32i_m/B/src/maxu-01.S", - "rv32i_m/B/src/min-01.S", - "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_32-01.S", - "rv32i_m/B/src/rev8_32-01.S", - "rv32i_m/B/src/andn-01.S", - "rv32i_m/B/src/orn-01.S", - "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h_32-01.S", - "rv32i_m/B/src/sext.b-01.S", - "rv32i_m/B/src/sext.h-01.S", - "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ror-01.S", - "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh2add-01.S", - "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/I/src/add-01.S", - "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/and-01.S", - "rv32i_m/I/src/andi-01.S", - "rv32i_m/I/src/auipc-01.S", - "rv32i_m/I/src/beq-01.S", - "rv32i_m/I/src/bge-01.S", - "rv32i_m/I/src/bgeu-01.S", - "rv32i_m/I/src/blt-01.S", - "rv32i_m/I/src/bltu-01.S", - "rv32i_m/I/src/bne-01.S", - "rv32i_m/I/src/fence-01.S", - "rv32i_m/I/src/jal-01.S", - "rv32i_m/I/src/jalr-01.S", - "rv32i_m/I/src/lb-align-01.S", - "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/lh-align-01.S", - "rv32i_m/I/src/lhu-align-01.S", - "rv32i_m/I/src/lui-01.S", - "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/or-01.S", - "rv32i_m/I/src/ori-01.S", - "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sh-align-01.S", - "rv32i_m/I/src/sll-01.S", - "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slt-01.S", - "rv32i_m/I/src/slti-01.S", - "rv32i_m/I/src/sltiu-01.S", - "rv32i_m/I/src/sltu-01.S", - "rv32i_m/I/src/sra-01.S", - "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/srl-01.S", - "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/sw-align-01.S", - "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S" -}; - string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1440,104 +1366,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; - -string arch64b[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/rev8-01.S", - "rv64i_m/B/src/andn-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/rol-01.S", - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add.uw-01.S", - "rv64i_m/I/src/add-01.S", - "rv64i_m/I/src/addi-01.S", - "rv64i_m/I/src/addiw-01.S", - "rv64i_m/I/src/addw-01.S", - "rv64i_m/I/src/and-01.S", - "rv64i_m/I/src/andi-01.S", - "rv64i_m/I/src/auipc-01.S", - "rv64i_m/I/src/beq-01.S", - "rv64i_m/I/src/bge-01.S", - "rv64i_m/I/src/bgeu-01.S", - "rv64i_m/I/src/blt-01.S", - "rv64i_m/I/src/bltu-01.S", - "rv64i_m/I/src/bne-01.S", - "rv64i_m/I/src/fence-01.S", - "rv64i_m/I/src/jal-01.S", - "rv64i_m/I/src/jalr-01.S", - "rv64i_m/I/src/lb-align-01.S", - "rv64i_m/I/src/lbu-align-01.S", - "rv64i_m/I/src/ld-align-01.S", - "rv64i_m/I/src/lh-align-01.S", - "rv64i_m/I/src/lhu-align-01.S", - "rv64i_m/I/src/lui-01.S", - "rv64i_m/I/src/lw-align-01.S", - "rv64i_m/I/src/lwu-align-01.S", - "rv64i_m/I/src/or-01.S", - "rv64i_m/I/src/ori-01.S", - "rv64i_m/I/src/sb-align-01.S", - "rv64i_m/I/src/sd-align-01.S", - "rv64i_m/I/src/sh-align-01.S", - "rv64i_m/I/src/sll-01.S", - "rv64i_m/I/src/slli-01.S", - "rv64i_m/I/src/slliw-01.S", - "rv64i_m/I/src/sllw-01.S", - "rv64i_m/I/src/slt-01.S", - "rv64i_m/I/src/slti-01.S", - "rv64i_m/I/src/sltiu-01.S", - "rv64i_m/I/src/sltu-01.S", - "rv64i_m/I/src/sra-01.S", - "rv64i_m/I/src/srai-01.S", - "rv64i_m/I/src/sraiw-01.S", - "rv64i_m/I/src/sraw-01.S", - "rv64i_m/I/src/srl-01.S", - "rv64i_m/I/src/srli-01.S", - "rv64i_m/I/src/srliw-01.S", - "rv64i_m/I/src/srlw-01.S", - "rv64i_m/I/src/sub-01.S", - "rv64i_m/I/src/subw-01.S", - "rv64i_m/I/src/sw-align-01.S", - "rv64i_m/I/src/xor-01.S", - "rv64i_m/I/src/xori-01.S", - "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S", - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S" -}; - string arch64zba[] = '{ `RISCVARCHTEST, "rv64i_m/B/src/slli.uw-01.S", @@ -1550,8 +1378,6 @@ string arch64b[] = '{ "rv64i_m/B/src/sh3add.uw-01.S" }; - - string arch64zbb[] = '{ `RISCVARCHTEST, "rv64i_m/B/src/max-01.S", @@ -1599,8 +1425,6 @@ string arch64zbs[] = '{ "rv64i_m/B/src/bseti-01.S" }; - - string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From 4e0ada05827429f5be3e65a205c85d82e605e0f7 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:42:52 -0800 Subject: [PATCH 100/183] removed bit manipulation from rv[xlen]_i. tests still pass --- config/rv32i/wally-config.vh | 8 ++++---- config/rv64i/wally-config.vh | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index baee5a82..efbf6e7c 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -145,10 +145,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 671e3620..a3702c3f 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -147,10 +147,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 // Memory synthesis configuration `define USE_SRAM 0 From c64723fd5abe265b85c4271676e875c5090b44a0 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:47:14 -0800 Subject: [PATCH 101/183] removed comment out on stop in testbench --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index eb501499..756b75f4 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -362,7 +362,7 @@ logic [3:0] dummy; errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - //$stop;//***debug + $stop;//***debug end i = i + 1; end From f0cf7c2c6a07bd3e0d9a02dfb386e2adc6d63545 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Feb 2023 21:57:28 -0800 Subject: [PATCH 102/183] small optimization to condzext select --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index b6e8d0b4..222097e1 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -64,7 +64,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Zero Extend Mux if (WIDTH == 64) begin - assign CondZextA = (BSelect[3] & (W64 | Funct3[0])) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? + assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? end else assign CondZextA = A; // Pre-Shift Mux From a856c5de96f7445bd28d875ec7bb0d2c4ddc4150 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 12:09:34 -0800 Subject: [PATCH 103/183] optimized mux to shifter, passes rv32/64i --- src/ieu/alu.sv | 14 +++- src/ieu/shifternew.sv | 153 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 src/ieu/shifternew.sv diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 222097e1..7979e065 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -54,6 +54,7 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic Rotate; + logic [WIDTH:0] shA; // 65 bit input source to shifter if (`ZBS_SUPPORTED) begin: zbsdec @@ -61,6 +62,17 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; + + if (WIDTH == 64) begin + always_comb + case ({W64, SubArith}) + 2'b00: shA = {{1'b0}, A}; + 2'b01: shA = {A[63], A}; + 2'b10: shA = {{33'b0}, A[31:0]}; + 2'b11: shA = {{33{A[31]}}, A[31:0]}; + endcase + end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; + if (`ZBA_SUPPORTED) begin: zbamuxes // Zero Extend Mux if (WIDTH == 64) begin @@ -89,7 +101,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); + shifternew sh(.shA(shA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifternew.sv b/src/ieu/shifternew.sv new file mode 100644 index 00000000..12f2bf99 --- /dev/null +++ b/src/ieu/shifternew.sv @@ -0,0 +1,153 @@ +/////////////////////////////////////////// +// shifter.sv +// +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu +// Created: 9 January 2021 +// Modified: 6 February 2023 +// +// Purpose: RISC-V 32/64 bit shifter +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module shifternew ( + input logic [`XLEN:0] shA, // Source + input logic [`LOG_XLEN-1:0] Amt, // Shift amount + input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + output logic [`XLEN-1:0] Y); // Shifted result + + logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + + + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + // Handle left and right shifts with a funnel shifter. + // For RV32, only 32-bit shifts are needed. + // For RV64, 32- and 64-bit shifts are needed, with sign extension. + /* + // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + */ + /* + + if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) + else + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else + if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw + else + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else + if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Rotate) z = {A[62:0], A[63:0]}; //ror + else + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else + if (Rotate) z = {A[63:0], A[63:1]}; //rol + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotFunnel + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end + */ + // Opposite offset for right shifts + assign offset = Right ? amttrunc : ~amttrunc; + //if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; + //else assign CondOffsetTrunc = offset; + + // Funnel operation + assign zshift = z >> offset; + assign Y = zshift[`XLEN-1:0]; +endmodule + + From 0fe1d3b9f3734364430b9a12bbfe6fa6acb4ff9b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 17:09:56 -0800 Subject: [PATCH 104/183] took sign extension out of shifter --- src/ieu/alu.sv | 30 ++++++---- src/ieu/shifternew.sv | 128 ++++++++++-------------------------------- 2 files changed, 49 insertions(+), 109 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 7979e065..46ca2e17 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -54,7 +54,8 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic Rotate; - logic [WIDTH:0] shA; // 65 bit input source to shifter + logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter if (`ZBS_SUPPORTED) begin: zbsdec @@ -63,15 +64,22 @@ module alu #(parameter WIDTH=32) ( end else assign CondMaskB = B; - if (WIDTH == 64) begin - always_comb - case ({W64, SubArith}) - 2'b00: shA = {{1'b0}, A}; - 2'b01: shA = {A[63], A}; - 2'b10: shA = {{33'b0}, A[31:0]}; - 2'b11: shA = {{33{A[31]}}, A[31:0]}; - endcase - end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; + // Sign/Zero extend mux + if (WIDTH == 64) begin // rv64 must handle word s/z extensions + always_comb + case ({W64, SubArith}) + 2'b00: shA = {{1'b0}, A}; + 2'b01: shA = {A[63], A}; + 2'b10: shA = {{33'b0}, A[31:0]}; + 2'b11: shA = {{33{A[31]}}, A[31:0]}; + endcase + end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions + + // shifter rotate source select mux + if (`ZBB_SUPPORTED) begin + if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; + else assign rotA = A; // NOTE: change this for the future! + end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes // Zero Extend Mux @@ -101,7 +109,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifternew sh(.shA(shA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); + shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifternew.sv b/src/ieu/shifternew.sv index 12f2bf99..e58a1277 100644 --- a/src/ieu/shifternew.sv +++ b/src/ieu/shifternew.sv @@ -30,120 +30,52 @@ `include "wally-config.vh" module shifternew ( - input logic [`XLEN:0] shA, // Source + input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Rotate, W64, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) z = {{31{shA[32]}}, shA[31:0]}; - else z = {shA[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (Right) z = {{63{shA[64]}},shA[63:0]}; - else z = {shA[63:0],{63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - // Handle left and right shifts with a funnel shifter. - // For RV32, only 32-bit shifts are needed. - // For RV64, 32- and 64-bit shifts are needed, with sign extension. - /* - // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - */ - /* - - if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`ZBB_SUPPORTED) begin: rotfunnel + if (`XLEN==32) begin // rv32 with rotates + always_comb // funnel mux + case({Right, Rotate}) + 2'b00: z = {shA[31:0], 31'b0}; + 2'b01: z = {rotA,rotA[31:1]}; + 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b11: z = {rotA[30:0],rotA}; + endcase + assign amttrunc = Amt; // shift amount + end else begin // rv64 with rotates + always_comb // funnel mux + case ({Right, Rotate}) + 2'b00: z = {shA[63:0],{63'b0}}; + 2'b01: z = {rotA, rotA[63:1]}; + 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b11: z = {rotA[62:0],rotA[63:0]}; + endcase + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) - if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) - else - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else - if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) - else z = {A, 31'b0}; + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw - else - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else - if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Rotate) z = {A[62:0], A[63:0]}; //ror - else - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else - if (Rotate) z = {A[63:0], A[63:1]}; //rol - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotFunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end - */ + // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; - //if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; - //else assign CondOffsetTrunc = offset; // Funnel operation assign zshift = z >> offset; From b3180d73076dfc615fc0bfad1c4c6634284c8ce4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 17:14:12 -0800 Subject: [PATCH 105/183] removed now-redundant zero-extend mux in alu --- src/ieu/alu.sv | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 46ca2e17..1fdd06e4 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -78,22 +78,17 @@ module alu #(parameter WIDTH=32) ( // shifter rotate source select mux if (`ZBB_SUPPORTED) begin if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; - else assign rotA = A; // NOTE: change this for the future! + else assign rotA = A; end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes - // Zero Extend Mux - if (WIDTH == 64) begin - assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? - end else assign CondZextA = A; - // Pre-Shift Mux always_comb case (Funct3[2:1] & {2{BSelect[3]}}) - 2'b00: CondShiftA = CondZextA; - 2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}}; // sh1add - 2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}}; // sh2add - 2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add + 2'b00: CondShiftA = shA[63:0]; + 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add + 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add + 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add endcase end else assign CondShiftA = A; From c7050ada78194bf857d578212aa8445fc253cf7e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 17:33:47 -0800 Subject: [PATCH 106/183] removed old shifter --- src/ieu/alu.sv | 4 +- src/ieu/shifter.sv | 121 ++++++++++++------------------------------ src/ieu/shifternew.sv | 85 ----------------------------- 3 files changed, 35 insertions(+), 175 deletions(-) delete mode 100644 src/ieu/shifternew.sv diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 1fdd06e4..96d8c8f5 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -55,7 +55,7 @@ module alu #(parameter WIDTH=32) ( logic Asign, Bsign; // Sign bits of A, B logic Rotate; logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter - logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter if (`ZBS_SUPPORTED) begin: zbsdec @@ -85,7 +85,7 @@ module alu #(parameter WIDTH=32) ( // Pre-Shift Mux always_comb case (Funct3[2:1] & {2{BSelect[3]}}) - 2'b00: CondShiftA = shA[63:0]; + 2'b00: CondShiftA = shA[WIDTH-1:0]; 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index feb346ef..f6cb5bc1 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // shifter.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, Kevin Kim // Created: 9 January 2021 // Modified: 6 February 2023 // @@ -29,111 +29,56 @@ `include "wally-config.vh" -module shifter ( - input logic [`XLEN-1:0] A, // Source +module shifternew ( + input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Rotate, W64, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - // Handle left and right shifts with a funnel shifter. - // For RV32, only 32-bit shifts are needed. - // For RV64, 32- and 64-bit shifts are needed, with sign extension. - /* - // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - */ - if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`ZBB_SUPPORTED) begin: rotfunnel + if (`XLEN==32) begin // rv32 with rotates + always_comb // funnel mux + case({Right, Rotate}) + 2'b00: z = {shA[31:0], 31'b0}; + 2'b01: z = {rotA,rotA[31:1]}; + 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b11: z = {rotA[30:0],rotA}; + endcase + assign amttrunc = Amt; // shift amount + end else begin // rv64 with rotates + always_comb // funnel mux + case ({Right, Rotate}) + 2'b00: z = {shA[63:0],{63'b0}}; + 2'b01: z = {rotA, rotA[63:1]}; + 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b11: z = {rotA[62:0],rotA[63:0]}; + endcase + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) - if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) - else - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else - if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) - else z = {A, 31'b0}; + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw - else - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else - if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Rotate) z = {A[62:0], A[63:0]}; //ror - else - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else - if (Rotate) z = {A[63:0], A[63:1]}; //rol - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotFunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end - + // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; - if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; - else assign CondOffsetTrunc = offset; // Funnel operation - assign zshift = z >> CondOffsetTrunc; + assign zshift = z >> offset; assign Y = zshift[`XLEN-1:0]; endmodule diff --git a/src/ieu/shifternew.sv b/src/ieu/shifternew.sv deleted file mode 100644 index e58a1277..00000000 --- a/src/ieu/shifternew.sv +++ /dev/null @@ -1,85 +0,0 @@ -/////////////////////////////////////////// -// shifter.sv -// -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu -// Created: 9 January 2021 -// Modified: 6 February 2023 -// -// Purpose: RISC-V 32/64 bit shifter -// -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module shifternew ( - input logic [`XLEN:0] shA, // shift Source - input logic [`XLEN-1:0] rotA, // rotate source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, // Shift right, rotate signals - output logic [`XLEN-1:0] Y); // Shifted result - - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - - - if (`ZBB_SUPPORTED) begin: rotfunnel - if (`XLEN==32) begin // rv32 with rotates - always_comb // funnel mux - case({Right, Rotate}) - 2'b00: z = {shA[31:0], 31'b0}; - 2'b01: z = {rotA,rotA[31:1]}; - 2'b10: z = {{31{shA[32]}}, shA[31:0]}; - 2'b11: z = {rotA[30:0],rotA}; - endcase - assign amttrunc = Amt; // shift amount - end else begin // rv64 with rotates - always_comb // funnel mux - case ({Right, Rotate}) - 2'b00: z = {shA[63:0],{63'b0}}; - 2'b01: z = {rotA, rotA[63:1]}; - 2'b10: z = {{63{shA[64]}},shA[63:0]}; - 2'b11: z = {rotA[62:0],rotA[63:0]}; - endcase - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotfunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) z = {{31{shA[32]}}, shA[31:0]}; - else z = {shA[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (Right) z = {{63{shA[64]}},shA[63:0]}; - else z = {shA[63:0],{63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end - - // Opposite offset for right shifts - assign offset = Right ? amttrunc : ~amttrunc; - - // Funnel operation - assign zshift = z >> offset; - assign Y = zshift[`XLEN-1:0]; -endmodule - - From 30ef1ac9e3aacff69f42a4227a291892cf787760 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 07:27:34 -0800 Subject: [PATCH 107/183] rename result back to ALUResult in ALU --- src/ieu/alu.sv | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 96d8c8f5..d5f33827 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,12 +37,12 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags - output logic [WIDTH-1:0] Result, // ALU result + output logic [WIDTH-1:0] ALUResult, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -152,8 +152,8 @@ module alu #(parameter WIDTH=32) ( // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; + if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign CondExtFullResult = FullResult; //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc @@ -161,7 +161,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -169,11 +169,11 @@ module alu #(parameter WIDTH=32) ( always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS - 4'b0001: Result = FullResult; - 4'b0010: Result = ZBCResult; - 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. - 4'b0100: Result = ZBBResult; - default: Result = ALUResult; + 4'b0001: ALUResult = FullResult; + 4'b0010: ALUResult = ZBCResult; + 4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. + 4'b0100: ALUResult = ZBBResult; + default: ALUResult = CondExtFullResult; endcase - end else assign Result = ALUResult; + end else assign ALUResult = CondExtFullResult; endmodule \ No newline at end of file From 82059fba67a5efef2a091c264fd9f8fa8c874072 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 11:41:40 -0800 Subject: [PATCH 108/183] changed shifter source select signal name --- src/ieu/alu.sv | 5 ++++- src/ieu/controller.sv | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index d5f33827..f1bfd912 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -56,6 +56,9 @@ module alu #(parameter WIDTH=32) ( logic Rotate; logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [1:0] shASelect; // select signal for shifter source generation mux + + assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec @@ -67,7 +70,7 @@ module alu #(parameter WIDTH=32) ( // Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb - case ({W64, SubArith}) + case (shASelect) 2'b00: shA = {{1'b0}, A}; 2'b01: shA = {A[63], A}; 2'b10: shA = {{33'b0}, A[31:0]}; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 02ef3eea..2520bbe2 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -197,7 +197,8 @@ module controller( assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - + + //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); From 6835a635cc459623d4aa3509325f3d53c1f553f9 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 11:54:10 -0800 Subject: [PATCH 109/183] added BRegWrite, BW64, BALUOp signals to bctrl and controller -TODO: Main decode in bmuctrl must assert these 3 signals --- src/ieu/bmu/bmuctrl.sv | 11 +++++++---- src/ieu/controller.sv | 5 ++++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 097ee27e..0ca949ef 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -38,6 +38,9 @@ module bmuctrl( output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? + output logic BRegWriteD, // Indicates if it is a R type B instruction + output logic BW64D, // Indiciates if it is a W type B instruction + output logic BALUOpD, // Indicates if it is an ALU B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -50,7 +53,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 10 + `define BMUCTRLW 13 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -64,7 +67,7 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) @@ -146,12 +149,12 @@ module bmuctrl( 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu - default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2520bbe2..e39c5cac 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -121,6 +121,9 @@ module controller( logic IntDivM; // Integer divide instruction logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal + logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage + logic BW64D; // Indiciates if it is a W type B instruction in decode stage + logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage // Extract fields @@ -241,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From 036cad71c6171ddd2f9a111145f25a8196d90b91 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 12:09:35 -0800 Subject: [PATCH 110/183] bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG] --- src/ieu/bmu/bmuctrl.sv | 108 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 0ca949ef..7bc2bbe3 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -69,85 +69,85 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti + BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase From 96995c559365db48ca7c3dea01fc611a111e7028 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:22:09 -0800 Subject: [PATCH 111/183] removed redundant zbs --- src/ieu/bmu/zbs.sv | 59 ---------------------------------------------- 1 file changed, 59 deletions(-) delete mode 100644 src/ieu/bmu/zbs.sv diff --git a/src/ieu/bmu/zbs.sv b/src/ieu/bmu/zbs.sv deleted file mode 100644 index 214d6e2c..00000000 --- a/src/ieu/bmu/zbs.sv +++ /dev/null @@ -1,59 +0,0 @@ -/////////////////////////////////////////// -// zbs.sv -// -// Written: Kevin Kim and Kip Macsai-Goren -// Created: 31 January 2023 -// Modified: -// -// Purpose: RISC-V single bit manipulation unit (ZBS instructions) -// -// Documentation: RISC-V System on Chip Design Chapter *** -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module zbs #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, - input logic [2:0] Funct3, // With ***Control, indicates operation to perform - output logic [WIDTH-1:0] ZBSResult); // ZBS result - - logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; - - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); - - assign InvResult = A ^ BMask; - assign ClrResult = A & ~BMask; - assign SetResult = A | BMask; - assign ExtResult = {{(WIDTH-1){1'b0}},{|(A & BMask)}}; - - always_comb begin - casez ({Funct7, Funct3}) - 10'b010010?_001: ZBSResult = ClrResult; - 10'b010010?_101: ZBSResult = ExtResult; - 10'b011010?_001: ZBSResult = InvResult; - 10'b001010?_001: ZBSResult = SetResult; - default: ZBSResult = 0; // *** expand to include faults - endcase - end - -endmodule - From 44d40afca817b7615b104ef447b86901cb2e3464 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:36:12 -0800 Subject: [PATCH 112/183] fixed controller lint, changed byte unit mux select name and input width --- src/ieu/bmu/byte.sv | 5 +++-- src/ieu/bmu/zbb.sv | 2 +- src/ieu/controller.sv | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index efd43d84..2b98b83d 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -30,7 +30,8 @@ `include "wally-config.vh" module byteUnit #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, // Operands + input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result logic [WIDTH-1:0] OrcBResult, Rev8Result; @@ -41,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) ( assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i]; end - assign ByteResult = (B[0]) ? OrcBResult : Rev8Result; + assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 3289d13a..13529d6a 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -54,7 +54,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] ExtResult; // sign/zero extend result cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); - byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult)); + byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 7bbc8bf6..d27af3b4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -244,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From 2bfbf051a5a06d19f3a72ba70ae8915bf1923d7e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:40:29 -0800 Subject: [PATCH 113/183] zbc select mux optimization --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 580cdacc..ad858846 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -66,7 +66,7 @@ module zbc #(parameter WIDTH=32) ( clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3 == 3'b011 || Funct3 == 3'b010) ? RevClmulResult : ClmulResult; + assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From 905373d53b72dc7963edf5b068bb97e2a9b39b6c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:43:05 -0800 Subject: [PATCH 114/183] zbc input select mux optimize --- src/ieu/bmu/zbc.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index ad858846..243ed396 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -43,16 +43,16 @@ module zbc #(parameter WIDTH=32) ( //NOTE: Optimize this when doing decoder stuff. always_comb begin - casez (Funct3) - 3'b001: begin //clmul + casez (Funct3[1:0]) + 2'b01: begin //clmul x = A; y = B; end - 3'b011: begin //clmulh + 2'b11: begin //clmulh x = {RevA[WIDTH-2:0], {1'b0}}; y = {{1'b0}, RevB[WIDTH-2:0]}; end - 3'b010: begin //clmulr + 2'b10: begin //clmulr x = RevA; y = RevB; end From d40f3b2a1cd6714e667462d265ae294bbddd692d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:45:32 -0800 Subject: [PATCH 115/183] rename shifternew to shifter --- src/ieu/alu.sv | 4 ++-- src/ieu/shifter.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index f1bfd912..4cf8d6ed 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -106,8 +106,8 @@ module alu #(parameter WIDTH=32) ( assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; - // Shifts - shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + // Shifts (configurable for rotation) + shifter sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index f6cb5bc1..b784414b 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" -module shifternew ( +module shifter ( input logic [`XLEN:0] shA, // shift Source input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount From 7dd4a2e9755a0534dcb493633f765724fb0bf7c6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:15:22 -0800 Subject: [PATCH 116/183] added BRegWriteE signal --- src/ieu/bmu/bmuctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 7bc2bbe3..b9df2154 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -45,7 +45,8 @@ module bmuctrl( input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - output logic [2:0] ZBBSelectE // ZBB mux select signal + output logic [2:0] ZBBSelectE, // ZBB mux select signal + output logic BRegWriteE // Indicates if it is a R type B instruction in Execute ); logic [6:0] OpD; // Opcode in Decode stage @@ -159,5 +160,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE}); + flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE}); endmodule \ No newline at end of file From 1e1ecaafb18375cdfc22bca23857697571af7d6a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:15:57 -0800 Subject: [PATCH 117/183] moved SubArith and RegWriteE into configurable block --- src/ieu/controller.sv | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d27af3b4..549e23ad 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -114,6 +114,7 @@ module controller( logic unused; logic BranchFlagE; // Branch flag to use (chosen between eq or lt) logic IEURegWriteE; // Register write + logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE, FenceM; // Fence instruction @@ -240,17 +241,26 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand - assign ALUControlD = {W64D, SubArithD, ALUOpD}; + assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + + assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers + assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b0000; assign BSelectD = 4'b0000; assign ZBBSelectE = 3'b000; + assign BRegWriteD = 1'b0; + assign BW64D = 1'b0; + assign BALUOpD = 1'b0; + assign BRegWriteE = 1'b0; + + assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); end // Fences @@ -287,7 +297,6 @@ module controller( // Other execute stage controller signals assign MemReadE = MemRWE[1]; assign SCE = (ResultSrcE == 3'b100); - assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign IntDivE = MDUE & Funct3E[2]; // Integer division operation // Memory stage pipeline control register From 1b222f91bea4f6428591108a289cc639ee2ceea5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:17:03 -0800 Subject: [PATCH 118/183] moved ALUControlD into configurable block --- src/ieu/controller.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 549e23ad..6911f75e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -241,13 +241,13 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand + assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -261,6 +261,7 @@ module controller( assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); + assign ALUControlD = {W64D, SubArithD, ALUOpD}; end // Fences From 2d7d143f6d0088722345e8347c425bda88e56715 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 13:45:15 -0800 Subject: [PATCH 119/183] formatted bmu decoder --- src/ieu/bmu/bmuctrl.sv | 108 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b9df2154..e838c6ea 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -70,85 +70,85 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase From b52208b53965451ca93513d5065ad86e893d839b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 13:52:00 -0800 Subject: [PATCH 120/183] zbc comments --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 243ed396..011af80e 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -41,7 +41,7 @@ module zbc #(parameter WIDTH=32) ( bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); - //NOTE: Optimize this when doing decoder stuff. + // zbc input select mux always_comb begin casez (Funct3[1:0]) 2'b01: begin //clmul From 11a977ffe3ea79ed00b19b784263177b22e48704 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:09:55 -0800 Subject: [PATCH 121/183] added bitmanip illegal instruction signal --- src/ieu/bmu/bmuctrl.sv | 115 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 ++- 2 files changed, 64 insertions(+), 59 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e838c6ea..145b2513 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -41,6 +41,7 @@ module bmuctrl( output logic BRegWriteD, // Indicates if it is a R type B instruction output logic BW64D, // Indiciates if it is a W type B instruction output logic BALUOpD, // Indicates if it is an ALU B instruction + output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -54,7 +55,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 13 + `define BMUCTRLW 14 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -70,92 +71,92 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // minu - default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {10'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 6911f75e..eaf28989 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -116,6 +116,7 @@ module controller( logic IEURegWriteE; // Register write logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers + logic IllegalBitmanipInstrD; // Unrecognized B instruction logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE, FenceM; // Fence instruction logic SFenceVmaD; // sfence.vma instruction @@ -191,7 +192,8 @@ module controller( // Squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; - assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD; + assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal + //assign IllegalBaseInstrD = 1'b0; assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; @@ -243,7 +245,7 @@ module controller( assign sraD = (Funct3D == 3'b101 & Funct7D[5]); if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand @@ -262,6 +264,8 @@ module controller( assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; + + assign IllegalBitmanipInstrD = 1'b1; end // Fences From d0c486df5449c7d1a2b78ceb444a18a843c689ac Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:28:33 -0800 Subject: [PATCH 122/183] removed main instruction decoder dependence on bmu controller --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index eaf28989..324b255b 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -162,14 +162,14 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBB_SUPPORTED & BSelectD[2]) | (`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2]))) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3]) | (`ZBB_SUPPORTED & BSelectD[2])) & `XLEN == 64) + 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide From 2a0c59d5a7ac5628d0b12f6ddeb95e586313d87c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:28:43 -0800 Subject: [PATCH 123/183] formatting --- src/ieu/alu.sv | 10 +++++----- src/ieu/bmu/bmuctrl.sv | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4cf8d6ed..a22a3a02 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -58,15 +58,18 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux - assign shASelect = {W64,SubArith}; + // Extract control signals from ALUControl. + assign {W64, SubArith, ALUOp} = ALUControl; + + // Pack control signals into shifter select + assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; - // Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb @@ -99,9 +102,6 @@ module alu #(parameter WIDTH=32) ( assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? end else assign Rotate = 1'b0; - // Extract control signals from ALUControl. - assign {W64, SubArith, ALUOp} = ALUControl; - // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 145b2513..9b3e3a97 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -69,7 +69,7 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) From f4b8968e12e072637dc8707ccb863cd9d5d8de65 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 16:00:56 -0800 Subject: [PATCH 124/183] bug fix, more elegant logic changes in controller --- src/ieu/controller.sv | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 324b255b..e41a73ad 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -91,6 +91,8 @@ module controller( logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) + logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically + logic BaseRegWriteD; // Indicates if Base instruction register write instruction logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -137,7 +139,7 @@ module controller( // Main Instruction Decoder always_comb case(OpD) - // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal + // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported @@ -194,9 +196,14 @@ module controller( assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal //assign IllegalBaseInstrD = 1'b0; - assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, - ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, + assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, + ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; + + // If either bitmanip signal or base instruction signal + assign ALUOpD = BaseALUOpD | BALUOpD; + assign RegWriteD = BaseRegWriteD | BRegWriteD; + assign W64D = BaseW64D | BW64D; assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? @@ -243,13 +250,13 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign ALUControlD = {W64D, SubArithD, ALUOpD}; + // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); - assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers - assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand - assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; + assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -261,9 +268,7 @@ module controller( assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; - assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); - assign ALUControlD = {W64D, SubArithD, ALUOpD}; assign IllegalBitmanipInstrD = 1'b1; end @@ -302,6 +307,7 @@ module controller( // Other execute stage controller signals assign MemReadE = MemRWE[1]; assign SCE = (ResultSrcE == 3'b100); + assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign IntDivE = MDUE & Funct3E[2]; // Integer division operation // Memory stage pipeline control register From b5a5f364e11c43f5c92aca7d808cfbfea09d01e2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:27:11 -0800 Subject: [PATCH 125/183] began subarith configurability optimization in controller --- src/ieu/controller.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e41a73ad..0e5f3079 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -93,6 +93,7 @@ module controller( logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically logic BaseRegWriteD; // Indicates if Base instruction register write instruction + logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -106,7 +107,7 @@ module controller( logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals - logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu + logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic bclrD, bextD; // Indicates if is one of these instructions logic andnD, ornD, xnorD; // Indicates if is one of these instructions @@ -128,6 +129,7 @@ module controller( logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage logic BW64D; // Indiciates if it is a W type B instruction in decode stage logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage + logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor // Extract fields @@ -250,6 +252,7 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; // BITMANIP Configuration Block @@ -267,6 +270,7 @@ module controller( assign BW64D = 1'b0; assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; + assign BSubArithD = 1'b0; assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); From 11f165d1bb281afb9b0dba5acacf089fbbdde0ba Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:40:29 -0800 Subject: [PATCH 126/183] migrated B-subarith logic into b controller --- src/ieu/bmu/bmuctrl.sv | 117 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 +-- 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 9b3e3a97..2a4a450e 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -41,6 +41,7 @@ module bmuctrl( output logic BRegWriteD, // Indicates if it is a R type B instruction output logic BW64D, // Indiciates if it is a W type B instruction output logic BALUOpD, // Indicates if it is an ALU B instruction + output logic BSubArithD, // Indicates if Bitmanip SubArith flag should be on output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage @@ -55,7 +56,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 14 + `define BMUCTRLW 15 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -69,94 +70,94 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu - default: BMUControlsD = {Funct3D, {10'b0}, {1'b1}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0e5f3079..2cee4183 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -206,6 +206,7 @@ module controller( assign ALUOpD = BaseALUOpD | BALUOpD; assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; + assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? @@ -252,14 +253,14 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand + assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); - assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand + //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -272,7 +273,6 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign IllegalBitmanipInstrD = 1'b1; end From 2b9a6aba915f3415ed15bac4909304980766a219 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:41:47 -0800 Subject: [PATCH 127/183] comments to bctrl --- src/ieu/bmu/bmuctrl.sv | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 2a4a450e..527a2428 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -35,14 +35,14 @@ module bmuctrl( // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage - output logic [2:0] ALUSelectD, // ALU Mux select signal + output logic [2:0] ALUSelectD, // ALU Mux select signal in Decode Stage output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? - output logic BRegWriteD, // Indicates if it is a R type B instruction - output logic BW64D, // Indiciates if it is a W type B instruction - output logic BALUOpD, // Indicates if it is an ALU B instruction - output logic BSubArithD, // Indicates if Bitmanip SubArith flag should be on - output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction + output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage + output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage + output logic BALUOpD, // Indicates if it is an ALU B instruction in Decode Stage + output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage + output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -156,7 +156,6 @@ module bmuctrl( endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; From 77c9114bcc298d59fa10d8775745064b8397310d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:45:42 -0800 Subject: [PATCH 128/183] removed outdated b-signals in controller --- src/ieu/controller.sv | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2cee4183..f8b0d983 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -109,8 +109,6 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions - logic bclrD, bextD; // Indicates if is one of these instructions - logic andnD, ornD, xnorD; // Indicates if is one of these instructions logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs @@ -222,27 +220,13 @@ module controller( assign sltD = (Funct3D == 3'b010); end - if (`ZBS_SUPPORTED) begin - assign bclrD = (ALUSelectD == 3'b111 & BSelectD[0]); - assign bextD = (ALUSelectD == 3'b101 & BSelectD[0]); - end else begin - assign bclrD = 1'b0; - assign bextD = 1'b0; - end - if (`ZBB_SUPPORTED) begin - assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]); - assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]); - assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]); // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator. assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]); assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]); assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]); assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]); end else begin - assign andnD = 0; - assign ornD = 0; - assign xnorD = 0; assign maxE = 0; assign maxuE = 0; assign minE = 0; From d24f74dc4b55974a9e20d4d0831da421e926cd4b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 12:35:40 -0800 Subject: [PATCH 129/183] sltD logic optimize --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e20d29ae..4c8376d7 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -216,7 +216,7 @@ module controller( //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb - assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); + assign sltD = (Funct3D == 3'b010 & ~(Funct7D[4])); end else begin assign sltD = (Funct3D == 3'b010); end From 0bb75132c6a2ddcbd75ca7d63f9527aac93e3cb4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 12:44:33 -0800 Subject: [PATCH 130/183] sltD signal debug. Passes regression --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4c8376d7..ec54394e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -215,8 +215,8 @@ module controller( //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin - // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb - assign sltD = (Funct3D == 3'b010 & ~(Funct7D[4])); + // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw + assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; end else begin assign sltD = (Funct3D == 3'b010); end From 448e950ebad05acca284c949b98708625447e79b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 17:12:29 -0800 Subject: [PATCH 131/183] b controller generates comparison signed flag and controller branch signed logic updated accordingly --- src/ieu/bmu/bmuctrl.sv | 9 +++++++-- src/ieu/controller.sv | 11 +++++++---- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 527a2428..3ee6c42e 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -48,13 +48,15 @@ module bmuctrl( output logic [2:0] ALUSelectE, output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal - output logic BRegWriteE // Indicates if it is a R type B instruction in Execute + output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute + output logic BComparatorSignedE // Indicates if comparator signed in Execute Stage ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage + logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage `define BMUCTRLW 15 @@ -158,8 +160,11 @@ module bmuctrl( // Unpack Control Signals assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; + // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches + assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; + // BMU Execute stage pipieline control register - flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE}); + flopenrc#(12) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index ec54394e..9ea091e3 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -126,9 +126,10 @@ module controller( logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage - logic BW64D; // Indiciates if it is a W type B instruction in decode stage + logic BW64D; // Indicates if it is a W type B instruction in decode stage logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor + logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage // Extract fields @@ -243,7 +244,8 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE); + //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi @@ -257,6 +259,7 @@ module controller( assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; + assign BComparatorSignedE = 1'b0; assign IllegalBitmanipInstrD = 1'b1; @@ -286,8 +289,8 @@ module controller( // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE // Hence, only eq and lt flags are needed - assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & ~BSelectE[2]) | (`ZBB_SUPPORTED & (maxE | minE)) ; - //assign BranchSignedE = ~(Funct3E[2:1] == 2'b11); + // We also want comparator to handle signed comparison on a max/min bitmanip instruction + assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE ; assign {eqE, ltE} = FlagsE; mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE); assign BranchTakenE = BranchFlagE ^ Funct3E[0]; From efce306aabca1d85f84d2828199fed877c68ddc5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 21:52:25 -0800 Subject: [PATCH 132/183] removed redundant signals in controller --- src/ieu/controller.sv | 31 +++++++++---------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 9ea091e3..b76421d4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // controller.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu // Created: 9 January 2021 -// Modified: +// Modified: 3 March 2023 // // Purpose: Top level controller module // @@ -110,7 +110,6 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions - logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -215,25 +214,8 @@ module controller( assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i //NOTE: Move the B conditional logic into bctrl - if (`ZBA_SUPPORTED) begin - // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw - assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; - end else begin - assign sltD = (Funct3D == 3'b010); - end + - if (`ZBB_SUPPORTED) begin - // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator. - assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]); - assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]); - assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]); - assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]); - end else begin - assign maxE = 0; - assign maxuE = 0; - assign minE = 0; - assign minuE = 0; - end // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); @@ -245,7 +227,10 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE); - + if (`ZBA_SUPPORTED) begin + // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw + assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; + end else assign sltD = (Funct3D == 3'b010); //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi @@ -261,6 +246,8 @@ module controller( assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; + assign sltD = (Funct3D == 3'b010); + assign IllegalBitmanipInstrD = 1'b1; end From 18ab538a5e4825b54baef64465bee0c1c63e9fe6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 21:52:34 -0800 Subject: [PATCH 133/183] license comments --- src/ieu/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index a22a3a02..9843cea6 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // alu.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu // Created: 9 January 2021 -// Modified: +// Modified: 3 March 2023 // // Purpose: RISC-V Arithmetic/Logic Unit // From 6e52113208ae1a556aec72ad659ce79e7992d40e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 22:57:49 -0800 Subject: [PATCH 134/183] Rotate signal now gets generated in bmu ctrl --- src/ieu/alu.sv | 6 +- src/ieu/bmu/bmuctrl.sv | 123 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 +-- src/ieu/datapath.sv | 3 +- src/ieu/ieu.sv | 7 ++- 5 files changed, 72 insertions(+), 75 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9843cea6..3e564226 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,6 +37,7 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags + input logic Rotate, // Perform Rotate Operation output logic [WIDTH-1:0] ALUResult, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -53,7 +54,6 @@ module alu #(parameter WIDTH=32) ( logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic Rotate; logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux @@ -98,10 +98,6 @@ module alu #(parameter WIDTH=32) ( endcase end else assign CondShiftA = A; - if (`ZBB_SUPPORTED) begin: rotatelogic - assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? - end else assign Rotate = 1'b0; - // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 3ee6c42e..8fe3cb75 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -49,7 +49,8 @@ module bmuctrl( output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute - output logic BComparatorSignedE // Indicates if comparator signed in Execute Stage + output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage + output logic RotateE // Indiciates if rotate instruction in Execute Stage ); logic [6:0] OpD; // Opcode in Decode stage @@ -57,8 +58,9 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage + logic RotateD; // Indicates if rotate instruction in Decode Stage - `define BMUCTRLW 15 + `define BMUCTRLW 16 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -72,93 +74,92 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu - - default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // minu + default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, IllegalBitmanipInstrD} = BMUControlsD; // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; @@ -166,5 +167,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(12) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE}); + flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, RotateD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, RotateE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index b76421d4..b2e21ebf 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -60,6 +60,7 @@ module controller( output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage + output logic RotateE, // Indicates if rotate instruction in Execute Stage // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -129,7 +130,6 @@ module controller( logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage - // Extract fields assign OpD = InstrD[6:0]; @@ -213,9 +213,6 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - //NOTE: Move the B conditional logic into bctrl - - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); @@ -226,7 +223,7 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .RotateE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -245,6 +242,7 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; + assign RotateE = 1'b0; assign sltD = (Funct3D == 3'b010); diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 9f09efe7..19057fcb 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -48,6 +48,7 @@ module datapath ( input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal + input logic RotateE, // Indicates if Rotate instruction in Execute Stage output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -112,7 +113,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, RotateE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index e26622f9..88a83ea6 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -86,7 +86,8 @@ module ieu ( logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - logic [2:0] ZBBSelectE; + logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage + logic RotateE; // Indicates if Rotate Instruction in Execute Stage // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -100,7 +101,7 @@ controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD); @@ -108,7 +109,7 @@ controller c( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From b6dd8553957824d96d05171009dc89e98fe7869e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 09:22:21 -0800 Subject: [PATCH 135/183] zbc result mux is now structural --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 011af80e..74b2f64b 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -66,7 +66,7 @@ module zbc #(parameter WIDTH=32) ( clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult; + mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult); endmodule \ No newline at end of file From 6295178073c4a866d6589c2eb095ff8df7de0400 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 22:44:03 -0800 Subject: [PATCH 136/183] removed rotate signal in datapath and instead packed into the new BALUControl Signal - BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU --- src/ieu/alu.sv | 30 ++++++---- src/ieu/bmu/bmuctrl.sv | 130 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 7 ++- src/ieu/datapath.sv | 6 +- src/ieu/ieu.sv | 8 +-- 5 files changed, 96 insertions(+), 85 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3e564226..dea87022 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -30,16 +30,16 @@ `include "wally-config.vh" module alu #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [2:0] ALUSelect, // ALU mux select signal - input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect - input logic [1:0] CompFlags, // Comparator flags - input logic Rotate, // Perform Rotate Operation - output logic [WIDTH-1:0] ALUResult, // ALU result - output logic [WIDTH-1:0] Sum); // Sum of operands + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [2:0] ALUSelect, // ALU mux select signal + input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [1:0] CompFlags, // Comparator flags + input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + output logic [WIDTH-1:0] ALUResult, // ALU result + output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. @@ -57,17 +57,23 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux + logic Rotate; // Indicates if it is Rotate instruction + logic Mask; // Indicates if it is ZBS instruction + logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + // Extract control signals from bitmanip ALUControl. + assign {Rotate, Mask, PreShift} = BALUControl; + // Pack control signals into shifter select assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); - assign CondMaskB = (BSelect[0]) ? MaskB : B; + assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; // Sign/Zero extend mux @@ -90,7 +96,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift Mux always_comb - case (Funct3[2:1] & {2{BSelect[3]}}) + case (Funct3[2:1] & {2{PreShift}}) 2'b00: CondShiftA = shA[WIDTH-1:0]; 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 8fe3cb75..b9fb539a 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// controller.sv +// bmuctrl.sv // // Written: Kevin Kim // Created: 16 February 2023 // Modified: // -// Purpose: Top level B instrution controller module +// Purpose: Top level B instruction decoder // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // @@ -50,7 +50,8 @@ module bmuctrl( output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage - output logic RotateE // Indiciates if rotate instruction in Execute Stage + output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage + ); logic [6:0] OpD; // Opcode in Decode stage @@ -59,8 +60,10 @@ module bmuctrl( logic [4:0] Rs2D; // Rs2 source register in Decode stage logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage logic RotateD; // Indicates if rotate instruction in Decode Stage - - `define BMUCTRLW 16 + logic MaskD; // Indicates if zbs instruction in Decode Stage + logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage + logic [2:0] BALUControlD; // ALU Control signals for B instructions + `define BMUCTRLW 18 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -74,92 +77,93 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // minu - default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // maxu + default: BMUControlsD = {Funct3D, {14'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; + + // Pack BALUControl Signals + assign BALUControlD = {RotateD, MaskD, PreShiftD}; // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; @@ -167,5 +171,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, RotateD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, RotateE}); + flopenrc#(15) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index b2e21ebf..0486ff21 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -60,7 +60,8 @@ module controller( output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage - output logic RotateE, // Indicates if rotate instruction in Execute Stage + output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage + // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -223,7 +224,7 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .RotateE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -242,7 +243,7 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; - assign RotateE = 1'b0; + assign BALUControlE = 3'b0; assign sltD = (Funct3D == 3'b010); diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 19057fcb..dd93e71d 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -48,7 +48,7 @@ module datapath ( input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal - input logic RotateE, // Indicates if Rotate instruction in Execute Stage + input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -60,7 +60,7 @@ module datapath ( output logic [`XLEN-1:0] WriteDataM, // Write data in Memory stage // Writeback stage signals input logic StallW, FlushW, // Stall, flush Writeback stage - input logic RegWriteW, IntDivW, // Write register file, integer divide instruction + input logic RegWriteW, IntDivW, // Write register file, integer divide instruction input logic SquashSCW, // Squash a store conditional when a conflict arose input logic [2:0] ResultSrcW, // Select source of result to write back to register file input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result @@ -113,7 +113,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, RotateE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 88a83ea6..39bd36e6 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -72,7 +72,7 @@ module ieu ( output logic MDUStallD, CSRRdStallD, StoreStallD, output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions - output logic FenceM + output logic FenceM ); logic [2:0] ImmSrcD; // Select type of immediate extension @@ -87,7 +87,7 @@ module ieu ( logic IntDivW; // Integer divide instruction logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage - logic RotateE; // Indicates if Rotate Instruction in Execute Stage + logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -101,7 +101,7 @@ controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD); @@ -109,7 +109,7 @@ controller c( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .RotateE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From b0f152de28b01bb891f1de91835ff015579d5fe2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 22:54:32 -0800 Subject: [PATCH 137/183] added python script -I've been using this python script to make quick changes to the bitmanip controller --- src/ieu/bmu/bitfieldedit.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/ieu/bmu/bitfieldedit.py diff --git a/src/ieu/bmu/bitfieldedit.py b/src/ieu/bmu/bitfieldedit.py new file mode 100644 index 00000000..a9f604a3 --- /dev/null +++ b/src/ieu/bmu/bitfieldedit.py @@ -0,0 +1,32 @@ +""" + bitfieldedit.py + Script that appends 0 just before the "illegal instruction" field of the bitstring + Written by Kevin Kim +""" +def addZero(s): + try: + indexSemicolon = s.index(";") + newS = s[:indexSemicolon-1]+"0_"+s[indexSemicolon-1:] + return newS + except: return s + +def main(): + filename = input("Enter full filename: ") + n1 = int(input("Line number to begin: ")) + n2 = int(input("Line number to end: ")) + f = open(filename, "r") + flines = f.readlines() + + #create list of lines from line n1 to n2, inclusive + lines = flines[(n1-1):(n2-1)] + + #string to be printed + out = "" + + for i in range(len(lines)): + lines[i] = addZero(lines[i]) + out += lines[i] + print(out) + +if __name__ == "__main__": + main() \ No newline at end of file From 4b1ee5a19629de1a1f3fa1793471ff596ba2b8e7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 23:07:06 -0800 Subject: [PATCH 138/183] alu pre-shift -changed ALU pre shift logic to use a 2 bit shifter instead of mux --- src/ieu/alu.sv | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index dea87022..96751be8 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -94,14 +94,8 @@ module alu #(parameter WIDTH=32) ( end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes - // Pre-Shift Mux - always_comb - case (Funct3[2:1] & {2{PreShift}}) - 2'b00: CondShiftA = shA[WIDTH-1:0]; - 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add - 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add - 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add - endcase + // Pre-Shift + assign CondShiftA = shA[WIDTH-1:0] << (Funct3[2:1] & {2{PreShift}}); end else assign CondShiftA = A; // Addition From 6ead150cb1382970779befbf4f22c35dfa94ba18 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 23:19:31 -0800 Subject: [PATCH 139/183] BSelect from OH encoding to Binary --- src/ieu/alu.sv | 13 +++-- src/ieu/bmu/bmuctrl.sv | 114 ++++++++++++++++++++--------------------- src/ieu/controller.sv | 8 +-- src/ieu/datapath.sv | 2 +- src/ieu/ieu.sv | 2 +- 5 files changed, 69 insertions(+), 70 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 96751be8..565d30d2 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,7 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal - input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags @@ -167,12 +167,11 @@ module alu #(parameter WIDTH=32) ( if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb case (BSelect) - //ZBA_ZBB_ZBC_ZBS - 4'b0001: ALUResult = FullResult; - 4'b0010: ALUResult = ZBCResult; - 4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. - 4'b0100: ALUResult = ZBBResult; - default: ALUResult = CondExtFullResult; + // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC + 2'b00: ALUResult = CondExtFullResult; + 2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 2'b10: ALUResult = ZBBResult; + 2'b11: ALUResult = ZBCResult; endcase end else assign ALUResult = CondExtFullResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b9fb539a..6bac07d9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,7 +36,7 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal in Decode Stage - output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage @@ -46,7 +46,7 @@ module bmuctrl( // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, - output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage @@ -63,7 +63,7 @@ module bmuctrl( logic MaskD; // Indicates if zbs instruction in Decode Stage logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions - `define BMUCTRLW 18 + `define BMUCTRLW 16 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -79,84 +79,84 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0_0_0; // xnor + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_10_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_10_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_10_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // maxu - default: BMUControlsD = {Funct3D, {14'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu + default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals @@ -171,5 +171,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(15) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); + flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0486ff21..ce853aee 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -58,7 +58,7 @@ module controller( output logic BranchE, // Branch instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction + output logic [1:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage @@ -124,7 +124,7 @@ module controller( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction - logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage + logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage logic BW64D; // Indicates if it is a W type B instruction in decode stage @@ -234,8 +234,8 @@ module controller( end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign BSelectE = 4'b0000; - assign BSelectD = 4'b0000; + assign BSelectE = 2'b00; + assign BSelectD = 2'b00; assign ZBBSelectE = 3'b000; assign BRegWriteD = 1'b0; assign BW64D = 1'b0; diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index dd93e71d..dc9a0289 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -46,7 +46,7 @@ module datapath ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [1:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 39bd36e6..b5fa4517 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -85,7 +85,7 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction - logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [1:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage From 3d5ee8d96444d98216a1cb3ce73eb7c5dd95be75 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 23:56:33 -0800 Subject: [PATCH 140/183] bug in bctrl - deleted the min/minu decoding for some reason. --- src/ieu/bmu/bmuctrl.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 6bac07d9..a3ed483a 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -156,6 +156,8 @@ module bmuctrl( 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // minu default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase From 0e6ea0ee608551b0eebf5f7e378a3f92880174ed Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:06:24 -0800 Subject: [PATCH 141/183] ALU changes - added PreShiftAmt signal for shadd - condinvB now muxes from B instead of mask --- src/ieu/alu.sv | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 565d30d2..5ee0f900 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,11 +43,12 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux logic [WIDTH-1:0] CondZextA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -60,6 +61,7 @@ module alu #(parameter WIDTH=32) ( logic Rotate; // Indicates if it is Rotate instruction logic Mask; // Indicates if it is ZBS instruction logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic [1:0] PreShiftAmt; // Amount to Pre-Shift A // Extract control signals from ALUControl. @@ -71,6 +73,8 @@ module alu #(parameter WIDTH=32) ( // Pack control signals into shifter select assign shASelect = {W64,SubArith}; + assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; + if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); assign CondMaskB = (Mask) ? MaskB : B; @@ -80,10 +84,10 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb case (shASelect) - 2'b00: shA = {{1'b0}, A}; - 2'b01: shA = {A[63], A}; - 2'b10: shA = {{33'b0}, A[31:0]}; - 2'b11: shA = {{33{A[31]}}, A[31:0]}; + 2'b00: shA = {{1'b0}, A}; // zero-extend double-word (srl) + 2'b01: shA = {A[63], A}; // sign-extend double-word (sra) + 2'b10: shA = {{33'b0}, A[31:0]}; // zero-extend word (add.uw, shadd.uw, srlw) + 2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw) endcase end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions @@ -95,11 +99,12 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift - assign CondShiftA = shA[WIDTH-1:0] << (Funct3[2:1] & {2{PreShift}}); + assign CondShiftA = shA[WIDTH-1:0] << (PreShiftAmt); end else assign CondShiftA = A; // Addition - assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; + assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; + assign CondInvB = SubArith ? ~B : B; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) @@ -128,9 +133,9 @@ module alu #(parameter WIDTH=32) ( 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ CondInvB; // xor, xnor, binv - 3'b110: FullResult = A | CondInvB; // or, orn, bset - 3'b111: FullResult = A & CondInvB; // and, bclr + 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv + 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset + 3'b111: FullResult = A & CondMaskInvB; // and, bclr 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase end @@ -154,13 +159,16 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign CondExtFullResult = FullResult; + if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse + bitreverse #(WIDTH) brA(.a(A), .b(RevA)); + end //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + zbc #(WIDTH) ZBC(.A(A), .RevA(RevA), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux From 869e812aa856922fd54d163846d7b460724656a6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:26:24 -0800 Subject: [PATCH 142/183] revA signals to cnt, zbb --- src/ieu/bmu/cnt.sv | 3 ++- src/ieu/bmu/zbb.sv | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 32be6b2e..b5096a81 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -31,7 +31,8 @@ `include "wally-config.vh" module cnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, RevA, // Operands + input logic [4:0] B, // Last 5 bits of immediate input logic W64, // Indicates word operation output logic [WIDTH-1:0] CntResult // count result ); diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 13529d6a..1c2ae6bc 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -31,14 +31,13 @@ `include "wally-config.vh" module zbb #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, RevA, B, // Operands input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic lt, // lt flag input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result - // count result logic [WIDTH-1:0] CntResult; @@ -53,7 +52,8 @@ module zbb #(parameter WIDTH=32) ( // sign/zero extend results logic [WIDTH-1:0] ExtResult; // sign/zero extend result - cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); + + cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); From 3656d42ac0f32f5b74b1594989dd196e71221f7d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:26:31 -0800 Subject: [PATCH 143/183] zbc input mux structural --- src/ieu/bmu/zbc.sv | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 74b2f64b..fc4b17b7 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -30,39 +30,22 @@ `include "wally-config.vh" module zbc #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform - output logic [WIDTH-1:0] ZBCResult); // ZBC result + input logic [WIDTH-1:0] A, RevA, B, // Operands + input logic [2:0] Funct3, // Indicates operation to perform + output logic [WIDTH-1:0] ZBCResult); // ZBC result logic [WIDTH-1:0] ClmulResult, RevClmulResult; - logic [WIDTH-1:0] RevA, RevB; + logic [WIDTH-1:0] RevB; logic [WIDTH-1:0] x,y; + logic [1:0] select; + + assign select = ~Funct3[1:0]; - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); - // zbc input select mux - always_comb begin - casez (Funct3[1:0]) - 2'b01: begin //clmul - x = A; - y = B; - end - 2'b11: begin //clmulh - x = {RevA[WIDTH-2:0], {1'b0}}; - y = {{1'b0}, RevB[WIDTH-2:0]}; - end - 2'b10: begin //clmulr - x = RevA; - y = RevB; - end - default: begin - x = 0; - y = 0; - end - endcase - - end + + mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, select, x); + mux3 #(WIDTH) ymux({{1'b0},RevB[WIDTH-2:0]}, RevB, B, select, y); clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); From 7531bf1fd6b3d40c6608b0e0be0b7acd281c105f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:57:30 -0800 Subject: [PATCH 144/183] zbb result select mux structural --- src/ieu/bmu/bmuctrl.sv | 40 ++++++++++++++++++++-------------------- src/ieu/bmu/zbb.sv | 23 ++--------------------- 2 files changed, 22 insertions(+), 41 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index a3ed483a..d57aecfd 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -116,48 +116,48 @@ module bmuctrl( 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // roriw else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // sign extend instruction else BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv32) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_10_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_10_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_10_111_1_0_1_1_0_0_0_0; // xnor + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv32) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // minu + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // minu default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1c2ae6bc..fc191874 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -61,27 +61,8 @@ module zbb #(parameter WIDTH=32) ( assign MaxResult = (lt) ? B : A; assign MinResult = (lt) ? A : B; - //can replace with structural mux by looking at bit 4 in rs2 field - always_comb begin - case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn - 3'b000: ZBBResult = CntResult; // count - 3'b100: ZBBResult = ExtResult; // sign/zero extend - 3'b011: ZBBResult = ByteResult; // byte instructions - 3'b110: ZBBResult = MinResult; // min, minu - 3'b101: ZBBResult = MaxResult; // max, maxu - /*15'b0010100_101_00111: ZBBResult = OrcBResult; - 15'b0110100_101_11000: ZBBResult = Rev8Result; - 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110000_001_00000: ZBBResult = czResult; - 15'b0110000_001_00010: ZBBResult = cpopResult; - 15'b0110000_001_00001: ZBBResult = czResult; - 15'b0000100_100_00000: ZBBResult = zexthResult; - 15'b0110000_001_00100: ZBBResult = sextbResult; - 15'b0110000_001_00101: ZBBResult = sexthResult;*/ - default: ZBBResult = {(WIDTH){1'b0}}; - endcase - end + // ZBB Result select mux + mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); endmodule \ No newline at end of file From 19beed786638bb9f1b4c935b706c697702c9a695 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 15:09:02 -0800 Subject: [PATCH 145/183] extend unit structural mux --- src/ieu/bmu/ext.sv | 12 ++++-------- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 05cb24c0..346b7811 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -31,21 +31,17 @@ `include "wally-config.vh" module ext #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, // Operands + input logic [1:0] ExtSelect, // B[2], B[0] of immediate output logic [WIDTH-1:0] ExtResult); // Extend Result logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; + assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]}; assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; - always_comb - case({B[2],B[0]}) - 2'b00: ExtResult = zexthResult; - 2'b10: ExtResult = sextbResult; - 2'b11: ExtResult = sexthResult; - default: ExtResult = 0; - endcase + mux3 #(WIDTH) extmux(zexthResult, sextbResult, sexthResult, ExtSelect, ExtResult); endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index fc191874..65414629 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -55,7 +55,7 @@ module zbb #(parameter WIDTH=32) ( cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); - ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); + ext #(WIDTH) ext(.A(A), .ExtSelect({B[2], B[0]}), .ExtResult(ExtResult)); assign MaxResult = (lt) ? B : A; From cec1e89c786b40a9c8887b85f91bb6cd14efb510 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 15:20:48 -0800 Subject: [PATCH 146/183] bug fix --- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 346b7811..0b410327 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -41,7 +41,7 @@ module ext #(parameter WIDTH = 32) ( assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; - mux3 #(WIDTH) extmux(zexthResult, sextbResult, sexthResult, ExtSelect, ExtResult); + mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult); endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 65414629..f4b7eead 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -55,7 +55,7 @@ module zbb #(parameter WIDTH=32) ( cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); - ext #(WIDTH) ext(.A(A), .ExtSelect({B[2], B[0]}), .ExtResult(ExtResult)); + ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); assign MaxResult = (lt) ? B : A; From 288c7ad48c6cd7766980fec548fc499173138e01 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 05:41:53 -0800 Subject: [PATCH 147/183] updated license header --- src/ieu/bmu/bitreverse.sv | 4 ++-- src/ieu/bmu/bmuctrl.sv | 4 ++-- src/ieu/bmu/byte.sv | 6 +++--- src/ieu/bmu/clmul.sv | 4 ++-- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/bmu/zbb.sv | 4 ++-- src/ieu/bmu/zbc.sv | 4 ++-- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 5d195d24..559bb0c0 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -4,9 +4,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: Bit reverse submodule // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d57aecfd..3675a711 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -3,9 +3,9 @@ // // Written: Kevin Kim // Created: 16 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Top level B instruction decoder +// Purpose: Top level bit manipulation instruction decoder // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 2b98b83d..19b71fc1 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// clmul.sv +// byte.sv // // Written: Kevin Kim // Created: 1 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: RISCV bitmanip byte-wise operation unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 46893573..16d600b4 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// clmul.sv (carry-less multiplier) +// clmul.sv // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 // Modified: // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: Carry-Less multiplication unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 0b410327..3a832de6 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// -// cnt.sv +// ext.sv // // Written: Kevin Kim // Created: 4 February 2023 diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index c82476a6..544c1344 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// -// +// popccnt.sv // Written: Kevin Kim // Modified: 2/4/2023 // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index f4b7eead..54459db8 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -4,9 +4,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 2 February 2023 -// Modified: +// Modified: March 6 2023 // -// Purpose: RISC-V miscellaneous bit manipulation unit (subset of ZBB instructions) +// Purpose: RISC-V ZBB top level unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index fc4b17b7..c1ed706b 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -3,9 +3,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 2 February 2023 -// Modified: +// Modified: 3 March 2023 // -// Purpose: RISC-V single bit manipulation unit (ZBC instructions) +// Purpose: RISC-V ZBC top-level unit // // Documentation: RISC-V System on Chip Design Chapter *** // From 474b69967a13653709a765946b4c0942a6af1b1e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 05:52:08 -0800 Subject: [PATCH 148/183] formatted files --- src/ieu/bmu/bitreverse.sv | 1 - src/ieu/bmu/bmuctrl.sv | 6 ++---- src/ieu/bmu/ext.sv | 2 -- src/ieu/bmu/popcnt.sv | 2 -- src/ieu/bmu/zbb.sv | 21 ++++----------------- src/ieu/bmu/zbc.sv | 5 ++--- src/ieu/shifter.sv | 1 - 7 files changed, 8 insertions(+), 30 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 559bb0c0..644783e5 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -37,7 +37,6 @@ module bitreverse #(parameter WIDTH=32) ( for (i=0; i Date: Mon, 6 Mar 2023 06:19:01 -0800 Subject: [PATCH 149/183] formatting - reverted back to ALUResult signal in alu.sv --- src/ieu/alu.sv | 21 +++++++++++---------- src/ieu/bmu/bmuctrl.sv | 2 -- src/ieu/controller.sv | 3 +-- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 5ee0f900..11fab86e 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -38,12 +38,13 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - output logic [WIDTH-1:0] ALUResult, // ALU result + output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -156,8 +157,8 @@ module alu #(parameter WIDTH=32) ( // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign CondExtFullResult = FullResult; + if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.a(A), .b(RevA)); @@ -168,7 +169,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -176,10 +177,10 @@ module alu #(parameter WIDTH=32) ( always_comb case (BSelect) // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC - 2'b00: ALUResult = CondExtFullResult; - 2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. - 2'b10: ALUResult = ZBBResult; - 2'b11: ALUResult = ZBCResult; + 2'b00: Result = ALUResult; + 2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 2'b10: Result = ZBBResult; + 2'b11: Result = ZBCResult; endcase - end else assign ALUResult = CondExtFullResult; + end else assign Result = ALUResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ef9d2bb8..f4001456 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -29,7 +29,6 @@ `include "wally-config.vh" -// NOTE: DO we want to make this XLEN parameterized? module bmuctrl( input logic clk, reset, // Decode stage control signals @@ -51,7 +50,6 @@ module bmuctrl( output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage - ); logic [6:0] OpD; // Opcode in Decode stage diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index ce853aee..386ca228 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -222,7 +222,7 @@ module controller( assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; - // BITMANIP Configuration Block + // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin @@ -247,7 +247,6 @@ module controller( assign sltD = (Funct3D == 3'b010); - assign IllegalBitmanipInstrD = 1'b1; end From 45697f050d7bb3b439035fc36c312eb8ba25875c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 06:20:25 -0800 Subject: [PATCH 150/183] formatting --- src/ieu/alu.sv | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 11fab86e..eb7e9f3a 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -64,7 +64,6 @@ module alu #(parameter WIDTH=32) ( logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction logic [1:0] PreShiftAmt; // Amount to Pre-Shift A - // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -152,18 +151,12 @@ module alu #(parameter WIDTH=32) ( 3'b110: FullResult = A | B; // or 3'b111: FullResult = A & B; // and endcase - end - - - // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.a(A), .b(RevA)); end - //NOTE: This looks good and can be merged. + if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .RevA(RevA), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; @@ -171,7 +164,11 @@ module alu #(parameter WIDTH=32) ( if (`ZBB_SUPPORTED) begin: zbb zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; - + + // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits + if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; + // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb From 4a31ab1bc3bf129b43ad7fa4d2226227fe94e509 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 06:44:15 -0800 Subject: [PATCH 151/183] structural changes in cnt.sv --- src/ieu/bmu/cnt.sv | 41 +++++++---------------------------------- 1 file changed, 7 insertions(+), 34 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index b5096a81..1e3120e1 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -41,52 +41,25 @@ module cnt #(parameter WIDTH = 32) ( logic [WIDTH-1:0] czResult; // count zeros result logic [WIDTH-1:0] cpopResult; // population count result logic [WIDTH-1:0] lzcA, popcntA; - logic [WIDTH-1:0] revA; - //in both rv64, rv32 - bitreverse #(WIDTH) brtz(.a(A), .b(revA)); - //only in rv64 if (WIDTH==64) begin - //NOTE: signal widths can be decreased - always_comb begin - //clz input select mux - case({B[4:0],W64}) - 6'b00000_0: lzcA = A; //clz - 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw - 6'b00001_0: lzcA = revA; //ctz - 6'b00001_1: lzcA = {revA[63:32],{32{1'b1}}}; //ctzw - default: lzcA = A; - endcase - - //cpop select mux - case ({B[4:0],W64}) - 6'b00010_0: popcntA = A; - 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; - default: popcntA = A; - endcase - end + //clz input select mux + mux4 #(WIDTH) lzcmux64(A, {A[31:0],{32{1'b1}}}, RevA, {RevA[63:32],{32{1'b1}}}, {B[0],W64}, lzcA); + //cpop select mux + mux2 #(WIDTH) popcntmux64(A, {{32{1'b0}}, A[31:0]}, W64, popcntA); end + //rv32 else begin - //rv32 assign popcntA = A; - always_comb begin - //clz input slect mux - case(B[4:0]) - 5'b00000: lzcA = A; - 5'b00001: lzcA = revA; - default: lzcA = A; - endcase - end + mux2 #(WIDTH) lzcmux32(A, RevA, B[0], lzcA); end - lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0])); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0])); // zero extend these results to fit into width *** There may be a more elegant way to do this assign czResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; - assign CntResult = (B[1]) ? cpopResult : czResult; - + mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult); endmodule \ No newline at end of file From 8c20d67659d6d0e3e0f698ee59f0a9c70bd36f56 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 00:28:07 -0800 Subject: [PATCH 152/183] reverted to working version --- src/ieu/controller.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 386ca228..cfc8b46a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -124,6 +124,7 @@ module controller( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction +<<<<<<< HEAD logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage @@ -141,6 +142,7 @@ module controller( // Main Instruction Decoder always_comb case(OpD) +<<<<<<< HEAD // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw From 7651d41c907e5c8a972766cc9a1d8d1e2e667466 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 00:29:58 -0800 Subject: [PATCH 153/183] reverted backing to working version --- src/ieu/controller.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index cfc8b46a..386ca228 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -124,7 +124,6 @@ module controller( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction -<<<<<<< HEAD logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage @@ -142,7 +141,6 @@ module controller( // Main Instruction Decoder always_comb case(OpD) -<<<<<<< HEAD // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw From 7ec33ca0944c3ec57bff1dac1460520b718cc7b6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 10:57:06 -0800 Subject: [PATCH 154/183] shifter sign generation logic optimize --- src/ieu/alu.sv | 18 +++++++++++++----- src/ieu/shifter.sv | 12 ++++++------ 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index eb7e9f3a..cf33df53 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -48,7 +48,7 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondZextA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned @@ -56,7 +56,7 @@ module alu #(parameter WIDTH=32) ( logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter + logic shSignA; logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux logic Rotate; // Indicates if it is Rotate instruction @@ -80,7 +80,7 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; - // Sign/Zero extend mux + /*// Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb case (shASelect) @@ -90,6 +90,14 @@ module alu #(parameter WIDTH=32) ( 2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw) endcase end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions + */ + if (WIDTH == 64) begin + mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); + mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); + end else begin + mux2 #(1) signmux(1'b0, A[31], SubArith, shSignA); + assign CondExtA = A; + end // shifter rotate source select mux if (`ZBB_SUPPORTED) begin @@ -99,7 +107,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift - assign CondShiftA = shA[WIDTH-1:0] << (PreShiftAmt); + assign CondShiftA = CondExtA << (PreShiftAmt); end else assign CondShiftA = A; // Addition @@ -108,7 +116,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index dbed7655..594ef3dd 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] shA, // shift Source input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, // Shift right, rotate signals + input logic Right, Rotate, W64, Sign, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits @@ -45,7 +45,7 @@ module shifter ( case({Right, Rotate}) 2'b00: z = {shA[31:0], 31'b0}; 2'b01: z = {rotA,rotA[31:1]}; - 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b10: z = {{31{Sign}}, shA[31:0]}; 2'b11: z = {rotA[30:0],rotA}; endcase assign amttrunc = Amt; // shift amount @@ -54,7 +54,7 @@ module shifter ( case ({Right, Rotate}) 2'b00: z = {shA[63:0],{63'b0}}; 2'b01: z = {rotA, rotA[63:1]}; - 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b10: z = {{63{Sign}},shA[63:0]}; 2'b11: z = {rotA[62:0],rotA[63:0]}; endcase assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift @@ -62,12 +62,12 @@ module shifter ( end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) z = {{31{shA[32]}}, shA[31:0]}; + if (Right) z = {{31{Sign}}, shA[31:0]}; else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (Right) z = {{63{shA[64]}},shA[63:0]}; + if (Right) z = {{63{Sign}},shA[63:0]}; else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end From dc456415c1718912bafff8a9f716a620aebacba5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 10:57:52 -0800 Subject: [PATCH 155/183] formatting --- src/ieu/alu.sv | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index cf33df53..916b25a9 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -80,17 +80,7 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; - /*// Sign/Zero extend mux - if (WIDTH == 64) begin // rv64 must handle word s/z extensions - always_comb - case (shASelect) - 2'b00: shA = {{1'b0}, A}; // zero-extend double-word (srl) - 2'b01: shA = {A[63], A}; // sign-extend double-word (sra) - 2'b10: shA = {{33'b0}, A[31:0]}; // zero-extend word (add.uw, shadd.uw, srlw) - 2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw) - endcase - end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions - */ + if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); From b33b0afc77392fb131e1cecd3c4f6572bad89244 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 13:58:08 -0800 Subject: [PATCH 156/183] specifc instruction handling for B's - Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW --- src/ieu/bmu/bmuctrl.sv | 121 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 16 +++--- 2 files changed, 70 insertions(+), 67 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index f4001456..4488ff29 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -38,6 +38,7 @@ module bmuctrl( output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage + output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage output logic BALUOpD, // Indicates if it is an ALU B instruction in Decode Stage output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage @@ -62,7 +63,7 @@ module bmuctrl( logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions - `define BMUCTRLW 16 + `define BMUCTRLW 17 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -75,92 +76,96 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + //17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_1_1_0_0_0_0; // xnor + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // minu - default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu + default: BMUControlsD = {Funct3D, {13'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; // Pack BALUControl Signals assign BALUControlD = {RotateD, MaskD, PreShiftD}; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 97bda128..03979fc2 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -97,6 +97,7 @@ module controller( logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically logic BaseRegWriteD; // Indicates if Base instruction register write instruction logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu + logic BaseALUSrcBD; // Base instruction ALU B source select signal logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -130,6 +131,7 @@ module controller( logic BW64D; // Indicates if it is a W type B instruction in decode stage logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor + logic BALUSrcBD; // B-type alu src select signal logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions @@ -179,15 +181,9 @@ module controller( always_comb begin ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction case(OpD) -<<<<<<< HEAD - // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal - 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction - 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw -======= // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000011: if (LFunctD) ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads ->>>>>>> origin 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported 7'b0001111: if (`ZIFENCEI_SUPPORTED) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence @@ -196,7 +192,7 @@ module controller( 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc - 7'b0011011: if (IFunctD & `XLEN == 64) + 7'b0011011: if ((IFunctD & `XLEN == 64)) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i 7'b0100011: if (SFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores @@ -239,7 +235,7 @@ module controller( assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal //assign IllegalBaseInstrD = 1'b0; - assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, + assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; @@ -247,6 +243,7 @@ module controller( assign ALUOpD = BaseALUOpD | BALUOpD; assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; + assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand @@ -265,7 +262,7 @@ module controller( // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -285,6 +282,7 @@ module controller( assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; assign BALUControlE = 3'b0; + assign BALUSrcBD = 1'b0; assign sltD = (Funct3D == 3'b010); From 20af58cdd4e4844e5579d984dbbf10c24825f9c3 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 14:01:47 -0800 Subject: [PATCH 157/183] alu formatting --- src/ieu/alu.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 916b25a9..cdb2e491 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -80,7 +80,6 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; - if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); From 2175702f6d9b66eb761e3ec3f0da9913d69e48b6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 8 Mar 2023 16:22:43 -0800 Subject: [PATCH 158/183] cleaner bmu decode logic --- src/ieu/bmu/bmuctrl.sv | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4488ff29..47df5f30 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -64,6 +64,7 @@ module bmuctrl( logic [2:0] BALUControlD; // ALU Control signals for B instructions `define BMUCTRLW 17 + `define BMUCTRLWSUB3 14 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -74,35 +75,27 @@ module bmuctrl( assign Rs2D = InstrD[24:20]; // Main Instruction Decoder - always_comb + always_comb begin + BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset - //17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw @@ -126,43 +119,29 @@ module bmuctrl( 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction - else - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu - default: BMUControlsD = {Funct3D, {13'b0}, {1'b1}}; // not B instruction or shift endcase + end // Unpack Control Signals assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; From 5853854f5240eb76d11c801e7683715fe1c96b5d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Mar 2023 12:35:42 -0800 Subject: [PATCH 159/183] fixed bmu bug - accidentally deleted count instruction decode --- src/ieu/bmu/bmuctrl.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 47df5f30..377c26f9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -123,6 +123,8 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw 17'b0010011_0110000_001: if (Rs2D[2]) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction + else + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) From 6ee15c6e2c7d18cda497315fce0bd970480ebc32 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Mar 2023 12:44:51 -0800 Subject: [PATCH 160/183] more comprehensive illegal b instr. check --- src/ieu/bmu/bmuctrl.sv | 127 ++++++++++++++++++++++++++--------------- 1 file changed, 81 insertions(+), 46 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 377c26f9..4d357854 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -80,68 +80,103 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100101_001: if (`XLEN == 64) + 17'b0010011_0100100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0100101_101: if (`XLEN == 64) + 17'b0010011_0100100_101: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0110101_001: if (`XLEN == 64) + 17'b0010011_0110100_001: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti - 17'b0010011_0010101_001: if (`XLEN == 64) + 17'b0010011_0010100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + 17'b0110011_0100100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + 17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: if (`ZBC_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + 17'b0110011_0010000_010: if (`ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: if (`ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: if (`ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) - 17'b0010011_0110001_101: if (`XLEN == 64) + 17'b0110011_0110000_001: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0010011_0110001_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: if (`XLEN == 64) + 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (Rs2D[2]) + 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction - 17'b0111011_0000100_100: if (`XLEN == 64) + 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + 17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - 17'b0110011_0000100_100: if (`XLEN == 32) + 17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_0110101_101: if (`XLEN == 64) + 17'b0110011_0100000_111: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - 17'b0010011_0110100_101: if (`XLEN == 32) + 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu + 17'b0010011_0010100_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu endcase end From a5841c6fb2c630eb695c3eb59cbd26b457a5aa32 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:17:38 -0800 Subject: [PATCH 161/183] removed redundant condinvb mux --- src/ieu/alu.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index cdb2e491..5fce245b 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -101,8 +101,7 @@ module alu #(parameter WIDTH=32) ( // Addition assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; - assign CondInvB = SubArith ? ~B : B; - assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); From 827cf567e69221a537f89ff2f5b42e2370e97ec2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:18:24 -0800 Subject: [PATCH 162/183] removed redundant convinvb signal --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 5fce245b..6398e4fc 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,7 +43,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux From 869c7283e82cb28d43fac5b8913eab322479095e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:32:01 -0800 Subject: [PATCH 163/183] formatting --- src/ieu/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 6398e4fc..c770a630 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,12 +43,12 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned From bc9cd4a26e11ec02a22e0d71088b8e7188939daa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 17:17:24 -0800 Subject: [PATCH 164/183] more checks in bitmanip decode --- src/ieu/bmu/bmuctrl.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4d357854..936986cf 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -147,11 +147,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED) + 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction - else + else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) + 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) @@ -163,11 +163,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED) + 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED) + 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) - 17'b0010011_0010100_101: if (`ZBB_SUPPORTED) + 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max From 9e5360e31f7d3b2aa42be33679a82c5e7248f023 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 09:37:57 -0700 Subject: [PATCH 165/183] format + min/max structural mux --- src/ieu/bmu/zbb.sv | 4 ++-- src/ieu/controller.sv | 5 +---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 70b984ea..ddf96b11 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -47,8 +47,8 @@ module zbb #(parameter WIDTH=32) ( byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); - assign MaxResult = (lt) ? B : A; - assign MinResult = (lt) ? A : B; + mux2 #(WIDTH) maxmux(A, B, lt, MaxResult); + mux2 #(WIDTH) minmux(B, A, lt, MinResult); // ZBB Result select mux mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4e20458c..22c9d057 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -246,13 +246,11 @@ module controller( assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand - assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi @@ -268,7 +266,6 @@ module controller( assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; end else assign sltD = (Funct3D == 3'b010); - //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -314,7 +311,7 @@ module controller( // The comparator handles both signed and unsigned branches using BranchSignedE // Hence, only eq and lt flags are needed // We also want comparator to handle signed comparison on a max/min bitmanip instruction - assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE ; + assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE; assign {eqE, ltE} = FlagsE; mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE); assign BranchTakenE = BranchFlagE ^ Funct3E[0]; From 728be29ce3d35cab1ae68d90758231a84fce63fe Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 13:09:49 -0700 Subject: [PATCH 166/183] formatting --- src/ieu/alu.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 99e14404..de649b5e 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,7 +43,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux @@ -123,8 +123,8 @@ module alu #(parameter WIDTH=32) ( else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect 3'b000: FullResult = Sum; // add or sub 3'b001: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu + 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt + 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr @@ -137,8 +137,8 @@ module alu #(parameter WIDTH=32) ( else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect 3'b000: FullResult = Sum; // add or sub 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu + 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt + 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ B; // xor 3'b110: FullResult = A | B; // or 3'b111: FullResult = A & B; // and From 7a6d1ab39347f36f7173c2fb13519931e72e3a20 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 14:19:39 -0700 Subject: [PATCH 167/183] added bitmanip 64 tests to updated regression script + alu structural mux changes --- sim/regression-wally | 2 +- src/ieu/alu.sv | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 31110454..565f4f6d 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -126,7 +126,7 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] coverStr = '-coverage' diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index de649b5e..110ca418 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -77,7 +77,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); - assign CondMaskB = (Mask) ? MaskB : B; + mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; if (WIDTH == 64) begin @@ -89,9 +89,8 @@ module alu #(parameter WIDTH=32) ( end // shifter rotate source select mux - if (`ZBB_SUPPORTED) begin - if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; - else assign rotA = A; + if (`ZBB_SUPPORTED & WIDTH == 64) begin + mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes From 37b73ea42e26448e9098fdab02a7db73c9e7dd02 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 14:23:54 -0700 Subject: [PATCH 168/183] more structural mux changes --- src/ieu/bmu/byte.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 19b71fc1..52480235 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -42,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) ( assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i]; end - assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result; + mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult); endmodule \ No newline at end of file From 73fbc21aabd8a5e63e9a08476f8bb8183359d368 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 14:25:05 -0700 Subject: [PATCH 169/183] formatting --- src/ieu/bmu/byte.sv | 1 - src/ieu/bmu/clmul.sv | 1 - 2 files changed, 2 deletions(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 52480235..8cf3f0e5 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -43,5 +43,4 @@ module byteUnit #(parameter WIDTH=32) ( end mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult); - endmodule \ No newline at end of file diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 16d600b4..85d427ed 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -47,7 +47,6 @@ module clmul #(parameter WIDTH=32) ( ClmulResult[i] = s[WIDTH*i+j-1]; end end - endmodule From 80a490888ad1f3b10eb2a51214be1dc6c2bece9d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:14:12 -0700 Subject: [PATCH 170/183] formatting --- src/ieu/bmu/bitreverse.sv | 6 +++--- src/ieu/bmu/clmul.sv | 3 +-- src/ieu/bmu/cnt.sv | 6 +++--- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/bmu/zbc.sv | 4 ++-- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 644783e5..86024a34 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -30,12 +30,12 @@ `include "wally-config.vh" module bitreverse #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] a, - output logic [WIDTH-1:0] b); + input logic [WIDTH-1:0] A, + output logic [WIDTH-1:0] RevA); genvar i; for (i=0; i Date: Wed, 22 Mar 2023 10:25:54 -0700 Subject: [PATCH 171/183] min/max mux optimize --- src/ieu/bmu/bmuctrl.sv | 24 ++++++++++++------------ src/ieu/bmu/zbb.sv | 14 +++++++------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 936986cf..b09bec11 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -84,11 +84,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100100_101: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + 17'b0010011_0100100_101: if (`ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110100_001: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + 17'b0010011_0110100_001: if (`ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) @@ -141,13 +141,13 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror 17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) - 17'b0010011_0110001_101: if (`XLEN == 64 & `ZBB_SUPPORTED) + //17'b0010011_0110000_101: if (`ZBB_SUPPORTED) + // BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) + 17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction @@ -163,16 +163,16 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) + 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 + //17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) + // BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max + BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max 17'b0110011_0000101_111: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu + BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu 17'b0110011_0000101_100: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min 17'b0110011_0000101_101: if (`ZBB_SUPPORTED) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index ddf96b11..89ae7beb 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -39,17 +39,17 @@ module zbb #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ZBBResult); // ZBB result logic [WIDTH-1:0] CntResult; // count result - logic [WIDTH-1:0] MinResult,MaxResult; // min,max result + logic [WIDTH-1:0] MinResult,MaxResult, MinMaxResult; // min,max result logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results - cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); - byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); - ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); + cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult); + byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); + ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); - mux2 #(WIDTH) maxmux(A, B, lt, MaxResult); - mux2 #(WIDTH) minmux(B, A, lt, MinResult); + // ZBBSelect[2] differentiates between min(u) vs max(u) instruction + mux2 #(WIDTH) minmaxmux(B, A, lt^ZBBSelect[2], MinMaxResult); // ZBB Result select mux - mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); + mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult); endmodule \ No newline at end of file From b9b8023674b12151c000d13594edd31ae6c51077 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:26:04 -0700 Subject: [PATCH 172/183] formatting --- src/ieu/alu.sv | 12 ++++++------ src/ieu/controller.sv | 4 +++- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 110ca418..7e38b1a6 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -93,7 +93,7 @@ module alu #(parameter WIDTH=32) ( mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); end else assign rotA = A; - if (`ZBA_SUPPORTED) begin: zbamuxes + if (`ZBA_SUPPORTED) begin: zbapreshift // Pre-Shift assign CondShiftA = CondExtA << (PreShiftAmt); end else assign CondShiftA = A; @@ -103,7 +103,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -125,9 +125,9 @@ module alu #(parameter WIDTH=32) ( 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr - 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase end else begin @@ -145,15 +145,15 @@ module alu #(parameter WIDTH=32) ( end if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); + bitreverse #(WIDTH) brA(.A, .RevA); end if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A(A), .RevA(RevA), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 168f6af1..5c397d15 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -260,7 +260,9 @@ module controller( // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, + .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, + .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; From c197a040c8a5170a2c6c1cbf3cfd9354d600008d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:27:59 -0700 Subject: [PATCH 173/183] remove helper python script --- src/ieu/bmu/bitfieldedit.py | 32 -------------------------------- 1 file changed, 32 deletions(-) delete mode 100644 src/ieu/bmu/bitfieldedit.py diff --git a/src/ieu/bmu/bitfieldedit.py b/src/ieu/bmu/bitfieldedit.py deleted file mode 100644 index a9f604a3..00000000 --- a/src/ieu/bmu/bitfieldedit.py +++ /dev/null @@ -1,32 +0,0 @@ -""" - bitfieldedit.py - Script that appends 0 just before the "illegal instruction" field of the bitstring - Written by Kevin Kim -""" -def addZero(s): - try: - indexSemicolon = s.index(";") - newS = s[:indexSemicolon-1]+"0_"+s[indexSemicolon-1:] - return newS - except: return s - -def main(): - filename = input("Enter full filename: ") - n1 = int(input("Line number to begin: ")) - n2 = int(input("Line number to end: ")) - f = open(filename, "r") - flines = f.readlines() - - #create list of lines from line n1 to n2, inclusive - lines = flines[(n1-1):(n2-1)] - - #string to be printed - out = "" - - for i in range(len(lines)): - lines[i] = addZero(lines[i]) - out += lines[i] - print(out) - -if __name__ == "__main__": - main() \ No newline at end of file From b3fbdba7f3668e20720980ad675ef41dd9f5b71c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:31:21 -0700 Subject: [PATCH 174/183] updated header comments to indicate chapter 15 --- src/ieu/bmu/bitreverse.sv | 2 +- src/ieu/bmu/bmuctrl.sv | 4 +--- src/ieu/bmu/byte.sv | 2 +- src/ieu/bmu/clmul.sv | 2 +- src/ieu/bmu/cnt.sv | 2 +- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 ++ src/ieu/bmu/zbb.sv | 2 +- src/ieu/bmu/zbc.sv | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 86024a34..e2afb0c9 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -8,7 +8,7 @@ // // Purpose: Bit reverse submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b09bec11..ae401ef8 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -7,7 +7,7 @@ // // Purpose: Top level bit manipulation instruction decoder // -// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // @@ -165,8 +165,6 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 - //17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - // BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 8cf3f0e5..db7a3b45 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -7,7 +7,7 @@ // // Purpose: RISCV bitmanip byte-wise operation unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index b96f3af6..904c6423 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -7,7 +7,7 @@ // // Purpose: Carry-Less multiplication unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 296e6d38..13ff1e15 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -8,7 +8,7 @@ // // Purpose: Count Instruction Submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 250616b5..12e69043 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -8,7 +8,7 @@ // // Purpose: Sign/Zero Extension Submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index f7e18b15..77c4b615 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -6,6 +6,8 @@ // // Purpose: Population Count // +// Documentation: RISC-V System on Chip Design Chapter 15 +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 89ae7beb..1e2c8437 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -8,7 +8,7 @@ // // Purpose: RISC-V ZBB top level unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 5ed04bc0..05e05d38 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBC top-level unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // From cd500180873c3b7e9ac3fb2ea8947d9add2fa0fb Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:34:17 -0700 Subject: [PATCH 175/183] remove outdated --- src/ieu/bmu/zbb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1e2c8437..5d1c52f1 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -39,7 +39,7 @@ module zbb #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ZBBResult); // ZBB result logic [WIDTH-1:0] CntResult; // count result - logic [WIDTH-1:0] MinResult,MaxResult, MinMaxResult; // min,max result + logic [WIDTH-1:0] MinMaxResult; // min,max result logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results From a62b92e2efd29d9d89c476bc3a16e22e0e3d7b70 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 13:23:52 -0700 Subject: [PATCH 176/183] Removed unused ISA string from spike YAML --- tests/riscof/spike/spike_rv32gc_isa.yaml | 1 - tests/riscof/spike/spike_rv64gc_isa.yaml | 1 - 2 files changed, 2 deletions(-) diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 05fc6f60..3438e17a 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,6 +1,5 @@ hart_ids: [0] hart0: - #ISA: RV32IMAFDCZicsr_Zifencei ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index e6bfc72e..a8837ac7 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,6 +1,5 @@ hart_ids: [0] hart0: -# ISA: RV64IMAFDCSUZicsr_Zifencei ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' From 1232f3a6c539b81b4e2a3743a2a458bba75d19e0 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 13:32:24 -0700 Subject: [PATCH 177/183] restored sim-wally-batch to existing tests --- sim/sim-wally-batch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch index 95fc677c..4fa06d3c 100755 --- a/sim/sim-wally-batch +++ b/sim/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-batch.do rv64gc arch64b" +vsim -c -do "do wally-batch.do rv32gc wally32priv" \ No newline at end of file From 1bf08d6d896dd1e2cd85cfb9962e6e623759fcdf Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 14:11:42 -0700 Subject: [PATCH 178/183] restored Imperas test names --- testbench/tests.vh | 1455 +++++++++++++++++++++----------------------- 1 file changed, 698 insertions(+), 757 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 10633276..17d9fea0 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -98,755 +98,755 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, - "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", - "rv32i_m/F/FADD-S-DYN-RDN-01.S", - "rv32i_m/F/FADD-S-DYN-RMM-01.S", - "rv32i_m/F/FADD-S-DYN-RNE-01.S", - "rv32i_m/F/FADD-S-DYN-RTZ-01.S", - "rv32i_m/F/FADD-S-DYN-RUP-01.S", - "rv32i_m/F/FADD-S-RDN-01.S", - "rv32i_m/F/FADD-S-RMM-01.S", - "rv32i_m/F/FADD-S-RNE-01.S", - "rv32i_m/F/FADD-S-RTZ-01.S", - "rv32i_m/F/FADD-S-RUP-01.S", - "rv32i_m/F/FCLASS-S-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01.S", - "rv32i_m/F/FCVT-S-W-RDN-01.S", - "rv32i_m/F/FCVT-S-W-RMM-01.S", - "rv32i_m/F/FCVT-S-W-RNE-01.S", - "rv32i_m/F/FCVT-S-W-RTZ-01.S", - "rv32i_m/F/FCVT-S-W-RUP-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01.S", - "rv32i_m/F/FCVT-S-WU-RDN-01.S", - "rv32i_m/F/FCVT-S-WU-RMM-01.S", - "rv32i_m/F/FCVT-S-WU-RNE-01.S", - "rv32i_m/F/FCVT-S-WU-RTZ-01.S", - "rv32i_m/F/FCVT-S-WU-RUP-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01.S", - "rv32i_m/F/FCVT-W-S-RDN-01.S", - "rv32i_m/F/FCVT-W-S-RMM-01.S", - "rv32i_m/F/FCVT-W-S-RNE-01.S", - "rv32i_m/F/FCVT-W-S-RTZ-01.S", - "rv32i_m/F/FCVT-W-S-RUP-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01.S", - "rv32i_m/F/FCVT-WU-S-RDN-01.S", - "rv32i_m/F/FCVT-WU-S-RMM-01.S", - "rv32i_m/F/FCVT-WU-S-RNE-01.S", - "rv32i_m/F/FCVT-WU-S-RTZ-01.S", - "rv32i_m/F/FCVT-WU-S-RUP-01.S", - "rv32i_m/F/FDIV-S-DYN-RDN-01.S", - "rv32i_m/F/FDIV-S-DYN-RMM-01.S", - "rv32i_m/F/FDIV-S-DYN-RNE-01.S", - "rv32i_m/F/FDIV-S-DYN-RTZ-01.S", - "rv32i_m/F/FDIV-S-DYN-RUP-01.S", - "rv32i_m/F/FDIV-S-RDN-01.S", - "rv32i_m/F/FDIV-S-RMM-01.S", - "rv32i_m/F/FDIV-S-RNE-01.S", - "rv32i_m/F/FDIV-S-RTZ-01.S", - "rv32i_m/F/FDIV-S-RUP-01.S", - "rv32i_m/F/FEQ-S-01.S", - "rv32i_m/F/FLE-S-01.S", - "rv32i_m/F/FLT-S-01.S", - "rv32i_m/F/FLW-01.S", - "rv32i_m/F/FMADD-S-DYN-RDN-01.S", - "rv32i_m/F/FMADD-S-DYN-RMM-01.S", - "rv32i_m/F/FMADD-S-DYN-RNE-01.S", - "rv32i_m/F/FMADD-S-DYN-RTZ-01.S", - "rv32i_m/F/FMADD-S-DYN-RUP-01.S", - "rv32i_m/F/FMADD-S-RDN-01.S", - "rv32i_m/F/FMADD-S-RMM-01.S", - "rv32i_m/F/FMADD-S-RNE-01.S", - "rv32i_m/F/FMADD-S-RTZ-01.S", - "rv32i_m/F/FMADD-S-RUP-01.S", - "rv32i_m/F/FMAX-S-01.S", - "rv32i_m/F/FMIN-S-01.S", - "rv32i_m/F/FMSUB-S-DYN-RDN-01.S", - "rv32i_m/F/FMSUB-S-DYN-RMM-01.S", - "rv32i_m/F/FMSUB-S-DYN-RNE-01.S", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01.S", - "rv32i_m/F/FMSUB-S-DYN-RUP-01.S", - "rv32i_m/F/FMSUB-S-RDN-01.S", - "rv32i_m/F/FMSUB-S-RMM-01.S", - "rv32i_m/F/FMSUB-S-RNE-01.S", - "rv32i_m/F/FMSUB-S-RTZ-01.S", - "rv32i_m/F/FMSUB-S-RUP-01.S", - "rv32i_m/F/FMUL-S-DYN-RDN-01.S", - "rv32i_m/F/FMUL-S-DYN-RMM-01.S", - "rv32i_m/F/FMUL-S-DYN-RNE-01.S", - "rv32i_m/F/FMUL-S-DYN-RTZ-01.S", - "rv32i_m/F/FMUL-S-DYN-RUP-01.S", - "rv32i_m/F/FMUL-S-RDN-01.S", - "rv32i_m/F/FMUL-S-RMM-01.S", - "rv32i_m/F/FMUL-S-RNE-01.S", - "rv32i_m/F/FMUL-S-RTZ-01.S", - "rv32i_m/F/FMUL-S-RUP-01.S", - "rv32i_m/F/FMV-W-X-01.S", - "rv32i_m/F/FMV-X-W-01.S", - "rv32i_m/F/FNMADD-S-DYN-RDN-01.S", - "rv32i_m/F/FNMADD-S-DYN-RMM-01.S", - "rv32i_m/F/FNMADD-S-DYN-RNE-01.S", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01.S", - "rv32i_m/F/FNMADD-S-DYN-RUP-01.S", - "rv32i_m/F/FNMADD-S-RDN-01.S", - "rv32i_m/F/FNMADD-S-RMM-01.S", - "rv32i_m/F/FNMADD-S-RNE-01.S", - "rv32i_m/F/FNMADD-S-RTZ-01.S", - "rv32i_m/F/FNMADD-S-RUP-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01.S", - "rv32i_m/F/FNMSUB-S-RDN-01.S", - "rv32i_m/F/FNMSUB-S-RMM-01.S", - "rv32i_m/F/FNMSUB-S-RNE-01.S", - "rv32i_m/F/FNMSUB-S-RTZ-01.S", - "rv32i_m/F/FNMSUB-S-RUP-01.S", - "rv32i_m/F/FSGNJN-S-01.S", - "rv32i_m/F/FSGNJ-S-01.S", - "rv32i_m/F/FSGNJX-S-01.S", - "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", - "rv32i_m/F/FSQRT-S-DYN-RMM-01.S", - "rv32i_m/F/FSQRT-S-DYN-RNE-01.S", - "rv32i_m/F/FSQRT-S-DYN-RTZ-01.S", - "rv32i_m/F/FSQRT-S-DYN-RUP-01.S", - "rv32i_m/F/FSQRT-S-RDN-01.S", - "rv32i_m/F/FSQRT-S-RMM-01.S", - "rv32i_m/F/FSQRT-S-RNE-01.S", - "rv32i_m/F/FSQRT-S-RTZ-01.S", - "rv32i_m/F/FSQRT-S-RUP-01.S", - "rv32i_m/F/FSUB-S-DYN-RDN-01.S", - "rv32i_m/F/FSUB-S-DYN-RMM-01.S", - "rv32i_m/F/FSUB-S-DYN-RNE-01.S", - "rv32i_m/F/FSUB-S-DYN-RTZ-01.S", - "rv32i_m/F/FSUB-S-DYN-RUP-01.S", - "rv32i_m/F/FSUB-S-RDN-01.S", - "rv32i_m/F/FSUB-S-RMM-01.S", - "rv32i_m/F/FSUB-S-RNE-01.S", - "rv32i_m/F/FSUB-S-RTZ-01.S", - "rv32i_m/F/FSUB-S-RUP-01.S", - "rv32i_m/F/FSW-01.S" + "rv32i_m/F/FSQRT-S-DYN-RDN-01", + "rv32i_m/F/FADD-S-DYN-RDN-01", + "rv32i_m/F/FADD-S-DYN-RMM-01", + "rv32i_m/F/FADD-S-DYN-RNE-01", + "rv32i_m/F/FADD-S-DYN-RTZ-01", + "rv32i_m/F/FADD-S-DYN-RUP-01", + "rv32i_m/F/FADD-S-RDN-01", + "rv32i_m/F/FADD-S-RMM-01", + "rv32i_m/F/FADD-S-RNE-01", + "rv32i_m/F/FADD-S-RTZ-01", + "rv32i_m/F/FADD-S-RUP-01", + "rv32i_m/F/FCLASS-S-01", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01", + "rv32i_m/F/FCVT-S-W-RDN-01", + "rv32i_m/F/FCVT-S-W-RMM-01", + "rv32i_m/F/FCVT-S-W-RNE-01", + "rv32i_m/F/FCVT-S-W-RTZ-01", + "rv32i_m/F/FCVT-S-W-RUP-01", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv32i_m/F/FCVT-S-WU-RDN-01", + "rv32i_m/F/FCVT-S-WU-RMM-01", + "rv32i_m/F/FCVT-S-WU-RNE-01", + "rv32i_m/F/FCVT-S-WU-RTZ-01", + "rv32i_m/F/FCVT-S-WU-RUP-01", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01", + "rv32i_m/F/FCVT-W-S-RDN-01", + "rv32i_m/F/FCVT-W-S-RMM-01", + "rv32i_m/F/FCVT-W-S-RNE-01", + "rv32i_m/F/FCVT-W-S-RTZ-01", + "rv32i_m/F/FCVT-W-S-RUP-01", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv32i_m/F/FCVT-WU-S-RDN-01", + "rv32i_m/F/FCVT-WU-S-RMM-01", + "rv32i_m/F/FCVT-WU-S-RNE-01", + "rv32i_m/F/FCVT-WU-S-RTZ-01", + "rv32i_m/F/FCVT-WU-S-RUP-01", + "rv32i_m/F/FDIV-S-DYN-RDN-01", + "rv32i_m/F/FDIV-S-DYN-RMM-01", + "rv32i_m/F/FDIV-S-DYN-RNE-01", + "rv32i_m/F/FDIV-S-DYN-RTZ-01", + "rv32i_m/F/FDIV-S-DYN-RUP-01", + "rv32i_m/F/FDIV-S-RDN-01", + "rv32i_m/F/FDIV-S-RMM-01", + "rv32i_m/F/FDIV-S-RNE-01", + "rv32i_m/F/FDIV-S-RTZ-01", + "rv32i_m/F/FDIV-S-RUP-01", + "rv32i_m/F/FEQ-S-01", + "rv32i_m/F/FLE-S-01", + "rv32i_m/F/FLT-S-01", + "rv32i_m/F/FLW-01", + "rv32i_m/F/FMADD-S-DYN-RDN-01", + "rv32i_m/F/FMADD-S-DYN-RMM-01", + "rv32i_m/F/FMADD-S-DYN-RNE-01", + "rv32i_m/F/FMADD-S-DYN-RTZ-01", + "rv32i_m/F/FMADD-S-DYN-RUP-01", + "rv32i_m/F/FMADD-S-RDN-01", + "rv32i_m/F/FMADD-S-RMM-01", + "rv32i_m/F/FMADD-S-RNE-01", + "rv32i_m/F/FMADD-S-RTZ-01", + "rv32i_m/F/FMADD-S-RUP-01", + "rv32i_m/F/FMAX-S-01", + "rv32i_m/F/FMIN-S-01", + "rv32i_m/F/FMSUB-S-DYN-RDN-01", + "rv32i_m/F/FMSUB-S-DYN-RMM-01", + "rv32i_m/F/FMSUB-S-DYN-RNE-01", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FMSUB-S-DYN-RUP-01", + "rv32i_m/F/FMSUB-S-RDN-01", + "rv32i_m/F/FMSUB-S-RMM-01", + "rv32i_m/F/FMSUB-S-RNE-01", + "rv32i_m/F/FMSUB-S-RTZ-01", + "rv32i_m/F/FMSUB-S-RUP-01", + "rv32i_m/F/FMUL-S-DYN-RDN-01", + "rv32i_m/F/FMUL-S-DYN-RMM-01", + "rv32i_m/F/FMUL-S-DYN-RNE-01", + "rv32i_m/F/FMUL-S-DYN-RTZ-01", + "rv32i_m/F/FMUL-S-DYN-RUP-01", + "rv32i_m/F/FMUL-S-RDN-01", + "rv32i_m/F/FMUL-S-RMM-01", + "rv32i_m/F/FMUL-S-RNE-01", + "rv32i_m/F/FMUL-S-RTZ-01", + "rv32i_m/F/FMUL-S-RUP-01", + "rv32i_m/F/FMV-W-X-01", + "rv32i_m/F/FMV-X-W-01", + "rv32i_m/F/FNMADD-S-DYN-RDN-01", + "rv32i_m/F/FNMADD-S-DYN-RMM-01", + "rv32i_m/F/FNMADD-S-DYN-RNE-01", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01", + "rv32i_m/F/FNMADD-S-DYN-RUP-01", + "rv32i_m/F/FNMADD-S-RDN-01", + "rv32i_m/F/FNMADD-S-RMM-01", + "rv32i_m/F/FNMADD-S-RNE-01", + "rv32i_m/F/FNMADD-S-RTZ-01", + "rv32i_m/F/FNMADD-S-RUP-01", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01", + "rv32i_m/F/FNMSUB-S-RDN-01", + "rv32i_m/F/FNMSUB-S-RMM-01", + "rv32i_m/F/FNMSUB-S-RNE-01", + "rv32i_m/F/FNMSUB-S-RTZ-01", + "rv32i_m/F/FNMSUB-S-RUP-01", + "rv32i_m/F/FSGNJN-S-01", + "rv32i_m/F/FSGNJ-S-01", + "rv32i_m/F/FSGNJX-S-01", + "rv32i_m/F/FSQRT-S-DYN-RDN-01", + "rv32i_m/F/FSQRT-S-DYN-RMM-01", + "rv32i_m/F/FSQRT-S-DYN-RNE-01", + "rv32i_m/F/FSQRT-S-DYN-RTZ-01", + "rv32i_m/F/FSQRT-S-DYN-RUP-01", + "rv32i_m/F/FSQRT-S-RDN-01", + "rv32i_m/F/FSQRT-S-RMM-01", + "rv32i_m/F/FSQRT-S-RNE-01", + "rv32i_m/F/FSQRT-S-RTZ-01", + "rv32i_m/F/FSQRT-S-RUP-01", + "rv32i_m/F/FSUB-S-DYN-RDN-01", + "rv32i_m/F/FSUB-S-DYN-RMM-01", + "rv32i_m/F/FSUB-S-DYN-RNE-01", + "rv32i_m/F/FSUB-S-DYN-RTZ-01", + "rv32i_m/F/FSUB-S-DYN-RUP-01", + "rv32i_m/F/FSUB-S-RDN-01", + "rv32i_m/F/FSUB-S-RMM-01", + "rv32i_m/F/FSUB-S-RNE-01", + "rv32i_m/F/FSUB-S-RTZ-01", + "rv32i_m/F/FSUB-S-RUP-01", + "rv32i_m/F/FSW-01" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01.S", - "rv64i_m/F/FADD-S-DYN-RMM-01.S", - "rv64i_m/F/FADD-S-DYN-RNE-01.S", - "rv64i_m/F/FADD-S-DYN-RTZ-01.S", - "rv64i_m/F/FADD-S-DYN-RUP-01.S", - "rv64i_m/F/FADD-S-RDN-01.S", - "rv64i_m/F/FADD-S-RMM-01.S", - "rv64i_m/F/FADD-S-RNE-01.S", - "rv64i_m/F/FADD-S-RTZ-01.S", - "rv64i_m/F/FADD-S-RUP-01.S", - "rv64i_m/F/FCLASS-S-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-L-S-RDN-01.S", - "rv64i_m/F/FCVT-L-S-RMM-01.S", - "rv64i_m/F/FCVT-L-S-RNE-01.S", - "rv64i_m/F/FCVT-L-S-RTZ-01.S", - "rv64i_m/F/FCVT-L-S-RUP-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-LU-S-RDN-01.S", - "rv64i_m/F/FCVT-LU-S-RMM-01.S", - "rv64i_m/F/FCVT-LU-S-RNE-01.S", - "rv64i_m/F/FCVT-LU-S-RTZ-01.S", - "rv64i_m/F/FCVT-LU-S-RUP-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-L-RDN-01.S", - "rv64i_m/F/FCVT-S-L-RMM-01.S", - "rv64i_m/F/FCVT-S-L-RNE-01.S", - "rv64i_m/F/FCVT-S-L-RTZ-01.S", - "rv64i_m/F/FCVT-S-L-RUP-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-LU-RDN-01.S", - "rv64i_m/F/FCVT-S-LU-RMM-01.S", - "rv64i_m/F/FCVT-S-LU-RNE-01.S", - "rv64i_m/F/FCVT-S-LU-RTZ-01.S", - "rv64i_m/F/FCVT-S-LU-RUP-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-W-RDN-01.S", - "rv64i_m/F/FCVT-S-W-RMM-01.S", - "rv64i_m/F/FCVT-S-W-RNE-01.S", - "rv64i_m/F/FCVT-S-W-RTZ-01.S", - "rv64i_m/F/FCVT-S-W-RUP-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-WU-RDN-01.S", - "rv64i_m/F/FCVT-S-WU-RMM-01.S", - "rv64i_m/F/FCVT-S-WU-RNE-01.S", - "rv64i_m/F/FCVT-S-WU-RTZ-01.S", - "rv64i_m/F/FCVT-S-WU-RUP-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-W-S-RDN-01.S", - "rv64i_m/F/FCVT-W-S-RMM-01.S", - "rv64i_m/F/FCVT-W-S-RNE-01.S", - "rv64i_m/F/FCVT-W-S-RTZ-01.S", - "rv64i_m/F/FCVT-W-S-RUP-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-WU-S-RDN-01.S", - "rv64i_m/F/FCVT-WU-S-RMM-01.S", - "rv64i_m/F/FCVT-WU-S-RNE-01.S", - "rv64i_m/F/FCVT-WU-S-RTZ-01.S", - "rv64i_m/F/FCVT-WU-S-RUP-01.S", - "rv64i_m/F/FDIV-S-DYN-RDN-01.S", - "rv64i_m/F/FDIV-S-DYN-RMM-01.S", - "rv64i_m/F/FDIV-S-DYN-RNE-01.S", - "rv64i_m/F/FDIV-S-DYN-RTZ-01.S", - "rv64i_m/F/FDIV-S-DYN-RUP-01.S", - "rv64i_m/F/FDIV-S-RDN-01.S", - "rv64i_m/F/FDIV-S-RMM-01.S", - "rv64i_m/F/FDIV-S-RNE-01.S", - "rv64i_m/F/FDIV-S-RTZ-01.S", - "rv64i_m/F/FDIV-S-RUP-01.S", - "rv64i_m/F/FEQ-S-01.S", - "rv64i_m/F/FLE-S-01.S", - "rv64i_m/F/FLT-S-01.S", - "rv64i_m/F/FLW-01.S", - "rv64i_m/F/FMADD-S-DYN-RDN-01.S", - "rv64i_m/F/FMADD-S-DYN-RMM-01.S", - "rv64i_m/F/FMADD-S-DYN-RNE-01.S", - "rv64i_m/F/FMADD-S-DYN-RTZ-01.S", - "rv64i_m/F/FMADD-S-DYN-RUP-01.S", - "rv64i_m/F/FMADD-S-RDN-01.S", - "rv64i_m/F/FMADD-S-RMM-01.S", - "rv64i_m/F/FMADD-S-RNE-01.S", - "rv64i_m/F/FMADD-S-RTZ-01.S", - "rv64i_m/F/FMADD-S-RUP-01.S", - "rv64i_m/F/FMAX-S-01.S", - "rv64i_m/F/FMIN-S-01.S", - "rv64i_m/F/FMSUB-S-DYN-RDN-01.S", - "rv64i_m/F/FMSUB-S-DYN-RMM-01.S", - "rv64i_m/F/FMSUB-S-DYN-RNE-01.S", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01.S", - "rv64i_m/F/FMSUB-S-DYN-RUP-01.S", - "rv64i_m/F/FMSUB-S-RDN-01.S", - "rv64i_m/F/FMSUB-S-RMM-01.S", - "rv64i_m/F/FMSUB-S-RNE-01.S", - "rv64i_m/F/FMSUB-S-RTZ-01.S", - "rv64i_m/F/FMSUB-S-RUP-01.S", - "rv64i_m/F/FMUL-S-DYN-RDN-01.S", - "rv64i_m/F/FMUL-S-DYN-RMM-01.S", - "rv64i_m/F/FMUL-S-DYN-RNE-01.S", - "rv64i_m/F/FMUL-S-DYN-RTZ-01.S", - "rv64i_m/F/FMUL-S-DYN-RUP-01.S", - "rv64i_m/F/FMUL-S-RDN-01.S", - "rv64i_m/F/FMUL-S-RMM-01.S", - "rv64i_m/F/FMUL-S-RNE-01.S", - "rv64i_m/F/FMUL-S-RTZ-01.S", - "rv64i_m/F/FMUL-S-RUP-01.S", - "rv64i_m/F/FMV-W-X-01.S", - "rv64i_m/F/FMV-X-W-01.S", - "rv64i_m/F/FNMADD-S-DYN-RDN-01.S", - "rv64i_m/F/FNMADD-S-DYN-RMM-01.S", - "rv64i_m/F/FNMADD-S-DYN-RNE-01.S", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01.S", - "rv64i_m/F/FNMADD-S-DYN-RUP-01.S", - "rv64i_m/F/FNMADD-S-RDN-01.S", - "rv64i_m/F/FNMADD-S-RMM-01.S", - "rv64i_m/F/FNMADD-S-RNE-01.S", - "rv64i_m/F/FNMADD-S-RTZ-01.S", - "rv64i_m/F/FNMADD-S-RUP-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01.S", - "rv64i_m/F/FNMSUB-S-RDN-01.S", - "rv64i_m/F/FNMSUB-S-RMM-01.S", - "rv64i_m/F/FNMSUB-S-RNE-01.S", - "rv64i_m/F/FNMSUB-S-RTZ-01.S", - "rv64i_m/F/FNMSUB-S-RUP-01.S", - "rv64i_m/F/FSGNJN-S-01.S", - "rv64i_m/F/FSGNJ-S-01.S", - "rv64i_m/F/FSGNJX-S-01.S", - "rv64i_m/F/FSQRT-S-DYN-RDN-01.S", - "rv64i_m/F/FSQRT-S-DYN-RMM-01.S", - "rv64i_m/F/FSQRT-S-DYN-RNE-01.S", - "rv64i_m/F/FSQRT-S-DYN-RTZ-01.S", - "rv64i_m/F/FSQRT-S-DYN-RUP-01.S", - "rv64i_m/F/FSQRT-S-RDN-01.S", - "rv64i_m/F/FSQRT-S-RMM-01.S", - "rv64i_m/F/FSQRT-S-RNE-01.S", - "rv64i_m/F/FSQRT-S-RTZ-01.S", - "rv64i_m/F/FSQRT-S-RUP-01.S", - "rv64i_m/F/FSUB-S-DYN-RDN-01.S", - "rv64i_m/F/FSUB-S-DYN-RMM-01.S", - "rv64i_m/F/FSUB-S-DYN-RNE-01.S", - "rv64i_m/F/FSUB-S-DYN-RTZ-01.S", - "rv64i_m/F/FSUB-S-DYN-RUP-01.S", - "rv64i_m/F/FSUB-S-RDN-01.S", - "rv64i_m/F/FSUB-S-RMM-01.S", - "rv64i_m/F/FSUB-S-RNE-01.S", - "rv64i_m/F/FSUB-S-RTZ-01.S", - "rv64i_m/F/FSUB-S-RUP-01.S", - "rv64i_m/F/FSW-01.S" + "rv64i_m/F/FADD-S-DYN-RDN-01", + "rv64i_m/F/FADD-S-DYN-RMM-01", + "rv64i_m/F/FADD-S-DYN-RNE-01", + "rv64i_m/F/FADD-S-DYN-RTZ-01", + "rv64i_m/F/FADD-S-DYN-RUP-01", + "rv64i_m/F/FADD-S-RDN-01", + "rv64i_m/F/FADD-S-RMM-01", + "rv64i_m/F/FADD-S-RNE-01", + "rv64i_m/F/FADD-S-RTZ-01", + "rv64i_m/F/FADD-S-RUP-01", + "rv64i_m/F/FCLASS-S-01", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01", + "rv64i_m/F/FCVT-L-S-RDN-01", + "rv64i_m/F/FCVT-L-S-RMM-01", + "rv64i_m/F/FCVT-L-S-RNE-01", + "rv64i_m/F/FCVT-L-S-RTZ-01", + "rv64i_m/F/FCVT-L-S-RUP-01", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-LU-S-RDN-01", + "rv64i_m/F/FCVT-LU-S-RMM-01", + "rv64i_m/F/FCVT-LU-S-RNE-01", + "rv64i_m/F/FCVT-LU-S-RTZ-01", + "rv64i_m/F/FCVT-LU-S-RUP-01", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01", + "rv64i_m/F/FCVT-S-L-RDN-01", + "rv64i_m/F/FCVT-S-L-RMM-01", + "rv64i_m/F/FCVT-S-L-RNE-01", + "rv64i_m/F/FCVT-S-L-RTZ-01", + "rv64i_m/F/FCVT-S-L-RUP-01", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-LU-RDN-01", + "rv64i_m/F/FCVT-S-LU-RMM-01", + "rv64i_m/F/FCVT-S-LU-RNE-01", + "rv64i_m/F/FCVT-S-LU-RTZ-01", + "rv64i_m/F/FCVT-S-LU-RUP-01", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01", + "rv64i_m/F/FCVT-S-W-RDN-01", + "rv64i_m/F/FCVT-S-W-RMM-01", + "rv64i_m/F/FCVT-S-W-RNE-01", + "rv64i_m/F/FCVT-S-W-RTZ-01", + "rv64i_m/F/FCVT-S-W-RUP-01", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-WU-RDN-01", + "rv64i_m/F/FCVT-S-WU-RMM-01", + "rv64i_m/F/FCVT-S-WU-RNE-01", + "rv64i_m/F/FCVT-S-WU-RTZ-01", + "rv64i_m/F/FCVT-S-WU-RUP-01", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01", + "rv64i_m/F/FCVT-W-S-RDN-01", + "rv64i_m/F/FCVT-W-S-RMM-01", + "rv64i_m/F/FCVT-W-S-RNE-01", + "rv64i_m/F/FCVT-W-S-RTZ-01", + "rv64i_m/F/FCVT-W-S-RUP-01", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-WU-S-RDN-01", + "rv64i_m/F/FCVT-WU-S-RMM-01", + "rv64i_m/F/FCVT-WU-S-RNE-01", + "rv64i_m/F/FCVT-WU-S-RTZ-01", + "rv64i_m/F/FCVT-WU-S-RUP-01", + "rv64i_m/F/FDIV-S-DYN-RDN-01", + "rv64i_m/F/FDIV-S-DYN-RMM-01", + "rv64i_m/F/FDIV-S-DYN-RNE-01", + "rv64i_m/F/FDIV-S-DYN-RTZ-01", + "rv64i_m/F/FDIV-S-DYN-RUP-01", + "rv64i_m/F/FDIV-S-RDN-01", + "rv64i_m/F/FDIV-S-RMM-01", + "rv64i_m/F/FDIV-S-RNE-01", + "rv64i_m/F/FDIV-S-RTZ-01", + "rv64i_m/F/FDIV-S-RUP-01", + "rv64i_m/F/FEQ-S-01", + "rv64i_m/F/FLE-S-01", + "rv64i_m/F/FLT-S-01", + "rv64i_m/F/FLW-01", + "rv64i_m/F/FMADD-S-DYN-RDN-01", + "rv64i_m/F/FMADD-S-DYN-RMM-01", + "rv64i_m/F/FMADD-S-DYN-RNE-01", + "rv64i_m/F/FMADD-S-DYN-RTZ-01", + "rv64i_m/F/FMADD-S-DYN-RUP-01", + "rv64i_m/F/FMADD-S-RDN-01", + "rv64i_m/F/FMADD-S-RMM-01", + "rv64i_m/F/FMADD-S-RNE-01", + "rv64i_m/F/FMADD-S-RTZ-01", + "rv64i_m/F/FMADD-S-RUP-01", + "rv64i_m/F/FMAX-S-01", + "rv64i_m/F/FMIN-S-01", + "rv64i_m/F/FMSUB-S-DYN-RDN-01", + "rv64i_m/F/FMSUB-S-DYN-RMM-01", + "rv64i_m/F/FMSUB-S-DYN-RNE-01", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FMSUB-S-DYN-RUP-01", + "rv64i_m/F/FMSUB-S-RDN-01", + "rv64i_m/F/FMSUB-S-RMM-01", + "rv64i_m/F/FMSUB-S-RNE-01", + "rv64i_m/F/FMSUB-S-RTZ-01", + "rv64i_m/F/FMSUB-S-RUP-01", + "rv64i_m/F/FMUL-S-DYN-RDN-01", + "rv64i_m/F/FMUL-S-DYN-RMM-01", + "rv64i_m/F/FMUL-S-DYN-RNE-01", + "rv64i_m/F/FMUL-S-DYN-RTZ-01", + "rv64i_m/F/FMUL-S-DYN-RUP-01", + "rv64i_m/F/FMUL-S-RDN-01", + "rv64i_m/F/FMUL-S-RMM-01", + "rv64i_m/F/FMUL-S-RNE-01", + "rv64i_m/F/FMUL-S-RTZ-01", + "rv64i_m/F/FMUL-S-RUP-01", + "rv64i_m/F/FMV-W-X-01", + "rv64i_m/F/FMV-X-W-01", + "rv64i_m/F/FNMADD-S-DYN-RDN-01", + "rv64i_m/F/FNMADD-S-DYN-RMM-01", + "rv64i_m/F/FNMADD-S-DYN-RNE-01", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01", + "rv64i_m/F/FNMADD-S-DYN-RUP-01", + "rv64i_m/F/FNMADD-S-RDN-01", + "rv64i_m/F/FNMADD-S-RMM-01", + "rv64i_m/F/FNMADD-S-RNE-01", + "rv64i_m/F/FNMADD-S-RTZ-01", + "rv64i_m/F/FNMADD-S-RUP-01", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01", + "rv64i_m/F/FNMSUB-S-RDN-01", + "rv64i_m/F/FNMSUB-S-RMM-01", + "rv64i_m/F/FNMSUB-S-RNE-01", + "rv64i_m/F/FNMSUB-S-RTZ-01", + "rv64i_m/F/FNMSUB-S-RUP-01", + "rv64i_m/F/FSGNJN-S-01", + "rv64i_m/F/FSGNJ-S-01", + "rv64i_m/F/FSGNJX-S-01", + "rv64i_m/F/FSQRT-S-DYN-RDN-01", + "rv64i_m/F/FSQRT-S-DYN-RMM-01", + "rv64i_m/F/FSQRT-S-DYN-RNE-01", + "rv64i_m/F/FSQRT-S-DYN-RTZ-01", + "rv64i_m/F/FSQRT-S-DYN-RUP-01", + "rv64i_m/F/FSQRT-S-RDN-01", + "rv64i_m/F/FSQRT-S-RMM-01", + "rv64i_m/F/FSQRT-S-RNE-01", + "rv64i_m/F/FSQRT-S-RTZ-01", + "rv64i_m/F/FSQRT-S-RUP-01", + "rv64i_m/F/FSUB-S-DYN-RDN-01", + "rv64i_m/F/FSUB-S-DYN-RMM-01", + "rv64i_m/F/FSUB-S-DYN-RNE-01", + "rv64i_m/F/FSUB-S-DYN-RTZ-01", + "rv64i_m/F/FSUB-S-DYN-RUP-01", + "rv64i_m/F/FSUB-S-RDN-01", + "rv64i_m/F/FSUB-S-RMM-01", + "rv64i_m/F/FSUB-S-RNE-01", + "rv64i_m/F/FSUB-S-RTZ-01", + "rv64i_m/F/FSUB-S-RUP-01", + "rv64i_m/F/FSW-01" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01.S", - "rv64i_m/D/FADD-D-DYN-RMM-01.S", - "rv64i_m/D/FADD-D-DYN-RNE-01.S", - "rv64i_m/D/FADD-D-DYN-RTZ-01.S", - "rv64i_m/D/FADD-D-DYN-RUP-01.S", - "rv64i_m/D/FADD-D-RDN-01.S", - "rv64i_m/D/FADD-D-RMM-01.S", - "rv64i_m/D/FADD-D-RNE-01.S", - "rv64i_m/D/FADD-D-RTZ-01.S", - "rv64i_m/D/FADD-D-RUP-01.S", - "rv64i_m/D/FCLASS-D-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01.S", - "rv64i_m/D/FCVT-D-L-RDN-01.S", - "rv64i_m/D/FCVT-D-L-RMM-01.S", - "rv64i_m/D/FCVT-D-L-RNE-01.S", - "rv64i_m/D/FCVT-D-L-RTZ-01.S", - "rv64i_m/D/FCVT-D-L-RUP-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01.S", - "rv64i_m/D/FCVT-D-LU-RDN-01.S", - "rv64i_m/D/FCVT-D-LU-RMM-01.S", - "rv64i_m/D/FCVT-D-LU-RNE-01.S", - "rv64i_m/D/FCVT-D-LU-RTZ-01.S", - "rv64i_m/D/FCVT-D-LU-RUP-01.S", - "rv64i_m/D/FCVT-D-S-01.S", - "rv64i_m/D/FCVT-D-W-01.S", - "rv64i_m/D/FCVT-D-WU-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-L-D-RDN-01.S", - "rv64i_m/D/FCVT-L-D-RMM-01.S", - "rv64i_m/D/FCVT-L-D-RNE-01.S", - "rv64i_m/D/FCVT-L-D-RTZ-01.S", - "rv64i_m/D/FCVT-L-D-RUP-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-LU-D-RDN-01.S", - "rv64i_m/D/FCVT-LU-D-RMM-01.S", - "rv64i_m/D/FCVT-LU-D-RNE-01.S", - "rv64i_m/D/FCVT-LU-D-RTZ-01.S", - "rv64i_m/D/FCVT-LU-D-RUP-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-S-D-RDN-01.S", - "rv64i_m/D/FCVT-S-D-RMM-01.S", - "rv64i_m/D/FCVT-S-D-RNE-01.S", - "rv64i_m/D/FCVT-S-D-RTZ-01.S", - "rv64i_m/D/FCVT-S-D-RUP-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-W-D-RDN-01.S", - "rv64i_m/D/FCVT-W-D-RMM-01.S", - "rv64i_m/D/FCVT-W-D-RNE-01.S", - "rv64i_m/D/FCVT-W-D-RTZ-01.S", - "rv64i_m/D/FCVT-W-D-RUP-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-WU-D-RDN-01.S", - "rv64i_m/D/FCVT-WU-D-RMM-01.S", - "rv64i_m/D/FCVT-WU-D-RNE-01.S", - "rv64i_m/D/FCVT-WU-D-RTZ-01.S", - "rv64i_m/D/FCVT-WU-D-RUP-01.S", - "rv64i_m/D/FDIV-D-DYN-RDN-01.S", - "rv64i_m/D/FDIV-D-DYN-RMM-01.S", - "rv64i_m/D/FDIV-D-DYN-RNE-01.S", - "rv64i_m/D/FDIV-D-DYN-RTZ-01.S", - "rv64i_m/D/FDIV-D-DYN-RUP-01.S", - "rv64i_m/D/FDIV-D-RDN-01.S", - "rv64i_m/D/FDIV-D-RMM-01.S", - "rv64i_m/D/FDIV-D-RNE-01.S", - "rv64i_m/D/FDIV-D-RTZ-01.S", - "rv64i_m/D/FDIV-D-RUP-01.S", - "rv64i_m/D/FEQ-D-01.S", - "rv64i_m/D/FLD-01.S", - "rv64i_m/D/FLE-D-01.S", - "rv64i_m/D/FLT-D-01.S", - "rv64i_m/D/FMADD-D-DYN-RDN-01.S", - "rv64i_m/D/FMADD-D-DYN-RMM-01.S", - "rv64i_m/D/FMADD-D-DYN-RNE-01.S", - "rv64i_m/D/FMADD-D-DYN-RTZ-01.S", - "rv64i_m/D/FMADD-D-DYN-RUP-01.S", - "rv64i_m/D/FMADD-D-RDN-01.S", - "rv64i_m/D/FMADD-D-RMM-01.S", - "rv64i_m/D/FMADD-D-RNE-01.S", - "rv64i_m/D/FMADD-D-RTZ-01.S", - "rv64i_m/D/FMADD-D-RUP-01.S", - "rv64i_m/D/FMAX-D-01.S", - "rv64i_m/D/FMIN-D-01.S", - "rv64i_m/D/FMSUB-D-DYN-RDN-01.S", - "rv64i_m/D/FMSUB-D-DYN-RMM-01.S", - "rv64i_m/D/FMSUB-D-DYN-RNE-01.S", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01.S", - "rv64i_m/D/FMSUB-D-DYN-RUP-01.S", - "rv64i_m/D/FMSUB-D-RDN-01.S", - "rv64i_m/D/FMSUB-D-RMM-01.S", - "rv64i_m/D/FMSUB-D-RNE-01.S", - "rv64i_m/D/FMSUB-D-RTZ-01.S", - "rv64i_m/D/FMSUB-D-RUP-01.S", - "rv64i_m/D/FMUL-D-DYN-RDN-01.S", - "rv64i_m/D/FMUL-D-DYN-RMM-01.S", - "rv64i_m/D/FMUL-D-DYN-RNE-01.S", - "rv64i_m/D/FMUL-D-DYN-RTZ-01.S", - "rv64i_m/D/FMUL-D-DYN-RUP-01.S", - "rv64i_m/D/FMUL-D-RDN-01.S", - "rv64i_m/D/FMUL-D-RMM-01.S", - "rv64i_m/D/FMUL-D-RNE-01.S", - "rv64i_m/D/FMUL-D-RTZ-01.S", - "rv64i_m/D/FMUL-D-RUP-01.S", - "rv64i_m/D/FMV-D-X-01.S", - "rv64i_m/D/FMV-X-D-01.S", - "rv64i_m/D/FNMADD-D-DYN-RDN-01.S", - "rv64i_m/D/FNMADD-D-DYN-RMM-01.S", - "rv64i_m/D/FNMADD-D-DYN-RNE-01.S", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01.S", - "rv64i_m/D/FNMADD-D-DYN-RUP-01.S", - "rv64i_m/D/FNMADD-D-RDN-01.S", - "rv64i_m/D/FNMADD-D-RMM-01.S", - "rv64i_m/D/FNMADD-D-RNE-01.S", - "rv64i_m/D/FNMADD-D-RTZ-01.S", - "rv64i_m/D/FNMADD-D-RUP-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01.S", - "rv64i_m/D/FNMSUB-D-RDN-01.S", - "rv64i_m/D/FNMSUB-D-RMM-01.S", - "rv64i_m/D/FNMSUB-D-RNE-01.S", - "rv64i_m/D/FNMSUB-D-RTZ-01.S", - "rv64i_m/D/FNMSUB-D-RUP-01.S", - "rv64i_m/D/FSD-01.S", - "rv64i_m/D/FSGNJ-D-01.S", - "rv64i_m/D/FSGNJN-D-01.S", - "rv64i_m/D/FSGNJX-D-01.S", - "rv64i_m/D/FSQRT-D-DYN-RDN-01.S", - "rv64i_m/D/FSQRT-D-DYN-RMM-01.S", - "rv64i_m/D/FSQRT-D-DYN-RNE-01.S", - "rv64i_m/D/FSQRT-D-DYN-RTZ-01.S", - "rv64i_m/D/FSQRT-D-DYN-RUP-01.S", - "rv64i_m/D/FSQRT-D-RDN-01.S", - "rv64i_m/D/FSQRT-D-RMM-01.S", - "rv64i_m/D/FSQRT-D-RNE-01.S", - "rv64i_m/D/FSQRT-D-RTZ-01.S", - "rv64i_m/D/FSQRT-D-RUP-01.S", - "rv64i_m/D/FSUB-D-DYN-RDN-01.S", - "rv64i_m/D/FSUB-D-DYN-RMM-01.S", - "rv64i_m/D/FSUB-D-DYN-RNE-01.S", - "rv64i_m/D/FSUB-D-DYN-RTZ-01.S", - "rv64i_m/D/FSUB-D-DYN-RUP-01.S", - "rv64i_m/D/FSUB-D-RDN-01.S", - "rv64i_m/D/FSUB-D-RMM-01.S", - "rv64i_m/D/FSUB-D-RNE-01.S", - "rv64i_m/D/FSUB-D-RTZ-01.S", - "rv64i_m/D/FSUB-D-RUP-01.S" + "rv64i_m/D/FADD-D-DYN-RDN-01", + "rv64i_m/D/FADD-D-DYN-RMM-01", + "rv64i_m/D/FADD-D-DYN-RNE-01", + "rv64i_m/D/FADD-D-DYN-RTZ-01", + "rv64i_m/D/FADD-D-DYN-RUP-01", + "rv64i_m/D/FADD-D-RDN-01", + "rv64i_m/D/FADD-D-RMM-01", + "rv64i_m/D/FADD-D-RNE-01", + "rv64i_m/D/FADD-D-RTZ-01", + "rv64i_m/D/FADD-D-RUP-01", + "rv64i_m/D/FCLASS-D-01", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01", + "rv64i_m/D/FCVT-D-L-RDN-01", + "rv64i_m/D/FCVT-D-L-RMM-01", + "rv64i_m/D/FCVT-D-L-RNE-01", + "rv64i_m/D/FCVT-D-L-RTZ-01", + "rv64i_m/D/FCVT-D-L-RUP-01", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", + "rv64i_m/D/FCVT-D-LU-RDN-01", + "rv64i_m/D/FCVT-D-LU-RMM-01", + "rv64i_m/D/FCVT-D-LU-RNE-01", + "rv64i_m/D/FCVT-D-LU-RTZ-01", + "rv64i_m/D/FCVT-D-LU-RUP-01", + "rv64i_m/D/FCVT-D-S-01", + "rv64i_m/D/FCVT-D-W-01", + "rv64i_m/D/FCVT-D-WU-01", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01", + "rv64i_m/D/FCVT-L-D-RDN-01", + "rv64i_m/D/FCVT-L-D-RMM-01", + "rv64i_m/D/FCVT-L-D-RNE-01", + "rv64i_m/D/FCVT-L-D-RTZ-01", + "rv64i_m/D/FCVT-L-D-RUP-01", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-LU-D-RDN-01", + "rv64i_m/D/FCVT-LU-D-RMM-01", + "rv64i_m/D/FCVT-LU-D-RNE-01", + "rv64i_m/D/FCVT-LU-D-RTZ-01", + "rv64i_m/D/FCVT-LU-D-RUP-01", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01", + "rv64i_m/D/FCVT-S-D-RDN-01", + "rv64i_m/D/FCVT-S-D-RMM-01", + "rv64i_m/D/FCVT-S-D-RNE-01", + "rv64i_m/D/FCVT-S-D-RTZ-01", + "rv64i_m/D/FCVT-S-D-RUP-01", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01", + "rv64i_m/D/FCVT-W-D-RDN-01", + "rv64i_m/D/FCVT-W-D-RMM-01", + "rv64i_m/D/FCVT-W-D-RNE-01", + "rv64i_m/D/FCVT-W-D-RTZ-01", + "rv64i_m/D/FCVT-W-D-RUP-01", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-WU-D-RDN-01", + "rv64i_m/D/FCVT-WU-D-RMM-01", + "rv64i_m/D/FCVT-WU-D-RNE-01", + "rv64i_m/D/FCVT-WU-D-RTZ-01", + "rv64i_m/D/FCVT-WU-D-RUP-01", + "rv64i_m/D/FDIV-D-DYN-RDN-01", + "rv64i_m/D/FDIV-D-DYN-RMM-01", + "rv64i_m/D/FDIV-D-DYN-RNE-01", + "rv64i_m/D/FDIV-D-DYN-RTZ-01", + "rv64i_m/D/FDIV-D-DYN-RUP-01", + "rv64i_m/D/FDIV-D-RDN-01", + "rv64i_m/D/FDIV-D-RMM-01", + "rv64i_m/D/FDIV-D-RNE-01", + "rv64i_m/D/FDIV-D-RTZ-01", + "rv64i_m/D/FDIV-D-RUP-01", + "rv64i_m/D/FEQ-D-01", + "rv64i_m/D/FLD-01", + "rv64i_m/D/FLE-D-01", + "rv64i_m/D/FLT-D-01", + "rv64i_m/D/FMADD-D-DYN-RDN-01", + "rv64i_m/D/FMADD-D-DYN-RMM-01", + "rv64i_m/D/FMADD-D-DYN-RNE-01", + "rv64i_m/D/FMADD-D-DYN-RTZ-01", + "rv64i_m/D/FMADD-D-DYN-RUP-01", + "rv64i_m/D/FMADD-D-RDN-01", + "rv64i_m/D/FMADD-D-RMM-01", + "rv64i_m/D/FMADD-D-RNE-01", + "rv64i_m/D/FMADD-D-RTZ-01", + "rv64i_m/D/FMADD-D-RUP-01", + "rv64i_m/D/FMAX-D-01", + "rv64i_m/D/FMIN-D-01", + "rv64i_m/D/FMSUB-D-DYN-RDN-01", + "rv64i_m/D/FMSUB-D-DYN-RMM-01", + "rv64i_m/D/FMSUB-D-DYN-RNE-01", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FMSUB-D-DYN-RUP-01", + "rv64i_m/D/FMSUB-D-RDN-01", + "rv64i_m/D/FMSUB-D-RMM-01", + "rv64i_m/D/FMSUB-D-RNE-01", + "rv64i_m/D/FMSUB-D-RTZ-01", + "rv64i_m/D/FMSUB-D-RUP-01", + "rv64i_m/D/FMUL-D-DYN-RDN-01", + "rv64i_m/D/FMUL-D-DYN-RMM-01", + "rv64i_m/D/FMUL-D-DYN-RNE-01", + "rv64i_m/D/FMUL-D-DYN-RTZ-01", + "rv64i_m/D/FMUL-D-DYN-RUP-01", + "rv64i_m/D/FMUL-D-RDN-01", + "rv64i_m/D/FMUL-D-RMM-01", + "rv64i_m/D/FMUL-D-RNE-01", + "rv64i_m/D/FMUL-D-RTZ-01", + "rv64i_m/D/FMUL-D-RUP-01", + "rv64i_m/D/FMV-D-X-01", + "rv64i_m/D/FMV-X-D-01", + "rv64i_m/D/FNMADD-D-DYN-RDN-01", + "rv64i_m/D/FNMADD-D-DYN-RMM-01", + "rv64i_m/D/FNMADD-D-DYN-RNE-01", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01", + "rv64i_m/D/FNMADD-D-DYN-RUP-01", + "rv64i_m/D/FNMADD-D-RDN-01", + "rv64i_m/D/FNMADD-D-RMM-01", + "rv64i_m/D/FNMADD-D-RNE-01", + "rv64i_m/D/FNMADD-D-RTZ-01", + "rv64i_m/D/FNMADD-D-RUP-01", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01", + "rv64i_m/D/FNMSUB-D-RDN-01", + "rv64i_m/D/FNMSUB-D-RMM-01", + "rv64i_m/D/FNMSUB-D-RNE-01", + "rv64i_m/D/FNMSUB-D-RTZ-01", + "rv64i_m/D/FNMSUB-D-RUP-01", + "rv64i_m/D/FSD-01", + "rv64i_m/D/FSGNJ-D-01", + "rv64i_m/D/FSGNJN-D-01", + "rv64i_m/D/FSGNJX-D-01", + "rv64i_m/D/FSQRT-D-DYN-RDN-01", + "rv64i_m/D/FSQRT-D-DYN-RMM-01", + "rv64i_m/D/FSQRT-D-DYN-RNE-01", + "rv64i_m/D/FSQRT-D-DYN-RTZ-01", + "rv64i_m/D/FSQRT-D-DYN-RUP-01", + "rv64i_m/D/FSQRT-D-RDN-01", + "rv64i_m/D/FSQRT-D-RMM-01", + "rv64i_m/D/FSQRT-D-RNE-01", + "rv64i_m/D/FSQRT-D-RTZ-01", + "rv64i_m/D/FSQRT-D-RUP-01", + "rv64i_m/D/FSUB-D-DYN-RDN-01", + "rv64i_m/D/FSUB-D-DYN-RMM-01", + "rv64i_m/D/FSUB-D-DYN-RNE-01", + "rv64i_m/D/FSUB-D-DYN-RTZ-01", + "rv64i_m/D/FSUB-D-DYN-RUP-01", + "rv64i_m/D/FSUB-D-RDN-01", + "rv64i_m/D/FSUB-D-RMM-01", + "rv64i_m/D/FSUB-D-RNE-01", + "rv64i_m/D/FSUB-D-RTZ-01", + "rv64i_m/D/FSUB-D-RUP-01" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01.S", - "rv64i_m/M/DIVU-01.S", - "rv64i_m/M/DIVUW-01.S", - "rv64i_m/M/DIVW-01.S", - "rv64i_m/M/MUL-01.S", - "rv64i_m/M/MULH-01.S", - "rv64i_m/M/MULHSU-01.S", - "rv64i_m/M/MULHU-01.S", - "rv64i_m/M/MULW-01.S", - "rv64i_m/M/REM-01.S", - "rv64i_m/M/REMU-01.S", - "rv64i_m/M/REMUW-01.S", - "rv64i_m/M/REMW-01.S" + "rv64i_m/M/DIV-01", + "rv64i_m/M/DIVU-01", + "rv64i_m/M/DIVUW-01", + "rv64i_m/M/DIVW-01", + "rv64i_m/M/MUL-01", + "rv64i_m/M/MULH-01", + "rv64i_m/M/MULHSU-01", + "rv64i_m/M/MULHU-01", + "rv64i_m/M/MULW-01", + "rv64i_m/M/REM-01", + "rv64i_m/M/REMU-01", + "rv64i_m/M/REMUW-01", + "rv64i_m/M/REMW-01" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01.S", - "rv64i_m/C/C-ADDI-01.S", - "rv64i_m/C/C-ADDI16SP-01.S", - "rv64i_m/C/C-ADDI4SPN-01.S", - "rv64i_m/C/C-ADDIW-01.S", - "rv64i_m/C/C-ADDW-01.S", - "rv64i_m/C/C-AND-01.S", - "rv64i_m/C/C-ANDI-01.S", - "rv64i_m/C/C-BEQZ-01.S", - "rv64i_m/C/C-BNEZ-01.S", - "rv64i_m/C/C-J-01.S", - "rv64i_m/C/C-JALR-01.S", - "rv64i_m/C/C-JR-01.S", - "rv64i_m/C/C-LD-01.S", - "rv64i_m/C/C-LDSP-01.S", - "rv64i_m/C/C-LI-01.S", - "rv64i_m/C/C-LUI-01.S", - "rv64i_m/C/C-LW-01.S", - "rv64i_m/C/C-LWSP-01.S", - "rv64i_m/C/C-MV-01.S", - "rv64i_m/C/C-OR-01.S", - "rv64i_m/C/C-SD-01.S", - "rv64i_m/C/C-SDSP-01.S", - "rv64i_m/C/C-SLLI-01.S", - "rv64i_m/C/C-SRAI-01.S", - "rv64i_m/C/C-SRLI-01.S", - "rv64i_m/C/C-SUB-01.S", - "rv64i_m/C/C-SUBW-01.S", - "rv64i_m/C/C-SW-01.S", - "rv64i_m/C/C-SWSP-01.S", - "rv64i_m/C/C-XOR-01.S", - "rv64i_m/C/I-C-EBREAK-01.S", - "rv64i_m/C/I-C-NOP-01.S" + "rv64i_m/C/C-ADD-01", + "rv64i_m/C/C-ADDI-01", + "rv64i_m/C/C-ADDI16SP-01", + "rv64i_m/C/C-ADDI4SPN-01", + "rv64i_m/C/C-ADDIW-01", + "rv64i_m/C/C-ADDW-01", + "rv64i_m/C/C-AND-01", + "rv64i_m/C/C-ANDI-01", + "rv64i_m/C/C-BEQZ-01", + "rv64i_m/C/C-BNEZ-01", + "rv64i_m/C/C-J-01", + "rv64i_m/C/C-JALR-01", + "rv64i_m/C/C-JR-01", + "rv64i_m/C/C-LD-01", + "rv64i_m/C/C-LDSP-01", + "rv64i_m/C/C-LI-01", + "rv64i_m/C/C-LUI-01", + "rv64i_m/C/C-LW-01", + "rv64i_m/C/C-LWSP-01", + "rv64i_m/C/C-MV-01", + "rv64i_m/C/C-OR-01", + "rv64i_m/C/C-SD-01", + "rv64i_m/C/C-SDSP-01", + "rv64i_m/C/C-SLLI-01", + "rv64i_m/C/C-SRAI-01", + "rv64i_m/C/C-SRLI-01", + "rv64i_m/C/C-SUB-01", + "rv64i_m/C/C-SUBW-01", + "rv64i_m/C/C-SW-01", + "rv64i_m/C/C-SWSP-01", + "rv64i_m/C/C-XOR-01", + "rv64i_m/C/I-C-EBREAK-01", + "rv64i_m/C/I-C-NOP-01" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01.S" + "rv64i_m/I/I-MISALIGN_JMP-01" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01.S", - "rv64i_m/I/ADD-01.S", - "rv64i_m/I/ADDI-01.S", - "rv64i_m/I/ADDIW-01.S", - "rv64i_m/I/ADDW-01.S", - "rv64i_m/I/AND-01.S", - "rv64i_m/I/ANDI-01.S", - "rv64i_m/I/AUIPC-01.S", - "rv64i_m/I/BEQ-01.S", - "rv64i_m/I/BGE-01.S", - "rv64i_m/I/BGEU-01.S", - "rv64i_m/I/BLT-01.S", - "rv64i_m/I/BLTU-01.S", - "rv64i_m/I/BNE-01.S", - "rv64i_m/I/I-DELAY_SLOTS-01.S", - "rv64i_m/I/I-EBREAK-01.S", - "rv64i_m/I/I-ECALL-01.S", - "rv64i_m/I/I-ENDIANESS-01.S", - "rv64i_m/I/I-IO-01.S", -// "rv64i_m/I/I-MISALIGN_JMP-01.S", - "rv64i_m/I/I-MISALIGN_LDST-01.S", - "rv64i_m/I/I-NOP-01.S", - "rv64i_m/I/I-RF_size-01.S", - "rv64i_m/I/I-RF_width-01.S", - "rv64i_m/I/I-RF_x0-01.S", - "rv64i_m/I/JAL-01.S", - "rv64i_m/I/JALR-01.S", - "rv64i_m/I/LB-01.S", - "rv64i_m/I/LBU-01.S", - "rv64i_m/I/LD-01.S", - "rv64i_m/I/LH-01.S", - "rv64i_m/I/LHU-01.S", - "rv64i_m/I/LUI-01.S", - "rv64i_m/I/LW-01.S", - "rv64i_m/I/LWU-01.S", - "rv64i_m/I/OR-01.S", - "rv64i_m/I/ORI-01.S", - "rv64i_m/I/SB-01.S", - "rv64i_m/I/SD-01.S", - "rv64i_m/I/SH-01.S", - "rv64i_m/I/SLL-01.S", - "rv64i_m/I/SLLI-01.S", - "rv64i_m/I/SLLIW-01.S", - "rv64i_m/I/SLLW-01.S", - "rv64i_m/I/SLT-01.S", - "rv64i_m/I/SLTI-01.S", - "rv64i_m/I/SLTIU-01.S", - "rv64i_m/I/SLTU-01.S", - "rv64i_m/I/SRA-01.S", - "rv64i_m/I/SRAI-01.S", - "rv64i_m/I/SRAIW-01.S", - "rv64i_m/I/SRAW-01.S", - "rv64i_m/I/SRL-01.S", - "rv64i_m/I/SRLI-01.S", - "rv64i_m/I/SRLIW-01.S", - "rv64i_m/I/SRLW-01.S", - "rv64i_m/I/SUB-01.S", - "rv64i_m/I/SUBW-01.S", - "rv64i_m/I/SW-01.S", - "rv64i_m/I/XOR-01.S", - "rv64i_m/I/XORI-01.S" + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/ADD-01", + "rv64i_m/I/ADDI-01", + "rv64i_m/I/ADDIW-01", + "rv64i_m/I/ADDW-01", + "rv64i_m/I/AND-01", + "rv64i_m/I/ANDI-01", + "rv64i_m/I/AUIPC-01", + "rv64i_m/I/BEQ-01", + "rv64i_m/I/BGE-01", + "rv64i_m/I/BGEU-01", + "rv64i_m/I/BLT-01", + "rv64i_m/I/BLTU-01", + "rv64i_m/I/BNE-01", + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/I-EBREAK-01", + "rv64i_m/I/I-ECALL-01", + "rv64i_m/I/I-ENDIANESS-01", + "rv64i_m/I/I-IO-01", +// "rv64i_m/I/I-MISALIGN_JMP-01", + "rv64i_m/I/I-MISALIGN_LDST-01", + "rv64i_m/I/I-NOP-01", + "rv64i_m/I/I-RF_size-01", + "rv64i_m/I/I-RF_width-01", + "rv64i_m/I/I-RF_x0-01", + "rv64i_m/I/JAL-01", + "rv64i_m/I/JALR-01", + "rv64i_m/I/LB-01", + "rv64i_m/I/LBU-01", + "rv64i_m/I/LD-01", + "rv64i_m/I/LH-01", + "rv64i_m/I/LHU-01", + "rv64i_m/I/LUI-01", + "rv64i_m/I/LW-01", + "rv64i_m/I/LWU-01", + "rv64i_m/I/OR-01", + "rv64i_m/I/ORI-01", + "rv64i_m/I/SB-01", + "rv64i_m/I/SD-01", + "rv64i_m/I/SH-01", + "rv64i_m/I/SLL-01", + "rv64i_m/I/SLLI-01", + "rv64i_m/I/SLLIW-01", + "rv64i_m/I/SLLW-01", + "rv64i_m/I/SLT-01", + "rv64i_m/I/SLTI-01", + "rv64i_m/I/SLTIU-01", + "rv64i_m/I/SLTU-01", + "rv64i_m/I/SRA-01", + "rv64i_m/I/SRAI-01", + "rv64i_m/I/SRAIW-01", + "rv64i_m/I/SRAW-01", + "rv64i_m/I/SRL-01", + "rv64i_m/I/SRLI-01", + "rv64i_m/I/SRLIW-01", + "rv64i_m/I/SRLW-01", + "rv64i_m/I/SUB-01", + "rv64i_m/I/SUBW-01", + "rv64i_m/I/SW-01", + "rv64i_m/I/XOR-01", + "rv64i_m/I/XORI-01" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01.S", - "rv32i_m/M/DIVU-01.S", - "rv32i_m/M/MUL-01.S", - "rv32i_m/M/MULH-01.S", - "rv32i_m/M/MULHSU-01.S", - "rv32i_m/M/MULHU-01.S", - "rv32i_m/M/REM-01.S", - "rv32i_m/M/REMU-01.S" + "rv32i_m/M/DIV-01", + "rv32i_m/M/DIVU-01", + "rv32i_m/M/MUL-01", + "rv32i_m/M/MULH-01", + "rv32i_m/M/MULHSU-01", + "rv32i_m/M/MULHU-01", + "rv32i_m/M/REM-01", + "rv32i_m/M/REMU-01" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01.S", - "rv32i_m/C/C-ADDI-01.S", - "rv32i_m/C/C-ADDI16SP-01.S", - "rv32i_m/C/C-ADDI4SPN-01.S", - "rv32i_m/C/C-AND-01.S", - "rv32i_m/C/C-ANDI-01.S", - "rv32i_m/C/C-BEQZ-01.S", - "rv32i_m/C/C-BNEZ-01.S", - "rv32i_m/C/C-J-01.S", - "rv32i_m/C/C-JAL-01.S", - "rv32i_m/C/C-JALR-01.S", - "rv32i_m/C/C-JR-01.S", - "rv32i_m/C/C-LI-01.S", - "rv32i_m/C/C-LUI-01.S", - "rv32i_m/C/C-LW-01.S", - "rv32i_m/C/C-LWSP-01.S", - "rv32i_m/C/C-MV-01.S", - "rv32i_m/C/C-OR-01.S", - "rv32i_m/C/C-SLLI-01.S", - "rv32i_m/C/C-SRAI-01.S", - "rv32i_m/C/C-SRLI-01.S", - "rv32i_m/C/C-SUB-01.S", - "rv32i_m/C/C-SW-01.S", - "rv32i_m/C/C-SWSP-01.S", - "rv32i_m/C/C-XOR-01.S", - "rv32i_m/C/I-C-EBREAK-01.S", - "rv32i_m/C/I-C-NOP-01.S" + "rv32i_m/C/C-ADD-01", + "rv32i_m/C/C-ADDI-01", + "rv32i_m/C/C-ADDI16SP-01", + "rv32i_m/C/C-ADDI4SPN-01", + "rv32i_m/C/C-AND-01", + "rv32i_m/C/C-ANDI-01", + "rv32i_m/C/C-BEQZ-01", + "rv32i_m/C/C-BNEZ-01", + "rv32i_m/C/C-J-01", + "rv32i_m/C/C-JAL-01", + "rv32i_m/C/C-JALR-01", + "rv32i_m/C/C-JR-01", + "rv32i_m/C/C-LI-01", + "rv32i_m/C/C-LUI-01", + "rv32i_m/C/C-LW-01", + "rv32i_m/C/C-LWSP-01", + "rv32i_m/C/C-MV-01", + "rv32i_m/C/C-OR-01", + "rv32i_m/C/C-SLLI-01", + "rv32i_m/C/C-SRAI-01", + "rv32i_m/C/C-SRLI-01", + "rv32i_m/C/C-SUB-01", + "rv32i_m/C/C-SW-01", + "rv32i_m/C/C-SWSP-01", + "rv32i_m/C/C-XOR-01", + "rv32i_m/C/I-C-EBREAK-01", + "rv32i_m/C/I-C-NOP-01" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01.S" + "rv32i_m/I/I-MISALIGN_JMP-01" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01.S", - "rv32i_m/I/ADDI-01.S", - "rv32i_m/I/AND-01.S", - "rv32i_m/I/ANDI-01.S", - "rv32i_m/I/AUIPC-01.S", - "rv32i_m/I/BEQ-01.S", - "rv32i_m/I/BGE-01.S", - "rv32i_m/I/BGEU-01.S", - "rv32i_m/I/BLT-01.S", - "rv32i_m/I/BLTU-01.S", - "rv32i_m/I/BNE-01.S", - "rv32i_m/I/I-DELAY_SLOTS-01.S", - "rv32i_m/I/I-EBREAK-01.S", - "rv32i_m/I/I-ECALL-01.S", - "rv32i_m/I/I-ENDIANESS-01.S", - "rv32i_m/I/I-IO-01.S", -// "rv32i_m/I/I-MISALIGN_JMP-01.S", - "rv32i_m/I/I-MISALIGN_LDST-01.S", - "rv32i_m/I/I-NOP-01.S", - "rv32i_m/I/I-RF_size-01.S", - "rv32i_m/I/I-RF_width-01.S", - "rv32i_m/I/I-RF_x0-01.S", - "rv32i_m/I/JAL-01.S", - "rv32i_m/I/JALR-01.S", - "rv32i_m/I/LB-01.S", - "rv32i_m/I/LBU-01.S", - "rv32i_m/I/LH-01.S", - "rv32i_m/I/LHU-01.S", - "rv32i_m/I/LUI-01.S", - "rv32i_m/I/LW-01.S", - "rv32i_m/I/OR-01.S", - "rv32i_m/I/ORI-01.S", - "rv32i_m/I/SB-01.S", - "rv32i_m/I/SH-01.S", - "rv32i_m/I/SLL-01.S", - "rv32i_m/I/SLLI-01.S", - "rv32i_m/I/SLT-01.S", - "rv32i_m/I/SLTI-01.S", - "rv32i_m/I/SLTIU-01.S", - "rv32i_m/I/SLTU-01.S", - "rv32i_m/I/SRA-01.S", - "rv32i_m/I/SRAI-01.S", - "rv32i_m/I/SRL-01.S", - "rv32i_m/I/SRLI-01.S", - "rv32i_m/I/SUB-01.S", - "rv32i_m/I/SW-01.S", - "rv32i_m/I/XOR-01.S", - "rv32i_m/I/XORI-01.S" + "rv32i_m/I/ADD-01", + "rv32i_m/I/ADDI-01", + "rv32i_m/I/AND-01", + "rv32i_m/I/ANDI-01", + "rv32i_m/I/AUIPC-01", + "rv32i_m/I/BEQ-01", + "rv32i_m/I/BGE-01", + "rv32i_m/I/BGEU-01", + "rv32i_m/I/BLT-01", + "rv32i_m/I/BLTU-01", + "rv32i_m/I/BNE-01", + "rv32i_m/I/I-DELAY_SLOTS-01", + "rv32i_m/I/I-EBREAK-01", + "rv32i_m/I/I-ECALL-01", + "rv32i_m/I/I-ENDIANESS-01", + "rv32i_m/I/I-IO-01", +// "rv32i_m/I/I-MISALIGN_JMP-01", + "rv32i_m/I/I-MISALIGN_LDST-01", + "rv32i_m/I/I-NOP-01", + "rv32i_m/I/I-RF_size-01", + "rv32i_m/I/I-RF_width-01", + "rv32i_m/I/I-RF_x0-01", + "rv32i_m/I/JAL-01", + "rv32i_m/I/JALR-01", + "rv32i_m/I/LB-01", + "rv32i_m/I/LBU-01", + "rv32i_m/I/LH-01", + "rv32i_m/I/LHU-01", + "rv32i_m/I/LUI-01", + "rv32i_m/I/LW-01", + "rv32i_m/I/OR-01", + "rv32i_m/I/ORI-01", + "rv32i_m/I/SB-01", + "rv32i_m/I/SH-01", + "rv32i_m/I/SLL-01", + "rv32i_m/I/SLLI-01", + "rv32i_m/I/SLT-01", + "rv32i_m/I/SLTI-01", + "rv32i_m/I/SLTIU-01", + "rv32i_m/I/SLTU-01", + "rv32i_m/I/SRA-01", + "rv32i_m/I/SRAI-01", + "rv32i_m/I/SRL-01", + "rv32i_m/I/SRLI-01", + "rv32i_m/I/SUB-01", + "rv32i_m/I/SW-01", + "rv32i_m/I/XOR-01", + "rv32i_m/I/XORI-01" }; - string wally64a[] = '{ + string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; - string wally32a[] = '{ + string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", "rv32i_m/privilege/src/WALLY-lrsc-01.S" - }; + }; string arch64priv[] = '{ `RISCVARCHTEST, @@ -1366,65 +1366,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; - string arch64zba[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add.uw-01.S" - }; - -string arch64zbb[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/rev8-01.S", - "rv64i_m/B/src/andn-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/rol-01.S" -}; - -string arch64zbc[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S" -}; - -string arch64zbs[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S" -}; - string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From ea87a6b856e1522357c147c15942c963c1735d46 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 14:16:07 -0700 Subject: [PATCH 179/183] fixed sim-wally-batch --- sim/sim-wally-batch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch index 4fa06d3c..46c35c75 100755 --- a/sim/sim-wally-batch +++ b/sim/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-batch.do rv32gc wally32priv" \ No newline at end of file +vsim -c -do "do wally-batch.do rv32gc wally32priv" From fee7abbbd9e2c2cd909e4108b4aa66687c38b3c2 Mon Sep 17 00:00:00 2001 From: James Stine Date: Wed, 22 Mar 2023 16:23:27 -0500 Subject: [PATCH 180/183] Change order of coverage and all in sim directory - order causing issue with compilation process of regression tests --- sim/Makefile | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 1c31e1f2..bf6255b3 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,3 +1,20 @@ + +all: riscoftests memfiles + # *** Build old tests/imperas-riscv-tests for now; + # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test + # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired + #make -C ../tests/imperas-riscv-tests --jobs + #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs + # Only compile Imperas tests if they are installed locally. + # They are usually a symlink to $RISCV/imperas-riscv-tests and only + # get compiled there manually during installation + #make -C ../addins/imperas-riscv-tests + #make -C ../addins/imperas-riscv-tests XLEN=64 + #cd ../addins/imperas-riscv-tests; elf2hex.sh + #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump + # Link Linux test vectors + #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh + coverage: #make -C ../tests/coverage --jobs #iter-elf.bash --cover --search ../tests/coverage @@ -21,22 +38,6 @@ coverage: # vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt vcover report -details -threshH 100 -html cov/cov.ucdb -all: riscoftests memfiles - # *** Build old tests/imperas-riscv-tests for now; - # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test - # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired - #make -C ../tests/imperas-riscv-tests --jobs - #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs - # Only compile Imperas tests if they are installed locally. - # They are usually a symlink to $RISCV/imperas-riscv-tests and only - # get compiled there manually during installation - #make -C ../addins/imperas-riscv-tests - #make -C ../addins/imperas-riscv-tests XLEN=64 - #cd ../addins/imperas-riscv-tests; elf2hex.sh - #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump - # Link Linux test vectors - #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh - allclean: clean all clean: From 9980e0153bd556ef05fde7fe2a3ba25679bf2c76 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 15:44:26 -0700 Subject: [PATCH 181/183] restored arch 64 bit manip tests --- testbench/tests.vh | 59 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/testbench/tests.vh b/testbench/tests.vh index 17d9fea0..668da4b7 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1366,6 +1366,65 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; +string arch64zba[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S" + }; + +string arch64zbb[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S" +}; + +string arch64zbc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S" +}; + +string arch64zbs[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S" +}; + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From 07f8b26557a509a8fbe9eaaecad001dbaa1337e7 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 22 Mar 2023 15:51:08 -0700 Subject: [PATCH 182/183] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f7abf0ba..03893ca0 100644 --- a/README.md +++ b/README.md @@ -62,7 +62,7 @@ This section describes the open source toolchain installation. These steps shou ## TL;DR Open Source Tool-chain Installation -The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. +The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. $ sudo wally-tool-chain-install.sh From 76c261723917239445f38a34990d277a740d5c6f Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 22 Mar 2023 16:11:59 -0700 Subject: [PATCH 183/183] Updating install instructions --- Install | 333 -------------------------------- README.md | 2 +- bin/wally-tool-chain-install.sh | 5 + 3 files changed, 6 insertions(+), 334 deletions(-) delete mode 100644 Install diff --git a/Install b/Install deleted file mode 100644 index 47a91ddd..00000000 --- a/Install +++ /dev/null @@ -1,333 +0,0 @@ -Complete Wally Installation guide -Formally RISC-V System on Chip Design Appendix D - -Sections: -1. RISC-V Tool Installation (Sys Admin) -2. Core-v-wally Repo Installation -3. Build and Run Regression Tests - -Section 1 tool install should be done once by a system admin with root access. The specific details may need to be -adjusted as some tools may already be present on the system. This guide assumes all compiled from source tools are -installed at base diretory $RISCV. - -* Tool-chain Installation (Sys Admin) - -** TL;DR Open Source Tool-chain Installation - - The installing details are involved, but can be skipped using the following script. wally-tool-chain-install.sh installs the open source tools to RISCV=/opt/riscv by default. Change by supplying an alternate path as an argument, (ie. wally-tool-chain-install.sh /mnt/disk1/riscv). - This install script does NOT install buildroot or commercial EDA tools; Questa, Design Compiler, or Innovus. - It must be run as root or with sudo. - This script is tested for Ubuntu, 20.04 and 22.04 - - wally-tool-chain-install.sh - - The step by step instructions include Red Hat 8 / Fedora. - -** Detailed Tool-chain Instal Guide - Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server. This appendix describes how the system administrator installs RISC-V tools. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman. - -*** Open Source Software Installation - -Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools: - -1. The GCC cross-compiler -2. A RISC-V simulator such as Spike, Sail, and/or QEMU -3. Spike is easy to use but doesn’t support peripherals to boot Linux -4. QEMU is faster and can boot Linux -5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal - -This setup needs to be done once by the administrator - -Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer. - -Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. - -*** Create the $RISCV Directory - -First, set up a directory for riscv software in some place such as /opt/riscv. We will call this shared directory $RISCV. - -$ export RISCV=/opt/riscv -$ sudo mkdir $RISCV -$ sudo chown cad $RISCV -$ sudo su cad (or root, if you don’t have a cad account) -$ export RISCV=/opt/riscv -$ chmod 755 $RISCV -$ umask 0002 -$ cd $RISCV - -*** Update Tools - -Ubuntu users may need to install and update various tools. - -$ sudo apt update -$ sudo apt upgrade -$ sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog - -*** Install RISC-V GCC Cross-Compiler - -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. - -$ git clone https://github.com/riscv/riscv-gnu-toolchain -$ cd riscv-gnu-toolchain -$ git checkout 2022.09.21 -$ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -$ make --jobs - -Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. - -*** Install elf2hex - -We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: - -$ cd $RISCV -$ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH -$ git clone https://github.com/sifive/elf2hex.git -$ cd elf2hex -$ autoreconf -i -$ ./configure --target=riscv64-unknown-elf --prefix=$RISCV -$ make -$ make install - -Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly. Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly. - -*** Install RISC-V Spike Simulator - -Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions . - -$ cd $RISCV -$ git clone https://github.com/riscv-software-src/riscv-isa-sim -$ mkdir riscv-isa-sim/build -$ cd riscv-isa-sim/build -$ ../configure --prefix=$RISCV --enable-commitlog -$ make --jobs -$ make install -$ cd ../arch_test_target/spike/device -$ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include -$ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include - -*** Install Sail Simulator - -Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification. OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install. - -On Ubuntu, apt-get makes opam installation fairly simple. - -$ sudo apt-get install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev - -If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source. - -$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" - When prompted, put it in /usr/bin -$ sudo yum groupinstall 'Development Tools' -$ sudo yum -y install gmp-devel -$ sudo yum -y install zlib-devel -$ git clone https://github.com/Z3Prover/z3.git -$ cd z3 -$ python scripts/mk_make.py -$ cd build -$ make -$ sudo make install -$ cd ../.. -$ sudo pip3 install chardet==3.0.4 -$ sudo pip3 install urllib3==1.22 - -Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail. Run as the cad user because you will be installing Sail in $RISCV. - -$ sudo su cad -$ opam init -y --disable-sandboxing -$ opam switch create ocaml-base-compiler.4.06.1 -$ opam install sail -y - -Now you can clone and compile Sail-RISCV. This will take a while. - -$ eval $(opam config env) -$ cd $RISCV -$ git clone https://github.com/riscv/sail-riscv.git -$ cd sail-riscv -$ make -$ ARCH=RV32 make -$ ARCH=RV64 make -$ exit -$ sudo su -$ export RISCV=/opt/riscv -$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 -$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 -$ exit - -*** Install riscof - -riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite. - -It is most convenient if the sysadmin installs riscof into the server’s Python libraries: - -$ sudo pip3 install testresources -$ sudo pip3 install riscof --ignore-installed PyYAML - -However, riscof can also be installed and run locally by individual users. - -*** Install Verilator - -Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. -$ sudo apt install verilator - -*** Install QEMU Simulator - -QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. - - -The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF). - - -$ cd $RISCV -$ git clone --recurse-submodules https://github.com/qemu/qemu -$ cd qemu -$ git checkout v6.2.0 # last version tested; newer versions might be ok -$ ./configure --target-list=riscv64-softmmu --prefix=$RISCV -$ make --jobs -$ make install - -*** Cross-Compile Buildroot Linux - -Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. - -Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. - -To configure and build Buildroot: - -$ cd $RISCV -$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now -$ git clone https://github.com/buildroot/buildroot.git -$ cd buildroot -$ git checkout 2021.05 # last tested working version -$ cp -r $WALLY/linux/buildroot-config-src/wally ./board -$ cp ./board/wally/main.config .config -$ make --jobs - -To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. - -$ source ~/riscv-wally/setup.sh -$ cd $WALLY/linux/buildroot-scripts -$ make all - -Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. - -*** Download Synthesis Libraries - -For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process: - -$ cd $RISCV -$ mkdir cad -$ mkdir cad/lib -$ cd cad/lib -$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 - -** Installing EDA Tools - -Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. - -Siemens Quest is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. - -Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server. Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. - -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. - -Siemens Questa - -Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to -https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. - -Synopsys Design Compiler (DC) - -Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer - -$ firefox & -Navigate to https://solvnet.synopsys.com -Log in with your institution’s username and password -Click on Downloads, then scroll down to Synopsys Installer -Select the latest version (currently 5.4). Click Download Here, agree, -Click on SynopsysInstaller_v5.4.run -Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want. - Click on all parts and the .spf file, then click Download Files near the top -move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, -move other files into /cad/synopsys/downloads and work as user cad from here on -$ cd /cad/synopsys/installer_5.4 -$ ./SynopsysInstaller_v5.4.run -Accept default installation directory -$ ./installer -Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys -When prompted, enter your site ID -Follow prompts - -Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. - -The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation: - -/import/programs/synopsys/syn/S-2021.06-SP1 - -Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. - -The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. - -If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. - -Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection. - -* Core-v-wally Repo Installation -** TL;DR Repo Install -cd -git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally -cd riscv-wally -source ./setup.sh # may require some modification for your system. Always run once after opening a new terminal. - -** Detailed Repo Install Guide - -1. cd - Return to home directory. The home directory is sufficent a location for students. - However more advanced users may choose to clone wally into another directory. - -2. git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally - Clone the wally repository and all dependent submodules into subdirectory riscv-wally. - -3. cd riscv-wally - Change directory to the wally repos riscv-wally. - -4. source ./setup.sh - setup.sh is s configuration script which creates several environment variables. - WALLY: Absolute directory path to this repo clone. - MGLS_LICENSE_FILE: Siemens license server for questa sim (modelsim). If your computer - is already configured for questa remove variable. - SNPSLMD_LICENSE_FILE: Synopsys license server. If remove if already setup. - PATH: PATH is extended to include the installation directories for Siemens questa and - Synopsys design compiler. Remove if already setup. - Adds riscv-gnu-toolchain and spike to PATH. Adjust if installed in another location. - Or remove if already in the PATH variable. - Adds path to wally repo specific tools. (Must include.) - Adds path to verilator. Remove if already in path. - RISCV: This is the location of the riscv tool chain and other wally requirements. - See the Sys Admin section for details. - - If using ubuntu 22.04 setup.sh can be reduced to - - echo "Executing Wally setup.sh" - - # Path to Wally repository - #!/bin/bash - - WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) - export WALLY=$(cd "$WALLY" && pwd) - echo \$WALLY set to ${WALLY} - - # Path to RISC-V Tools - export RISCV=/opt/riscv # change this if you installed the tools in a different location - - # utility functions in Wally repository - export PATH=$PATH:$RISCV/bin - export PATH=$WALLY/bin:$PATH - -* Build and Run Regression Tests - Ensure the system tools are installed. - - cd - make - cd sim - ./regression-wally #(depends on having Questa installed) - diff --git a/README.md b/README.md index d8c2432d..668510a8 100644 --- a/README.md +++ b/README.md @@ -65,7 +65,7 @@ This section describes the open source toolchain installation. These steps shou The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. - $ sudo wally-tool-chain-install.sh + $ sudo bin/wally-tool-chain-install.sh ## Detailed Toolchain Install Guide diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 331ca13d..eaaac145 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -39,6 +39,7 @@ sudo mkdir -p $RISCV # UPDATE / UPGRADE apt update +apt upgrade # INSTALL apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev @@ -134,3 +135,7 @@ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo && echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ && sudo apt update \ && sudo apt install gh -y + +# Other python libraries used through the book. +sudo pip3 install matplotlib scipy sklearn adjustText leif +