From 3ea4dd48981e1576dfc56c9186db494302e8de3b Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 11 Jan 2023 14:03:44 -0800 Subject: [PATCH] Changed Wally to CORE-V Wally --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cacheLRU.sv | 2 +- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/cache/cacheway.sv | 2 +- pipelined/src/cache/subcachelineread.sv | 2 +- pipelined/src/ebu/ahbcacheinterface.sv | 2 +- pipelined/src/ebu/ahbinterface.sv | 2 +- pipelined/src/ebu/amoalu.sv | 2 +- pipelined/src/ebu/buscachefsm.sv | 2 +- pipelined/src/ebu/busfsm.sv | 2 +- pipelined/src/ebu/controllerinputstage.sv | 2 +- pipelined/src/ebu/ebu.sv | 2 +- pipelined/src/fpu/fclassify.sv | 2 +- pipelined/src/fpu/fcmp.sv | 2 +- pipelined/src/fpu/fctrl.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 2 +- pipelined/src/fpu/fhazard.sv | 2 +- pipelined/src/fpu/fma/fma.sv | 2 +- pipelined/src/fpu/fma/fmaadd.sv | 2 +- pipelined/src/fpu/fma/fmaalign.sv | 2 +- pipelined/src/fpu/fma/fmaexpadd.sv | 2 +- pipelined/src/fpu/fma/fmalza.sv | 2 +- pipelined/src/fpu/fma/fmamult.sv | 2 +- pipelined/src/fpu/fma/fmasign.sv | 2 +- pipelined/src/fpu/fpu.sv | 2 +- pipelined/src/fpu/fregfile.sv | 2 +- pipelined/src/fpu/fsgninj.sv | 2 +- pipelined/src/fpu/postproc/cvtshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/divshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/flags.sv | 2 +- pipelined/src/fpu/postproc/fmashiftcalc.sv | 2 +- pipelined/src/fpu/postproc/negateintres.sv | 2 +- pipelined/src/fpu/postproc/normshift.sv | 2 +- pipelined/src/fpu/postproc/postprocess.sv | 2 +- pipelined/src/fpu/postproc/resultsign.sv | 2 +- pipelined/src/fpu/postproc/round.sv | 2 +- pipelined/src/fpu/postproc/roundsign.sv | 2 +- pipelined/src/fpu/postproc/shiftcorrection.sv | 2 +- pipelined/src/fpu/postproc/specialcase.sv | 2 +- pipelined/src/fpu/unpack.sv | 2 +- pipelined/src/fpu/unpackinput.sv | 2 +- pipelined/src/generic/adder.sv | 2 +- pipelined/src/generic/aplusbeq0.sv | 2 +- pipelined/src/generic/arrs.sv | 2 +- pipelined/src/generic/binencoder.sv | 2 +- pipelined/src/generic/clockgater.sv | 2 +- pipelined/src/generic/counter.sv | 2 +- pipelined/src/generic/csa.sv | 2 +- pipelined/src/generic/decoder.sv | 2 +- pipelined/src/generic/flop/flop.sv | 2 +- pipelined/src/generic/flop/flopen.sv | 2 +- pipelined/src/generic/flop/flopenl.sv | 2 +- pipelined/src/generic/flop/flopenr.sv | 2 +- pipelined/src/generic/flop/flopenrc.sv | 2 +- pipelined/src/generic/flop/flopens.sv | 2 +- pipelined/src/generic/flop/flopr.sv | 2 +- pipelined/src/generic/flop/floprc.sv | 2 +- pipelined/src/generic/flop/synchronizer.sv | 2 +- pipelined/src/generic/lzc.sv | 2 +- pipelined/src/generic/mem/ram1p1rwbe.sv | 2 +- pipelined/src/generic/mem/ram2p1r1wb.sv | 2 +- pipelined/src/generic/mem/ram2p1rwbefix.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 2 +- pipelined/src/generic/mux.sv | 2 +- pipelined/src/generic/neg.sv | 2 +- pipelined/src/generic/onehotdecoder.sv | 2 +- pipelined/src/generic/or_rows.sv | 2 +- pipelined/src/generic/priorityonehot.sv | 2 +- pipelined/src/generic/prioritythermometer.sv | 2 +- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/ieu/alu.sv | 2 +- pipelined/src/ieu/comparator.sv | 2 +- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ieu/datapath.sv | 2 +- pipelined/src/ieu/extend.sv | 2 +- pipelined/src/ieu/forward.sv | 2 +- pipelined/src/ieu/ieu.sv | 2 +- pipelined/src/ieu/regfile.sv | 2 +- pipelined/src/ieu/shifter.sv | 2 +- pipelined/src/ifu/BTBPredictor.sv | 2 +- pipelined/src/ifu/RAsPredictor.sv | 2 +- pipelined/src/ifu/bpred.sv | 2 +- pipelined/src/ifu/decompress.sv | 2 +- pipelined/src/ifu/foldedgshare.sv | 2 +- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/globalhistory.sv | 2 +- pipelined/src/ifu/gshare.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/ifu/irom.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor2.sv | 2 +- pipelined/src/ifu/satCounter2.sv | 2 +- pipelined/src/ifu/speculativeglobalhistory.sv | 2 +- pipelined/src/ifu/speculativegshare.sv | 2 +- pipelined/src/ifu/spillsupport.sv | 2 +- pipelined/src/ifu/twoBitPredictor.sv | 2 +- pipelined/src/lsu/atomic.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 +- pipelined/src/lsu/endianswap.sv | 2 +- pipelined/src/lsu/lrsc.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/lsu/subwordread.sv | 2 +- pipelined/src/lsu/subwordwrite.sv | 2 +- pipelined/src/lsu/swbytemask.sv | 2 +- pipelined/src/mdu/intdivrestoring.sv | 2 +- pipelined/src/mdu/intdivrestoringstep.sv | 2 +- pipelined/src/mdu/mdu.sv | 2 +- pipelined/src/mdu/mul.sv | 2 +- pipelined/src/mmu/adrdec.sv | 2 +- pipelined/src/mmu/adrdecs.sv | 2 +- pipelined/src/mmu/hptw.sv | 2 +- pipelined/src/mmu/mmu.sv | 2 +- pipelined/src/mmu/pmachecker.sv | 2 +- pipelined/src/mmu/pmpadrdec.sv | 2 +- pipelined/src/mmu/pmpchecker.sv | 2 +- pipelined/src/mmu/tlb.sv | 2 +- pipelined/src/mmu/tlbcam.sv | 2 +- pipelined/src/mmu/tlbcamline.sv | 2 +- pipelined/src/mmu/tlbcontrol.sv | 2 +- pipelined/src/mmu/tlblru.sv | 2 +- pipelined/src/mmu/tlbmixer.sv | 2 +- pipelined/src/mmu/tlbram.sv | 2 +- pipelined/src/mmu/tlbramline.sv | 2 +- pipelined/src/mmu/vm64check.sv | 2 +- pipelined/src/privileged/csr.sv | 2 +- pipelined/src/privileged/csrc.sv | 2 +- pipelined/src/privileged/csri.sv | 2 +- pipelined/src/privileged/csrm.sv | 2 +- pipelined/src/privileged/csrs.sv | 2 +- pipelined/src/privileged/csrsr.sv | 2 +- pipelined/src/privileged/csru.sv | 2 +- pipelined/src/privileged/privdec.sv | 2 +- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/privmode.sv | 2 +- pipelined/src/privileged/privpiperegs.sv | 2 +- pipelined/src/privileged/trap.sv | 2 +- pipelined/src/uncore/ahbapbbridge.sv | 2 +- pipelined/src/uncore/clint_apb.sv | 2 +- pipelined/src/uncore/gpio_apb.sv | 2 +- pipelined/src/uncore/plic_apb.sv | 2 +- pipelined/src/uncore/ram_ahb.sv | 2 +- pipelined/src/uncore/rom_ahb.sv | 2 +- pipelined/src/uncore/sdc/SDC.sv | 2 +- pipelined/src/uncore/sdc/SDCcounter.sv | 2 +- pipelined/src/uncore/sdc/clkdivider.sv | 2 +- pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/crc7_pipo.sv | 2 +- pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/piso_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv | 2 +- pipelined/src/uncore/sdc/sd_clk_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_dat_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_top.sv | 2 +- pipelined/src/uncore/sdc/simple_timer.sv | 2 +- pipelined/src/uncore/sdc/sipo_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/up_down_counter.sv | 2 +- pipelined/src/uncore/uartPC16550D.sv | 2 +- pipelined/src/uncore/uart_apb.sv | 2 +- pipelined/src/uncore/uncore.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- pipelined/src/wally/wallypipelinedsoc.sv | 2 +- pipelined/src/wally/wallypipelinedsocwrapper.v | 2 +- 179 files changed, 179 insertions(+), 179 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index f62de4fe..23a90db2 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -6,7 +6,7 @@ // // Purpose: Storage for data and meta data. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index 7485a5d8..36005e4e 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -6,7 +6,7 @@ // Tested for Powers of 2. // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 48b2aec8..657f1f97 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 20221441..4d25b8d3 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -6,7 +6,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 2e7c1e96..6a317e13 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 1bb8bb6a..6263f497 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index adb6ef38..98134afe 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/amoalu.sv b/pipelined/src/ebu/amoalu.sv index a771a8cd..5e1dd850 100644 --- a/pipelined/src/ebu/amoalu.sv +++ b/pipelined/src/ebu/amoalu.sv @@ -6,7 +6,7 @@ // // Purpose: Performs AMO operations // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 447da7b8..38b0b8ff 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 5f47fa57..41be2d2d 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/controllerinputstage.sv b/pipelined/src/ebu/controllerinputstage.sv index 2cd474f0..d84add27 100644 --- a/pipelined/src/ebu/controllerinputstage.sv +++ b/pipelined/src/ebu/controllerinputstage.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index b0f680b3..333da0dd 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index 3e0cf82a..c2dfa988 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 2c2b5d34..09881ff0 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -7,7 +7,7 @@ // // Purpose: Floating-point comparison unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 66602d04..1363d18e 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index b6b4af5c..a47031a7 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 9ff120d4..e5f58b6b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index d0580984..c4cd3918 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 16687442..863a7603 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 02a84bf1..4649e9a5 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 7687ce14..a2175451 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 84b3bfba..4a1d7d13 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 40ae2460..2fa3fb98 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index d9a72205..fce04715 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Quotient Digit Selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index e82732f7..ef725d97 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 Quotient Digit Selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index c9d8ff40..4751db29 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Quotient Digit Selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 73abf358..c4e341d0 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index bb2ef154..a7f3f214 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index bb35e4fd..04b36c44 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index a9791f73..01b30eb0 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index db1f5522..281f7460 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index 156acea8..71150255 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index e290fb40..cd899ebd 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv index fe412b19..a043df7d 100644 --- a/pipelined/src/fpu/fma/fmaalign.sv +++ b/pipelined/src/fpu/fma/fmaalign.sv @@ -7,7 +7,7 @@ // // Purpose: FMA alginment shift // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv index 81db8c81..dfb31dc4 100644 --- a/pipelined/src/fpu/fma/fmaexpadd.sv +++ b/pipelined/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv index 51a992b0..b9065f05 100644 --- a/pipelined/src/fpu/fma/fmalza.sv +++ b/pipelined/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv index 6bb480d6..5f30c166 100644 --- a/pipelined/src/fpu/fma/fmamult.sv +++ b/pipelined/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv index 7f86ee2c..2664d6c5 100644 --- a/pipelined/src/fpu/fma/fmasign.sv +++ b/pipelined/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 487ce46a..d9c82e9b 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index bf6ce671..393d25b1 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index e66ece11..4c2f1446 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv index eff29e10..8b6dc026 100644 --- a/pipelined/src/fpu/postproc/cvtshiftcalc.sv +++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index cab267f5..e2601211 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/flags.sv b/pipelined/src/fpu/postproc/flags.sv index 92299853..d8cd47b7 100644 --- a/pipelined/src/fpu/postproc/flags.sv +++ b/pipelined/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index 1e703431..3335b40f 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv index faeba4b9..8f9cc96d 100644 --- a/pipelined/src/fpu/postproc/negateintres.sv +++ b/pipelined/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/normshift.sv b/pipelined/src/fpu/postproc/normshift.sv index 1740ad21..95024c77 100644 --- a/pipelined/src/fpu/postproc/normshift.sv +++ b/pipelined/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index 9be14644..c4dcf9f3 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv index f85a1a0f..484d2132 100644 --- a/pipelined/src/fpu/postproc/resultsign.sv +++ b/pipelined/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/round.sv b/pipelined/src/fpu/postproc/round.sv index 0cba58eb..b14d39be 100644 --- a/pipelined/src/fpu/postproc/round.sv +++ b/pipelined/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv index 1fb497b2..0d376e7d 100644 --- a/pipelined/src/fpu/postproc/roundsign.sv +++ b/pipelined/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation ofr rounding // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv index 23fa66b8..0f1e6bd1 100644 --- a/pipelined/src/fpu/postproc/shiftcorrection.sv +++ b/pipelined/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv index 976b2e57..6e9e2156 100644 --- a/pipelined/src/fpu/postproc/specialcase.sv +++ b/pipelined/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 59023ef5..20fb8ed2 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 179e5d54..14a41475 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/adder.sv b/pipelined/src/generic/adder.sv index 58bab026..b5439a42 100644 --- a/pipelined/src/generic/adder.sv +++ b/pipelined/src/generic/adder.sv @@ -6,7 +6,7 @@ // // Purpose: Adder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/aplusbeq0.sv b/pipelined/src/generic/aplusbeq0.sv index afda700d..8dea1143 100644 --- a/pipelined/src/generic/aplusbeq0.sv +++ b/pipelined/src/generic/aplusbeq0.sv @@ -6,7 +6,7 @@ // // Purpose: Determine if A+B = 0. Used in FP divider. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/arrs.sv b/pipelined/src/generic/arrs.sv index 9d234985..3930314b 100644 --- a/pipelined/src/generic/arrs.sv +++ b/pipelined/src/generic/arrs.sv @@ -9,7 +9,7 @@ // arrs takes in the asynchronous reset and outputs an asynchronous // rising edge, but then syncs the falling edge to the posedge clk. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/binencoder.sv b/pipelined/src/generic/binencoder.sv index 7947ebdc..f62d2aee 100644 --- a/pipelined/src/generic/binencoder.sv +++ b/pipelined/src/generic/binencoder.sv @@ -5,7 +5,7 @@ // // Purpose: one-hot to binary encoding. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/clockgater.sv b/pipelined/src/generic/clockgater.sv index 4657354e..b3c2c689 100644 --- a/pipelined/src/generic/clockgater.sv +++ b/pipelined/src/generic/clockgater.sv @@ -6,7 +6,7 @@ // // Purpose: Clock gater model. Must use standard cell for synthesis. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/counter.sv b/pipelined/src/generic/counter.sv index c530654d..18e27884 100644 --- a/pipelined/src/generic/counter.sv +++ b/pipelined/src/generic/counter.sv @@ -6,7 +6,7 @@ // // Purpose: Counter with reset and enable // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/csa.sv b/pipelined/src/generic/csa.sv index 1c540de6..cffef432 100644 --- a/pipelined/src/generic/csa.sv +++ b/pipelined/src/generic/csa.sv @@ -6,7 +6,7 @@ // // Purpose: 3:2 carry-save adder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/decoder.sv b/pipelined/src/generic/decoder.sv index 7fa4f8ed..de1df16d 100644 --- a/pipelined/src/generic/decoder.sv +++ b/pipelined/src/generic/decoder.sv @@ -6,7 +6,7 @@ // // Purpose: Binary encoding to one-hot decoder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flop.sv b/pipelined/src/generic/flop/flop.sv index 35afda76..979c81b1 100644 --- a/pipelined/src/generic/flop/flop.sv +++ b/pipelined/src/generic/flop/flop.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopen.sv b/pipelined/src/generic/flop/flopen.sv index ea652aa0..8f447b91 100644 --- a/pipelined/src/generic/flop/flopen.sv +++ b/pipelined/src/generic/flop/flopen.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenl.sv b/pipelined/src/generic/flop/flopenl.sv index 4520089a..db79567a 100644 --- a/pipelined/src/generic/flop/flopenl.sv +++ b/pipelined/src/generic/flop/flopenl.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenr.sv b/pipelined/src/generic/flop/flopenr.sv index c0cac076..bd733aec 100644 --- a/pipelined/src/generic/flop/flopenr.sv +++ b/pipelined/src/generic/flop/flopenr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenrc.sv b/pipelined/src/generic/flop/flopenrc.sv index 4003c1ba..197c5591 100644 --- a/pipelined/src/generic/flop/flopenrc.sv +++ b/pipelined/src/generic/flop/flopenrc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopens.sv b/pipelined/src/generic/flop/flopens.sv index 2b17e01e..872d3490 100644 --- a/pipelined/src/generic/flop/flopens.sv +++ b/pipelined/src/generic/flop/flopens.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopr.sv b/pipelined/src/generic/flop/flopr.sv index 05f03bc8..1fe42277 100644 --- a/pipelined/src/generic/flop/flopr.sv +++ b/pipelined/src/generic/flop/flopr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/floprc.sv b/pipelined/src/generic/flop/floprc.sv index 76b73ca1..6d084d6c 100644 --- a/pipelined/src/generic/flop/floprc.sv +++ b/pipelined/src/generic/flop/floprc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/synchronizer.sv b/pipelined/src/generic/flop/synchronizer.sv index 6750ffbe..6e208e95 100644 --- a/pipelined/src/generic/flop/synchronizer.sv +++ b/pipelined/src/generic/flop/synchronizer.sv @@ -6,7 +6,7 @@ // // Purpose: Two-stage flip-flop synchronizer // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index fb8fbd1c..5a58cf42 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -5,7 +5,7 @@ // // Purpose: Leading Zero Counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index d203c500..374a9a0b 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index 504a7ea2..ee66e333 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -16,7 +16,7 @@ // example // mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index 36f87176..cc23b252 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 3c076e0c..6f6533a6 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -5,7 +5,7 @@ // // Purpose: Single-ported ROM // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mux.sv b/pipelined/src/generic/mux.sv index a63ae17f..d4f92667 100644 --- a/pipelined/src/generic/mux.sv +++ b/pipelined/src/generic/mux.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/neg.sv b/pipelined/src/generic/neg.sv index 82d9db33..f7947ce6 100644 --- a/pipelined/src/generic/neg.sv +++ b/pipelined/src/generic/neg.sv @@ -6,7 +6,7 @@ // // Purpose: 2's complement negator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/onehotdecoder.sv b/pipelined/src/generic/onehotdecoder.sv index eb340857..f1051969 100644 --- a/pipelined/src/generic/onehotdecoder.sv +++ b/pipelined/src/generic/onehotdecoder.sv @@ -6,7 +6,7 @@ // // Purpose: Bin to one hot decoder. Power of 2 only. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/or_rows.sv b/pipelined/src/generic/or_rows.sv index 77d47b5e..7f892f76 100644 --- a/pipelined/src/generic/or_rows.sv +++ b/pipelined/src/generic/or_rows.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv index e2c79cd6..1aa28c88 100644 --- a/pipelined/src/generic/priorityonehot.sv +++ b/pipelined/src/generic/priorityonehot.sv @@ -16,7 +16,7 @@ // in 01011101010100000 // out 00000000000100000 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv index 78f00d88..0e2ba7dc 100644 --- a/pipelined/src/generic/prioritythermometer.sv +++ b/pipelined/src/generic/prioritythermometer.sv @@ -12,7 +12,7 @@ // in 01011101010100000 // out 00000000000011111 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index f00837ab..d99cf394 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 0e2f5118..041712a7 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv index 103ca187..579f2c9c 100644 --- a/pipelined/src/ieu/comparator.sv +++ b/pipelined/src/ieu/comparator.sv @@ -6,7 +6,7 @@ // // Purpose: Branch comparison // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index 6fde524f..d6a204b0 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -6,7 +6,7 @@ // // Purpose: Top level controller module // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 346fab14..159d07f6 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -6,7 +6,7 @@ // // Purpose: Wally Integer Datapath // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index c9ec903a..feb7f9fb 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -6,7 +6,7 @@ // // Purpose: // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index b2581cc6..11fb4418 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -6,7 +6,7 @@ // // Purpose: Determine datapath forwarding // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 20fbe3a9..9f4a773d 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 8a937730..8ac09a91 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3-port register file // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv index 70e0bb6d..21573c6c 100644 --- a/pipelined/src/ieu/shifter.sv +++ b/pipelined/src/ieu/shifter.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index b8517b63..592d0f6f 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -9,7 +9,7 @@ // Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want // to encode to reduce storage), valid, target PC. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/RAsPredictor.sv index b75a8e20..b7fbbc5a 100644 --- a/pipelined/src/ifu/RAsPredictor.sv +++ b/pipelined/src/ifu/RAsPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 322321f1..29c3556f 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -9,7 +9,7 @@ // Purpose: Branch prediction unit // Produces a branch prediction based on branch history. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/decompress.sv b/pipelined/src/ifu/decompress.sv index d9d73856..044095f8 100644 --- a/pipelined/src/ifu/decompress.sv +++ b/pipelined/src/ifu/decompress.sv @@ -6,7 +6,7 @@ // // Purpose: Expand 16-bit compressed instructions to 32 bits // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/foldedgshare.sv index b6d57358..2665f318 100644 --- a/pipelined/src/ifu/foldedgshare.sv +++ b/pipelined/src/ifu/foldedgshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index 34b5115a..cf97039c 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/globalhistory.sv index 0d9156a5..d4f234ac 100644 --- a/pipelined/src/ifu/globalhistory.sv +++ b/pipelined/src/ifu/globalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/gshare.sv index 9fc7b082..2fbac5c5 100644 --- a/pipelined/src/ifu/gshare.sv +++ b/pipelined/src/ifu/gshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2e14a83a..d88ccdf5 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -7,7 +7,7 @@ // Purpose: Instrunction Fetch Unit // PC, branch prediction, instruction cache // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index c547b0a6..ef928431 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple instruction ROM -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 25959611..7e61d8c3 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/oldgsharepredictor.sv index d3115c41..627d2c33 100644 --- a/pipelined/src/ifu/oldgsharepredictor.sv +++ b/pipelined/src/ifu/oldgsharepredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/oldgsharepredictor2.sv index a652b650..047e9e6b 100644 --- a/pipelined/src/ifu/oldgsharepredictor2.sv +++ b/pipelined/src/ifu/oldgsharepredictor2.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/satCounter2.sv index 7873cb14..1a0d5a27 100644 --- a/pipelined/src/ifu/satCounter2.sv +++ b/pipelined/src/ifu/satCounter2.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit starting counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/speculativeglobalhistory.sv index d367caaf..7a099e74 100644 --- a/pipelined/src/ifu/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/speculativeglobalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv index 1ae611aa..0febd925 100644 --- a/pipelined/src/ifu/speculativegshare.sv +++ b/pipelined/src/ifu/speculativegshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 33691498..7835fc00 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -8,7 +8,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index 9ba98829..a7d2669a 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index b2a678ae..c61acd99 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -6,7 +6,7 @@ // // Purpose: atomic data path. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 716c7021..6e4689ef 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple memory with bus or cache. -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv index 0e8fe983..1b3497fa 100644 --- a/pipelined/src/lsu/endianswap.sv +++ b/pipelined/src/lsu/endianswap.sv @@ -6,7 +6,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index bcf6ae0e..f4a4b9ff 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -7,7 +7,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 3117d857..daf203f8 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -8,7 +8,7 @@ // Top level of the memory-stage core logic // Contains data cache, DTLB, subword read/write datapath, interface to external bus // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index de86b855..2b8854e5 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -6,7 +6,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 774e6a50..57607955 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -6,7 +6,7 @@ // // Purpose: Masking and muxing for subword writes // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv index d04a5855..433a5c91 100644 --- a/pipelined/src/lsu/swbytemask.sv +++ b/pipelined/src/lsu/swbytemask.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoring.sv b/pipelined/src/mdu/intdivrestoring.sv index 5d0b893a..59ecbe7d 100644 --- a/pipelined/src/mdu/intdivrestoring.sv +++ b/pipelined/src/mdu/intdivrestoring.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/pipelined/src/mdu/intdivrestoringstep.sv index f9a025d4..b37afd54 100644 --- a/pipelined/src/mdu/intdivrestoringstep.sv +++ b/pipelined/src/mdu/intdivrestoringstep.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mdu.sv b/pipelined/src/mdu/mdu.sv index 6dcb4791..0490642c 100644 --- a/pipelined/src/mdu/mdu.sv +++ b/pipelined/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mul.sv b/pipelined/src/mdu/mul.sv index d53ac074..a8c4e296 100644 --- a/pipelined/src/mdu/mul.sv +++ b/pipelined/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Multiply instructions // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdec.sv b/pipelined/src/mmu/adrdec.sv index c587ab07..6c0303cc 100644 --- a/pipelined/src/mmu/adrdec.sv +++ b/pipelined/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 40d55a95..8dc9c45c 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 8146ccaf..67e4a83b 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -11,7 +11,7 @@ // Purpose: Page Table Walker // Part of the Memory Management Unit (MMU) // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index a31c97f6..1949bf13 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index 871ceb72..f74cff2a 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpadrdec.sv b/pipelined/src/mmu/pmpadrdec.sv index 4b1e7d3d..fb3e2c61 100644 --- a/pipelined/src/mmu/pmpadrdec.sv +++ b/pipelined/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpchecker.sv b/pipelined/src/mmu/pmpchecker.sv index 12a8c751..c6f357a6 100644 --- a/pipelined/src/mmu/pmpchecker.sv +++ b/pipelined/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlb.sv b/pipelined/src/mmu/tlb.sv index 1ca57652..7d5e51bb 100644 --- a/pipelined/src/mmu/tlb.sv +++ b/pipelined/src/mmu/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcam.sv b/pipelined/src/mmu/tlbcam.sv index 2bcce393..79a1f21e 100644 --- a/pipelined/src/mmu/tlbcam.sv +++ b/pipelined/src/mmu/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcamline.sv b/pipelined/src/mmu/tlbcamline.sv index 84bafc9f..627f496d 100644 --- a/pipelined/src/mmu/tlbcamline.sv +++ b/pipelined/src/mmu/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index baf41e96..eb073513 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlblru.sv b/pipelined/src/mmu/tlblru.sv index ca553033..ee5ac7fe 100644 --- a/pipelined/src/mmu/tlblru.sv +++ b/pipelined/src/mmu/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbmixer.sv b/pipelined/src/mmu/tlbmixer.sv index efeb19d9..71e5ca91 100644 --- a/pipelined/src/mmu/tlbmixer.sv +++ b/pipelined/src/mmu/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbram.sv b/pipelined/src/mmu/tlbram.sv index 4712d46d..8b2c59d6 100644 --- a/pipelined/src/mmu/tlbram.sv +++ b/pipelined/src/mmu/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbramline.sv b/pipelined/src/mmu/tlbramline.sv index 42d8bf31..6c3a3079 100644 --- a/pipelined/src/mmu/tlbramline.sv +++ b/pipelined/src/mmu/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/vm64check.sv b/pipelined/src/mmu/vm64check.sv index 550937ac..ad4ff4ce 100644 --- a/pipelined/src/mmu/vm64check.sv +++ b/pipelined/src/mmu/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 82d500a7..003e5bf4 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 191aafd8..427c8152 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -9,7 +9,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index c363bb0d..9d0c6aff 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index f93e8fcf..1d621da9 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -8,7 +8,7 @@ // Purpose: Machine-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index 2e0e4d5b..d9590d0f 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 1550ef43..70505297 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 56df9503..0bf35694 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -8,7 +8,7 @@ // See RISC-V Privileged Mode Specification 20190608 Table 2.2 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 9febaa3d..d2729e9f 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index c8b7a21b..edaca1da 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index c962dc2f..1eb6b4db 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -7,7 +7,7 @@ // Purpose: Track privilege mode // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv index f0d4ea89..52761855 100644 --- a/pipelined/src/privileged/privpiperegs.sv +++ b/pipelined/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index d2d38fc2..05f1f6e9 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -7,7 +7,7 @@ // Purpose: Handle Traps: Exceptions and Interrupts // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv index 93d51ade..2a365695 100644 --- a/pipelined/src/uncore/ahbapbbridge.sv +++ b/pipelined/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv index b3a9802b..e80be7d7 100644 --- a/pipelined/src/uncore/clint_apb.sv +++ b/pipelined/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv index 22032fae..f84707a8 100644 --- a/pipelined/src/uncore/gpio_apb.sv +++ b/pipelined/src/uncore/gpio_apb.sv @@ -8,7 +8,7 @@ // See FE310-G002-Manual-v19p05 for specifications // No interrupts, drive strength, or pull-ups supported // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index 519fe4a0..bf580334 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -13,7 +13,7 @@ // Do we detect requests as level-triggered or edge-trigged? // If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests? // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index e3b72bd0..2a0a1b3f 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core, with AHB interface // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv index f68cffdc..9aba4d68 100644 --- a/pipelined/src/uncore/rom_ahb.sv +++ b/pipelined/src/uncore/rom_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip ROM, external to core // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv index 06320c52..f756e45e 100644 --- a/pipelined/src/uncore/sdc/SDC.sv +++ b/pipelined/src/uncore/sdc/SDC.sv @@ -6,7 +6,7 @@ // // Purpose: SDC interface to AHBLite BUS. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv index 39d75a2f..8009790f 100644 --- a/pipelined/src/uncore/sdc/SDCcounter.sv +++ b/pipelined/src/uncore/sdc/SDCcounter.sv @@ -7,7 +7,7 @@ // // Purpose: basic up counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv index 7875bf4e..44f58257 100644 --- a/pipelined/src/uncore/sdc/clkdivider.sv +++ b/pipelined/src/uncore/sdc/clkdivider.sv @@ -7,7 +7,7 @@ // // Purpose: clock divider for sd flash // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv index 257ee37c..4cc43211 100644 --- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv @@ -8,7 +8,7 @@ // Purpose: CRC16 generator SIPO using register_ce // w/o appending any zero-bits to the message // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv index 201b1ec2..797e62f6 100644 --- a/pipelined/src/uncore/sdc/crc7_pipo.sv +++ b/pipelined/src/uncore/sdc/crc7_pipo.sv @@ -9,7 +9,7 @@ // clock cycle! // w/o appending any zero-bits to the message // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv index ed3e5464..8f7fb928 100644 --- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv @@ -7,7 +7,7 @@ // Purpose: CRC7 generator SIPO using register_ce // w/o appending any zero-bits othe message // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv index 96f82a62..2d332b43 100644 --- a/pipelined/src/uncore/sdc/piso_generic_ce.sv +++ b/pipelined/src/uncore/sdc/piso_generic_ce.sv @@ -5,7 +5,7 @@ // Modified: Ross Thompson September 18, 2021 // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv index 80f3b95a..1956cbc7 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv index 71e77cbc..d0817972 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv index a6fae4c5..327a833c 100644 --- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_clk_fsm.sv @@ -15,7 +15,7 @@ // It must be synchronized with 50 MHz and held for a minimum period of a full // 400 KHz pulse width. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv index 38c2494c..b1b4a163 100644 --- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv @@ -6,7 +6,7 @@ // // Purpose: Finite state machine for the SD CMD bus // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv index 3f2d99f1..49ba94bf 100644 --- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_dat_fsm.sv @@ -8,7 +8,7 @@ // bus of the SD card. // 14 State Mealy FSM + Safe state = 15 State Mealy FSM // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv index cdc62d8e..7a9c35fa 100644 --- a/pipelined/src/uncore/sdc/sd_top.sv +++ b/pipelined/src/uncore/sdc/sd_top.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv index 9bbd32c2..0e6afa75 100644 --- a/pipelined/src/uncore/sdc/simple_timer.sv +++ b/pipelined/src/uncore/sdc/simple_timer.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv index c3d52686..ed55559d 100644 --- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv +++ b/pipelined/src/uncore/sdc/sipo_generic_ce.sv @@ -9,7 +9,7 @@ // bit first. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv index f0c47a2f..894df369 100644 --- a/pipelined/src/uncore/sdc/up_down_counter.sv +++ b/pipelined/src/uncore/sdc/up_down_counter.sv @@ -6,7 +6,7 @@ // // Purpose: basic up counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 211f7507..f627aca8 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -13,7 +13,7 @@ // Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 // Timeout not ye implemented*** // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index 2f562dad..f1d6fd7a 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -8,7 +8,7 @@ // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model *** // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 372b2dbf..1ca9d3cb 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -7,7 +7,7 @@ // Purpose: System-on-Chip components outside the core // Memories, peripherals, external bus control // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index b48dcd28..b6d04b62 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -6,7 +6,7 @@ // // Purpose: Pipelined RISC-V Processor // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 8f057854..69c3ce04 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsocwrapper.v b/pipelined/src/wally/wallypipelinedsocwrapper.v index faf76228..a812924c 100644 --- a/pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/pipelined/src/wally/wallypipelinedsocwrapper.v @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University //