From 3e8d3bae88799d3ec6ba54b498ff808265fab39a Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 9 Jun 2022 17:33:51 -0700 Subject: [PATCH] Changes made on 9th Jun --- pipelined/src/ebu/ahblite.sv | 10 +++++----- pipelined/src/lsu/busdp.sv | 2 +- pipelined/src/lsu/busfsm.sv | 16 +++++++++------- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index e4cc5edf..68561cba 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -115,11 +115,11 @@ module ahblite ( else if (LSUBusWrite) NextBusState = MEMWRITE; else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; - MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; + MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; else if (LSUTransComplete) NextBusState = IDLE; else NextBusState = MEMREAD; MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; - else if (LSUTransComplete) NextBusState = IDLE; + else if (LSUTransComplete) NextBusState = IDLE;// Ram cannot handle a read after a write, Do not send one. else NextBusState = MEMWRITE; INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD; else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE; @@ -155,7 +155,7 @@ module ahblite ( assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // delay write data by one cycle for - flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck | IFUBusInit | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); @@ -167,8 +167,8 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); - assign LSUBusInit = ((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE); + assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD) & HREADY; + assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE)) & HREADY; assign IFUBusAck = HREADY & (BusState == INSTRREAD); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 5139efdc..f1156b44 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -68,7 +68,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic BusStall, output logic BusCommittedM); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 1; logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [LOGWPL-1:0] WordCountDelayed; diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 37da283d..2285591c 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -65,7 +65,7 @@ module busfsm #(parameter integer WordCountThreshold, logic CntReset; logic WordCountFlag; logic [LOGWPL-1:0] NextWordCount; - logic UnCachedAccess; + logic UnCachedAccess, UnCachedRW; logic [2:0] LocalBurstType; @@ -97,6 +97,7 @@ module busfsm #(parameter integer WordCountThreshold, assign NextWordCount = WordCount + 1'b1; + assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag; @@ -138,21 +139,20 @@ module busfsm #(parameter integer WordCountThreshold, 3: LocalBurstType = 3'b011; // INCR4 7: LocalBurstType = 3'b101; // INCR8 15: LocalBurstType = 3'b111; // INCR16 - default: LocalBurstType = 3'b001; // No Burst + default: LocalBurstType = 3'b001; // INCR without end. endcase end - assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access. - assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; - assign LSUTransType = (|WordCount) & ~UnCachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag | UnCachedAccess) ? 2'b10 : 2'b00; + assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. + assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; + assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~WordCountFlag) ? 2'b10 : 2'b00; - assign CntReset = (BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine)) | LSUTransComplete; + assign CntReset = BusCurrState == STATE_BUS_READY; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE); @@ -164,6 +164,8 @@ module busfsm #(parameter integer WordCountThreshold, (BusCurrState == STATE_BUS_UNCACHED_READ); assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); + assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; + assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY;