From 67eb1f5c6b2af0c32ca780b836c2860c4ebfd155 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Mon, 19 Jul 2021 11:30:07 -0400
Subject: [PATCH] change sram1rw to have a small delay so that we don't have
 signals changing on clock edges

---
 wally-pipelined/src/cache/sram1rw.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/cache/sram1rw.sv b/wally-pipelined/src/cache/sram1rw.sv
index a7459388..2b2c2d60 100644
--- a/wally-pipelined/src/cache/sram1rw.sv
+++ b/wally-pipelined/src/cache/sram1rw.sv
@@ -15,7 +15,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
     always_ff @(posedge clk) begin
         ReadData <= StoredData[Addr];
         if (WriteEnable) begin
-            StoredData[Addr] <= WriteData;
+            StoredData[Addr] <= #1 WriteData;
         end
     end
 endmodule