From 3d794742e9ed55d1031960083a8d2f64bd40f0a2 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 23 Jun 2022 13:22:00 -0700 Subject: [PATCH] Updating new GPIO tests --- .../references/WALLY-gpio-01.reference_output | 12 +++++--- .../rv32i_m/privilege/src/WALLY-gpio-01.S | 28 +++++++++++++++++-- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output index 278e0aa7..e6fd4d7f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output @@ -1,7 +1,11 @@ +00000000 # test reset to zero 00000000 -00000000 -A5A5A5A5 +A5A5A5A5 # test output pins 5A5AFFFF -00000000 +00000000 # test input enables 5A5A0000 -A55A0000 +A55A0000 # test XOR +# A55A0000 # test interrupt pins +# 5AA5FFFF +# 00000000 +# 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S index e4792a78..38bc533b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S @@ -88,12 +88,34 @@ test_cases: .4byte input_en, 0xFFFF0000, write32_test # enable a few input pins .4byte input_val, 0x5A5A0000, read32_test # read part of pattern set above. -# =========== Test output enables(?) =========== - -.4byte output_en, 0xFFFFFFFF, write32_test # undo changes made to output enable # =========== Test XOR functionality =========== .4byte out_xor, 0xFF00FF00, write32_test # invert certain pin values .4byte input_val, 0xA55A0000, read32_test # read inverted pins and verify input enable is working +# =========== End of functioning tests =========== +# # =========== Test Interrupt Pending bits =========== + +# .4byte low_ip, 0xFFFFFFFF, write32_test # clear pending low interrupts +# .4byte high_ip, 0xFFFFFFFF, write32_test # clear pending high interrupts +# .4byte rise_ip, 0xFFFFFFFF, write32_test # clear pending rise interrupts +# .4byte fall_ip, 0xFFFFFFFF, write32_test # clear pending fall interrupts +# .4byte high_ip, 0xA55A0000, read32_test # check pending high interrupts +# .4byte low_ip, 0x5AA5FFFF, read32_test # check pending low interrupts +# .4byte rise_ip, 0x00000000, read32_test # check pending rise interrupts +# .4byte fall_ip, 0x00000000, read32_test # check pending fall interrupts +# .4byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts +# .4byte input_val, 0xA4AA0000, read32_test # check new output matches expected output +# .4byte high_ip, 0xA5FA00000, read32_test # high interrupt pending *** (is this correct?) +# .4byte low_ip, 0x5BF50000, read32_test # low interrupt pending should be opposite high for enabled pins +# .4byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising) +# .4byte fall_ip, 0x01500000, read32_test # check for changed bits (falling) + +# # =========== Test Interrupt Enable without interrupts =========== + +# .4byte high_ie, 0x00010000, write32_test # enable high interrupt on bit 16, no pending interrupt +# .4byte high_ip, 0xA5FA0000, read32_test # read to show no interrupt has happened +# .4byte low_ie, 0x00020000, write32_test # enable low interrupt on bit 17, no pending interrupt +# .4byte low_ip, 5BF50000, read32_test # read to show no interrupt has happened + .4byte 0x0, 0x0, terminate_test # terminate tests