diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 9cf0a41f..59e9435a 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -55,7 +55,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   input  logic                   SelBusBeat,        // Word in cache line comes from BeatCount
   input  logic [LOGBWPL-1:0]     BeatCount,         // Beat in burst
   input  logic [LINELEN-1:0]     FetchBuffer,       // Buffer long enough to hold entire cache line arriving from bus
-  output logic [1:0]             CacheBusRW,        // [1] Read or [0] write bus
+  output logic [1:0]             CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
   output logic [`PA_BITS-1:0]    CacheBusAdr        // Address for bus access
 );
 
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index 5dba257d..3afb5858 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -29,30 +29,28 @@
 module cachefsm (
   input  logic       clk,
   input  logic       reset,
+  // hazard and privilege unit
+  input  logic       Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
+  input  logic       FlushStage,        // Pipeline flush of second stage (prevent writes and bus operations)
+  output logic       CacheCommitted,    // Cache has started bus operation that shouldn't be interrupted
+  output logic       CacheStall,        // Cache stalls pipeline during multicycle operation
   // inputs from IEU
-  input  logic       FlushStage,
-  input  logic [1:0] CacheRW,
-  input  logic [1:0] CacheAtomic,
-  input  logic       FlushCache,
-  input  logic       InvalidateCache,
-  // hazard inputs
-  input  logic       Stall,
-  // Bus inputs
-  input  logic       CacheBusAck,
-  // dcache internals
-  input  logic       CacheHit,
-  input  logic       LineDirty,
-  input  logic       FlushAdrFlag,
-  input  logic       FlushWayFlag, 
-
-  // hazard outputs
-  output logic       CacheStall,
-  // counter outputs
-  output logic       CacheMiss,
-  output logic       CacheAccess,
+  input  logic [1:0] CacheRW,           // [1] Read, [0] Write 
+  input  logic [1:0] CacheAtomic,       // Atomic operation
+  input  logic       FlushCache,        // Flush all dirty lines back to memory
+  input  logic       InvalidateCache,   // Clear all valid bits
+  // cache internals
+  input  logic       CacheHit,          // Exactly 1 way hits
+  input  logic       LineDirty,         // The selected line and way is dirty
+  input  logic       FlushAdrFlag,      // On last set of a cache flush
+  input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
+  // Bus controls
+  input  logic       CacheBusAck,       // Bus operation completed
+  output logic [1:0] CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
+  // performance counter outputs
+  output logic       CacheMiss,         // Cache miss  
+  output logic       CacheAccess,		// Cache access
   // Bus outputs
-  output logic       CacheCommitted,
-  output logic [1:0] CacheBusRW,
 
   // dcache internals
   output logic       SelAdr,
@@ -114,8 +112,6 @@ module cachefsm (
     case (CurrState)
       STATE_READY: if(InvalidateCache)                      NextState = STATE_READY;
                    else if(FlushCache)                      NextState = STATE_FLUSH;
-      // Delayed LRU update.  Cannot check if victim line is dirty on this cycle.
-      // To optimize do the fetch first, then eviction if necessary.
                    else if(AnyMiss & ~LineDirty)            NextState = STATE_FETCH;
                    else if(AnyMiss & LineDirty)             NextState = STATE_WRITEBACK;
                    else                                     NextState = STATE_READY;
@@ -128,11 +124,11 @@ module cachefsm (
                               else                          NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
       STATE_FLUSH: if(LineDirty)                            NextState = STATE_FLUSH_WRITEBACK;
-	               else if (FlushFlag)                        NextState = STATE_READ_HOLD;
-	               else                                       NextState = STATE_FLUSH;
-	  STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag)     NextState = STATE_FLUSH;
-	                          else if(CacheBusAck)            NextState = STATE_READ_HOLD;
-	                          else                            NextState = STATE_FLUSH_WRITEBACK;
+	               else if (FlushFlag)                      NextState = STATE_READ_HOLD;
+	               else                                     NextState = STATE_FLUSH;
+	  STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag)   NextState = STATE_FLUSH;
+	                          else if(CacheBusAck)          NextState = STATE_READ_HOLD;
+	                          else                          NextState = STATE_FLUSH_WRITEBACK;
       default:                                              NextState = STATE_READY;
     endcase
   end
@@ -174,7 +170,7 @@ module cachefsm (
   assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
                           (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
                      (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck);
-  // **** can this be simplified?
+
   assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed
                   (CurrState == STATE_FETCH) |
                   (CurrState == STATE_WRITEBACK) |