diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 8c05c8a4..5456ce8b 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -133,6 +133,7 @@ logic [3:0] dummy;
         "wally32periph":                   tests = wally32periph;
         "embench":                        tests = embench;
         "coremark":                       tests = coremark;
+        "arch32ba":     if (`ZBA_SUPPORTED) tests = arch32ba;
       endcase
     end
     if (tests.size() == 0) begin
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index ec83f8c6..bbc82d9a 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -944,6 +944,14 @@ string imperas32f[] = '{
     "rv32i_m/Zifencei/src/Fencei.S"
     };
 
+  string arch32ba[] = '{
+    `RISCVARCHTEST,
+    // *** unclear why add.uw isn't in the list
+    "rv64i_m/B/src/sh1add-01.S",
+    "rv64i_m/B/src/sh1add-02.S",
+    "rv64i_m/B/src/sh1add-013.S"
+  };
+
   string arch64m[] = '{
     `RISCVARCHTEST,
     "rv64i_m/M/src/div-01.S",
diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml
index 04a5da18..3438e17a 100644
--- a/tests/riscof/spike/spike_rv32imc_isa.yaml
+++ b/tests/riscof/spike/spike_rv32imc_isa.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMAFDCZicsr_Zifencei
+  ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml
index d3dad15c..a8837ac7 100644
--- a/tests/riscof/spike/spike_rv64gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv64gc_isa.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV64IMAFDCSUZicsr_Zifencei
+  ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]