diff --git a/pipelined/src/generic/flop/bram1p1rw.sv b/pipelined/src/generic/flop/bram1p1rw.sv
index cccf1f1f..d0d3c40a 100644
--- a/pipelined/src/generic/flop/bram1p1rw.sv
+++ b/pipelined/src/generic/flop/bram1p1rw.sv
@@ -44,8 +44,8 @@ module bram1p1rw
 	//----------------------------------------------------------------------
 	) (
 	   input logic 					 clk,
-	   input logic 					 en,
-	   input logic [NUM_COL-1:0] 	 we,
+	   input logic 					 we,
+	   input logic [NUM_COL-1:0] 	 bwe,
 	   input logic [ADDR_WIDTH-1:0]  addr,
 	   output logic [DATA_WIDTH-1:0] dout,
 	   input logic [DATA_WIDTH-1:0]  din
@@ -60,9 +60,9 @@ module bram1p1rw
 
   always @ (posedge clk) begin
 	dout <= RAM[addr];    
-	if(en) begin
+	if(we) begin
 	  for(i=0;i<NUM_COL;i=i+1) begin
-		if(we[i]) begin
+		if(bwe[i]) begin
 		  RAM[addr][i*COL_WIDTH +: COL_WIDTH] <= din[i*COL_WIDTH +:COL_WIDTH];
 		end
 	  end
diff --git a/pipelined/src/generic/flop/bram2p1r1w.sv b/pipelined/src/generic/flop/bram2p1r1w.sv
index 7c6f9aa8..de5a09f2 100644
--- a/pipelined/src/generic/flop/bram2p1r1w.sv
+++ b/pipelined/src/generic/flop/bram2p1r1w.sv
@@ -46,11 +46,11 @@ module bram2p1r1w
 	//----------------------------------------------------------------------
 	) (
 	   input logic 					 clk,
-	   input logic 					 enaA,
+	   input logic 					 reA,
 	   input logic [ADDR_WIDTH-1:0]  addrA,
 	   output logic [DATA_WIDTH-1:0] doutA,
-	   input logic 					 enaB,
-	   input logic [NUM_COL-1:0] 	 weB,
+	   input logic 					 weB,
+	   input logic [NUM_COL-1:0] 	 bweB,
 	   input logic [ADDR_WIDTH-1:0]  addrB,
 	   input logic [DATA_WIDTH-1:0]  dinB
 	   );
@@ -128,15 +128,15 @@ module bram2p1r1w
 
   // Port-A Operation
   always @ (posedge clk) begin
-	if(enaA) begin
+	if(reA) begin
 	  doutA <= RAM[addrA];
 	end
   end
   // Port-B Operation:
   always @ (posedge clk) begin
-	if(enaB) begin
+	if(weB) begin
 	  for(i=0;i<NUM_COL;i=i+1) begin
-		if(weB[i]) begin
+		if(bweB[i]) begin
 		  RAM[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +:COL_WIDTH];
 		end
 	  end
diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index aaa653ff..b0802161 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -43,6 +43,6 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
   localparam OFFSET = $clog2(`XLEN/8);
 
   bram1p1rw #(`XLEN/8, 8, ADDR_WDITH) 
-    memory(.clk, .en(we), .we(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd));
+    memory(.clk, .we, .bwe(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd));
 endmodule
 
diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv
index c53d1f48..40bf81eb 100644
--- a/pipelined/src/uncore/ram.sv
+++ b/pipelined/src/uncore/ram.sv
@@ -63,7 +63,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   // *** this seems like a weird way to use reset
   flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELRam &  HWRITE, memwrite);
   flopenr #(32)   haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A);
-  
+
   // busy FSM to extend READY signal
   always @(posedge HCLK, negedge HRESETn) 
     if (~HRESETn) begin
@@ -97,11 +97,31 @@ module ram #(parameter BASE=0, RANGE = 65535) (
     HWADDR <= #1 A;
 
   bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA)
-  memory(.clk(HCLK), .enaA(1'b1),
+  memory(.clk(HCLK), .reA(1'b1),
 		 .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam),
-		 .enaB(memwrite & risingHREADYRam), .weB(ByteMaskM),
+		 .weB(memwrite & risingHREADYRam), .bweB(ByteMaskM),
 		 .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA));
+/*
+  bram1p1r1w #(`XLEN/8, 8, ADDR_WDITH)
+    memory(.clk(HCLK), .we(memwrite), .bwe(ByteMaskM), . addr(A***), .dout(HREADRam), .din(HWDATA));
 		 
+       #(
+	//--------------------------------------------------------------------------
+	parameter NUM_COL = 8,
+	parameter COL_WIDTH = 8,
+	parameter ADDR_WIDTH = 10,
+	// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
+	parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
+	//----------------------------------------------------------------------
+	) (
+	   input logic 					 clk,
+	   input logic 					 ena,
+	   input logic [NUM_COL-1:0] 	 we,
+	   input logic [ADDR_WIDTH-1:0]  addr,
+	   output logic [DATA_WIDTH-1:0] dout,
+	   input logic [DATA_WIDTH-1:0]  din
+	   );*/
+
   
 endmodule
   
diff --git a/pipelined/src/uncore/ram_orig.sv b/pipelined/src/uncore/ram_orig.sv
index e40da7b3..bc852cf0 100644
--- a/pipelined/src/uncore/ram_orig.sv
+++ b/pipelined/src/uncore/ram_orig.sv
@@ -97,9 +97,9 @@ module ram_orig #(parameter BASE=0, RANGE = 65535) (
     HWADDR <= #1 A;
 
   bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA)
-  memory(.clk(HCLK), .enaA(1'b1),
+  memory(.clk(HCLK), .reA(1'b1),
 		 .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam),
-		 .enaB(memwrite & risingHREADYRam), .weB(ByteMaskM),
+		 .weB(memwrite & risingHREADYRam), .bweB(ByteMaskM),
 		 .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA));