From 74b6d1319523a434a7f1e8168233914a89e8e85f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Jul 2021 20:08:04 -0400 Subject: [PATCH 1/2] Fixed missing stall in InstrRet counter --- wally-pipelined/src/mmu/tlbcontrol.sv | 2 +- wally-pipelined/src/mmu/tlblru.sv | 2 +- wally-pipelined/src/privileged/csrc.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv index 4d971e0e..c161ad2f 100644 --- a/wally-pipelined/src/mmu/tlbcontrol.sv +++ b/wally-pipelined/src/mmu/tlbcontrol.sv @@ -64,7 +64,7 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8, // Grab the sv mode from SATP and determine whether translation should occur assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 - assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation; + assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; generate if (`XLEN==64) begin assign SV39Mode = (SATP_MODE == `SV39); diff --git a/wally-pipelined/src/mmu/tlblru.sv b/wally-pipelined/src/mmu/tlblru.sv index 0059adb8..2fb0a503 100644 --- a/wally-pipelined/src/mmu/tlblru.sv +++ b/wally-pipelined/src/mmu/tlblru.sv @@ -48,5 +48,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits); - + // *** seems like enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 endmodule diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 9e47eece..db4986bc 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -114,7 +114,7 @@ module csrc #(parameter // Counter adders with inhibits for power savings assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]}; //assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited - assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]}; + assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~StallW & ~MCOUNTINHIBIT_REGW[2]}; //assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls //assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0]; From 5c2f774c35627163a465a75d89129e13a1221fff Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Jul 2021 23:34:24 -0400 Subject: [PATCH 2/2] Simplified tlbmixer mux to and-or --- wally-pipelined/src/mmu/tlbcontrol.sv | 2 +- wally-pipelined/src/privileged/csrs.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv index c161ad2f..cd938625 100644 --- a/wally-pipelined/src/mmu/tlbcontrol.sv +++ b/wally-pipelined/src/mmu/tlbcontrol.sv @@ -122,5 +122,5 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8, endgenerate assign TLBHit = CAMHit & TLBAccess; - assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess; + assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess; endmodule diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index 0daaf4f5..116f6792 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -93,7 +93,7 @@ module csrs #(parameter if (`MEM_VIRTMEM) flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); else - assign SATP_REGW = 0; + assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported if (`BUSYBEAR == 1) flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW); else if (`BUILDROOT == 1)