From 3a9bc1e8c1dbdb3e7af9dfa77b74021be5d7475b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 26 Sep 2021 13:22:23 -0500 Subject: [PATCH] Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies the flash card to dram. Fixed latch issue in the sd card reader. --- testsBP/fpga-test-sdc/bios.s | 98 +++++++++++ testsBP/fpga-test-sdc/old.asm | 154 ++++++++++++++++++ .../{test-sdc.s => test-sdc.asm} | 0 wally-pipelined/src/sdc/SDC.sv | 3 + .../src/wally/wallypipelinedsocwrapper.v | 16 +- 5 files changed, 266 insertions(+), 5 deletions(-) create mode 100644 testsBP/fpga-test-sdc/bios.s create mode 100644 testsBP/fpga-test-sdc/old.asm rename testsBP/fpga-test-sdc/{test-sdc.s => test-sdc.asm} (100%) diff --git a/testsBP/fpga-test-sdc/bios.s b/testsBP/fpga-test-sdc/bios.s new file mode 100644 index 00000000..e8e23fc8 --- /dev/null +++ b/testsBP/fpga-test-sdc/bios.s @@ -0,0 +1,98 @@ +#PERIOD = 22000000 +PERIOD = 20 + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, 0x87FFFFF8 + + li a0, 0x00000000 + li a1, 0x80000000 + li a2, 128*1024*1024 # copy 128MB + jal ra, copyFlash + + + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1001200C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hard ID to a0 + li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB + la a2, end_of_bios + li t0, 0x80000000 # start of code + jalr x0, t0, 0 + +end_of_bios: + + + + diff --git a/testsBP/fpga-test-sdc/old.asm b/testsBP/fpga-test-sdc/old.asm new file mode 100644 index 00000000..c65b9557 --- /dev/null +++ b/testsBP/fpga-test-sdc/old.asm @@ -0,0 +1,154 @@ + # start by writting the clock divider to 4 setting SDC to 25MHz + la x3, 0x12100 + li x4, -4 + sw x4, 0x0(x3) + + # start by writting the clock divider to 1 setting SDC to 100MHZ + la x3, 0x12100 + li x4, 1 + sw x4, 0x0(x3) + + + # wait until the SDC is done with initialization + li x4, 0x1 +wait_sdc_done_init: + lw x5, 4(x3) + and x5, x5, x4 + bne x5, x4, wait_sdc_done_init + + # now that it is done lets setup for a read + li x6, 0x20000000 + sd x6, 0x10(x3) # write address register + + # send read by writting to command register + li x7, 0x4 + sw x7, 0x8(x3) + + li x4, 0x2 +wait_sdc_done_read: + lw x5, 4(x3) + and x5, x5, x4 + beq x5, x4, wait_sdc_done_read + + # copy data from mailbox + li x11, 0x80000000 + li x9, 0 +copy_sdc: + li x8, 512/8 + ld x10, 0x18(x3) # read the mailbox + sd x10, 0x0(x11) # write to dram + addi x9, x9, 1 + addi x11, x11, 8 + blt x9, x8, copy_sdc + + # second read of sdc + # now that it is done lets setup for a read + li x6, 0x20000200 + sd x6, 0x10(x3) # write address register + + # send read by writting to command register + li x7, 0x4 + sw x7, 0x8(x3) + + li x4, 0x2 +wait_sdc_done_read2: + lw x5, 4(x3) + and x5, x5, x4 + beq x5, x4, wait_sdc_done_read2 + + # copy data from mailbox + li x11, 0x80000200 + li x9, 0 +copy_sdc2: + li x8, 512/8 + ld x10, 0x18(x3) # read the mailbox + sd x10, 0x0(x11) # write to dram + addi x9, x9, 1 + addi x11, x11, 8 + blt x9, x8, copy_sdc2 + + + + # write to gpio + li x2, 0xFF + la x3, 0x10012000 + + # +8 is output enable + # +C is output value + + addi x4, x3, 8 + addi x5, x3, 0xC + + # write initial value of 0xFF to GPO + sw x2, 0x0(x5) + # enable output + sw x2, 0x0(x4) + + # before jumping to led loop + # lets try writting to dram. + + li x21, 0 + li x23, 4096*16 # 64KB of data + + li x22, 0x80000000 + li x24, 0 + +write_loop: + add x25, x22, x24 + sw x24, 0(x25) + addi x24, x24, 4 + blt x24, x23, write_loop + + li x24, 0 +read_loop: + add x25, x22, x24 + lw x21, 0(x25) + + # check value + bne x21, x24, fail_loop + + addi x24, x24, 4 + + # + blt x24, x23, read_loop + + + +loop: + + # delay + li x20, PERIOD +delay1: + addi x20, x20, -1 + bge x20, x0, delay1 + + # new GPO + addi x2, x2, 1 + sw x2, 0x0(x5) + + j loop + + +fail_loop: + + # delay + li x20, PERIOD/20 +fail_delay1: + addi x20, x20, -1 + bge x20, x0, fail_delay1 + + # clear GPO + sw x0, 0x0(x5) + + # delay + li x20, PERIOD/20 +fail_delay2: + addi x20, x20, -1 + bge x20, x0, fail_delay2 + + # write GPO + sw x2, 0x0(x5) + + j fail_loop + + diff --git a/testsBP/fpga-test-sdc/test-sdc.s b/testsBP/fpga-test-sdc/test-sdc.asm similarity index 100% rename from testsBP/fpga-test-sdc/test-sdc.s rename to testsBP/fpga-test-sdc/test-sdc.asm diff --git a/wally-pipelined/src/sdc/SDC.sv b/wally-pipelined/src/sdc/SDC.sv index 1f66e770..90865466 100644 --- a/wally-pipelined/src/sdc/SDC.sv +++ b/wally-pipelined/src/sdc/SDC.sv @@ -297,6 +297,9 @@ module SDC HREADYSDC = 1'b1; ReadDone = 1'b1; end + default: begin + NextState = STATE_READY; + end endcase end diff --git a/wally-pipelined/src/wally/wallypipelinedsocwrapper.v b/wally-pipelined/src/wally/wallypipelinedsocwrapper.v index 547997a9..bfc3e140 100644 --- a/wally-pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/wally-pipelined/src/wally/wallypipelinedsocwrapper.v @@ -37,7 +37,7 @@ module wallypipelinedsocwrapper ( // inputs from external memory input [`AHBW-1:0] HRDATAEXT, input HREADYEXT, HRESPEXT, - output HSELEXT, + output HSELEXT, // outputs to external memory, shared with uncore memory output HCLK, HRESETn, output [31:0] HADDR, @@ -48,13 +48,16 @@ module wallypipelinedsocwrapper ( output [3:0] HPROT, output [1:0] HTRANS, output HMASTLOCK, - output HREADY, + output HREADY, // I/O Interface input [3:0] GPIOPinsIn_IO, - output [4:0] GPIOPinsOut_IO, + output [4:0] GPIOPinsOut_IO, input UARTSin, output UARTSout, - input ddr4_calib_complete + input ddr4_calib_complete, + input [3:0] SDCDat, + output SDCCLK, + inout SDCCmd ); wire [31:0] GPIOPinsEn; @@ -105,6 +108,9 @@ module wallypipelinedsocwrapper ( .GPIOPinsOut(GPIOPinsOut), .GPIOPinsEn(GPIOPinsEn), .UARTSin(UARTSin), - .UARTSout(UARTSout)); + .UARTSout(UARTSout), + .SDCDat(SDCDat), + .SDCCLK(SDCCLK), + .SDCCmd(SDCCmd)); endmodule