From 76bba541a7297c1799398d90d8e19aaca757895f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 24 Oct 2021 21:21:49 -0500 Subject: [PATCH 1/4] Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. --- wally-pipelined/src/cache/sram1rw.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/cache/sram1rw.sv b/wally-pipelined/src/cache/sram1rw.sv index d2b4b847..835e7061 100644 --- a/wally-pipelined/src/cache/sram1rw.sv +++ b/wally-pipelined/src/cache/sram1rw.sv @@ -14,13 +14,19 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) ( ); logic [WIDTH-1:0][DEPTH-1:0] StoredData; + logic [$clog2(WIDTH)-1:0] AddrD; + always_ff @(posedge clk) begin - ReadData <= StoredData[Addr]; + AddrD <= Addr; if (WriteEnable) begin StoredData[Addr] <= #1 WriteData; end end + + + assign ReadData = StoredData[AddrD]; + endmodule /* verilator lint_on ASSIGNDLY */ From 2bf51362e243157fab73c9f254fbccf808514dca Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 25 Oct 2021 10:05:41 -0700 Subject: [PATCH 3/4] Added synchronizer to reset --- wally-pipelined/regression/lint-wally | 5 ++--- wally-pipelined/src/wally/wallypipelinedsoc.sv | 6 +++++- wally-pipelined/testbench/testbench.sv | 6 +++--- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/regression/lint-wally b/wally-pipelined/regression/lint-wally index 67cc7a64..a61624aa 100755 --- a/wally-pipelined/regression/lint-wally +++ b/wally-pipelined/regression/lint-wally @@ -7,7 +7,7 @@ verilator=`which verilator` basepath=$(dirname $0)/.. for config in rv64g rv32g; do echo "$config linting..." - if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then + if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi @@ -17,6 +17,5 @@ echo "All lints run with no errors or warnings" # --lint-only just runs lint rather than trying to compile and simulate # -I points to the include directory where files such as `include wally-config.vh are found -# For more exhaustive (and sometimes spurious) warnings, run: -# verilator --lint-only -Wall -Iconfig/rv64ic src/* +# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist. diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 94588958..bd6bf372 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -32,7 +32,8 @@ `include "wally-config.vh" module wallypipelinedsoc ( - input logic clk, reset, + input logic clk, reset_ext, + output logic reset, // AHB Lite Interface // inputs from external memory input logic [`AHBW-1:0] HRDATAEXT, @@ -63,6 +64,9 @@ module wallypipelinedsoc ( logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; + + // synchronize reset to SOC clock domain + synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); // instantiate processor and memories wallypipelinedhart hart(.clk, .reset, diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 79945d2f..d2c83a4c 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -34,7 +34,7 @@ module testbench; parameter TEST="none"; logic clk; - logic reset; + logic reset_ext, reset; parameter SIGNATURESIZE = 5000000; @@ -209,7 +209,7 @@ logic [3:0] dummy; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; $display("Read memfile %s", memfilename); - reset = 1; # 42; reset = 0; + reset_ext = 1; # 42; reset_ext = 0; end // generate clock to sequence tests @@ -290,7 +290,7 @@ logic [3:0] dummy; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; $display("Read memfile %s", memfilename); - reset = 1; # 17; reset = 0; + reset_ext = 1; # 47; reset_ext = 0; end end end // always @ (negedge clk) From fbee4963daa7c27dad9f649247966889f8fb3150 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 25 Oct 2021 11:49:20 -0700 Subject: [PATCH 4/4] Converted flops to synchronous reset now that reset signal is synchronized --- wally-pipelined/src/generic/flop/flopenl.sv | 4 +- wally-pipelined/src/generic/flop/flopenr.sv | 4 +- wally-pipelined/src/generic/flop/flopenrc.sv | 4 +- wally-pipelined/src/generic/flop/flopens.sv | 4 +- wally-pipelined/src/generic/flop/flopr.sv | 4 +- wally-pipelined/src/generic/flop/floprc.sv | 10 ++--- .../src/generic/flop/synchronizer.sv | 41 +++++++++++++++++++ 7 files changed, 55 insertions(+), 16 deletions(-) create mode 100644 wally-pipelined/src/generic/flop/synchronizer.sv diff --git a/wally-pipelined/src/generic/flop/flopenl.sv b/wally-pipelined/src/generic/flop/flopenl.sv index acf3f2a0..4361dc4c 100644 --- a/wally-pipelined/src/generic/flop/flopenl.sv +++ b/wally-pipelined/src/generic/flop/flopenl.sv @@ -25,14 +25,14 @@ `include "wally-config.vh" -// flop with enable, asynchronous load +// flop with enable, synchronous load module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( input logic clk, load, en, input TYPE d, input TYPE val, output TYPE q); - always_ff @(posedge clk, posedge load) + always_ff @(posedge clk) if (load) q <= #1 val; else if (en) q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/flopenr.sv b/wally-pipelined/src/generic/flop/flopenr.sv index 9db912ea..a30535d8 100644 --- a/wally-pipelined/src/generic/flop/flopenr.sv +++ b/wally-pipelined/src/generic/flop/flopenr.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with enable, asynchronous reset +// flop with enable, synchronous reset module flopenr #(parameter WIDTH = 8) ( input logic clk, reset, en, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) q <= #1 0; else if (en) q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/flopenrc.sv b/wally-pipelined/src/generic/flop/flopenrc.sv index d8806196..010a5210 100644 --- a/wally-pipelined/src/generic/flop/flopenrc.sv +++ b/wally-pipelined/src/generic/flop/flopenrc.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with enable, asynchronous reset, synchronous clear +// flop with enable, synchronous reset, enabled clear module flopenrc #(parameter WIDTH = 8) ( input logic clk, reset, clear, en, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) q <= #1 0; else if (en) if (clear) q <= #1 0; diff --git a/wally-pipelined/src/generic/flop/flopens.sv b/wally-pipelined/src/generic/flop/flopens.sv index d51659b8..22c6061c 100644 --- a/wally-pipelined/src/generic/flop/flopens.sv +++ b/wally-pipelined/src/generic/flop/flopens.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with enable, asynchronous set +// flop with enable, synchronous set module flopens #(parameter WIDTH = 8) ( input logic clk, set, en, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge set) + always_ff @(posedge clk) if (set) q <= #1 1; else if (en) q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/flopr.sv b/wally-pipelined/src/generic/flop/flopr.sv index 5ff6a5a9..e89f28e5 100644 --- a/wally-pipelined/src/generic/flop/flopr.sv +++ b/wally-pipelined/src/generic/flop/flopr.sv @@ -25,13 +25,13 @@ `include "wally-config.vh" -// flop with asynchronous reset +// flop with synchronous reset module flopr #(parameter WIDTH = 8) ( input logic clk, reset, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) q <= #1 0; else q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/floprc.sv b/wally-pipelined/src/generic/flop/floprc.sv index 9d5f17c7..27d0076f 100644 --- a/wally-pipelined/src/generic/flop/floprc.sv +++ b/wally-pipelined/src/generic/flop/floprc.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" -// flop with asynchronous reset, synchronous clear +// flop with synchronous reset, synchronous clear module floprc #(parameter WIDTH = 8) ( input logic clk, input logic reset, @@ -33,9 +33,7 @@ module floprc #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk, posedge reset) - if (reset) q <= #1 0; - else - if (clear) q <= #1 0; - else q <= #1 d; + always_ff @(posedge clk) + if (reset | clear ) q <= #1 0; + else q <= #1 d; endmodule diff --git a/wally-pipelined/src/generic/flop/synchronizer.sv b/wally-pipelined/src/generic/flop/synchronizer.sv new file mode 100644 index 00000000..ab4255c1 --- /dev/null +++ b/wally-pipelined/src/generic/flop/synchronizer.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// synchronizer.sv +// +// Written: David_Harris@hmc.edu 25 October 2021 +// Modified: +// +// Purpose: Two-stage flip-flop synchronizer +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// ordinary flip-flop +module synchronizer ( + input logic clk, + input logic d, + output logic q); + + logic mid; + + always_ff @(posedge clk) begin + mid <= #1 d; + q <= #1 d; + end +endmodule +