From 39ceb3a5505c4429ff775819583811954eba83e2 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 12 May 2022 16:16:42 +0000
Subject: [PATCH] Partitioned privilege mode fsm into new module

---
 pipelined/src/privileged/privileged.sv |  8 ++--
 pipelined/src/privileged/privmode.sv   | 66 ++++++++++++++++++++++++++
 pipelined/testbench/testbench-linux.sv |  2 +-
 3 files changed, 72 insertions(+), 4 deletions(-)
 create mode 100644 pipelined/src/privileged/privmode.sv

diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index ca3a3422..64740747 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -81,8 +81,6 @@ module privileged (
   output logic             BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
 );
 
-  logic [1:0] NextPrivilegeModeM;
-
   logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
   logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
   logic [`XLEN-1:0] MEDELEG_REGW;
@@ -102,15 +100,18 @@ module privileged (
   logic       STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;
   logic       STATUS_MIE, STATUS_SIE;
   logic [11:0] MIP_REGW, MIE_REGW;
-  logic md;
   logic       StallMQ;
   logic WFITimeoutM; 
+  logic [1:0] NextPrivilegeModeM;
 
 
   ///////////////////////////////////////////
   // track the current privilege level
   ///////////////////////////////////////////
 
+  privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .CauseM, 
+                    .MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
+  /*
   // get bits of DELEG registers based on CAUSE
   assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
   
@@ -129,6 +130,7 @@ module privileged (
   end
 
   flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
+*/
 
   ///////////////////////////////////////////
   // WFI timeout Privileged Spec 3.1.6.5
diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv
new file mode 100644
index 00000000..d48c57d5
--- /dev/null
+++ b/pipelined/src/privileged/privmode.sv
@@ -0,0 +1,66 @@
+///////////////////////////////////////////
+// privmode.sv
+//
+// Written: David_Harris@hmc.edu 12 May 2022
+// Modified: 
+//
+// Purpose: Track privilege mode
+//          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module privmode (
+  input  logic             clk, reset,
+  input  logic             StallW, TrapM, mretM, sretM,
+  input  logic [`XLEN-1:0] CauseM, MEDELEG_REGW,
+  input  logic [11:0]      MIDELEG_REGW,
+  input  logic [1:0]       STATUS_MPP,
+  input  logic             STATUS_SPP,
+  output logic [1:0]       NextPrivilegeModeM, PrivilegeModeW
+); 
+  
+  if (`U_SUPPORTED) begin:privmode
+    logic       md;
+
+    // get bits of DELEG registers based on CAUSE
+    assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
+    
+    // PrivilegeMode FSM
+    always_comb begin
+      if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
+        if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
+                          NextPrivilegeModeM = `S_MODE;
+        else              NextPrivilegeModeM = `M_MODE;
+      end else if (mretM) NextPrivilegeModeM = STATUS_MPP;
+      else if (sretM)     NextPrivilegeModeM = {1'b0, STATUS_SPP};
+      else                NextPrivilegeModeM = PrivilegeModeW;
+    end
+
+    flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
+  end else begin  // only machine mode supported
+    assign NextPrivilegeModeM = `M_MODE;
+    assign PrivilegeModeW = `M_MODE;
+  end
+endmodule
\ No newline at end of file
diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
index 0173e35b..f405af48 100644
--- a/pipelined/testbench/testbench-linux.sv
+++ b/pipelined/testbench/testbench-linux.sv
@@ -138,7 +138,7 @@ module testbench;
   `define RF dut.core.ieu.dp.regf.rf
   `define PC dut.core.ifu.pcreg.q
   `define PRIV_BASE   dut.core.priv.priv
-  `define PRIV        `PRIV_BASE.privmodereg.q
+  `define PRIV        `PRIV_BASE.privmode.privmode.privmodereg.q
   `define CSR_BASE    `PRIV_BASE.csr
   `define MEIP        `PRIV_BASE.MExtInt
   `define SEIP        `PRIV_BASE.SExtInt