From 38bbe23d1470b6dc926108ae612e228cd22be828 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 3 Feb 2022 01:08:34 +0000 Subject: [PATCH] More config file cleanup; 32ic tests broken --- pipelined/config/buildroot/wally-config.vh | 3 +-- pipelined/config/fpga/wally-config.vh | 3 +-- pipelined/config/rv32etim/wally-config.vh | 3 +-- pipelined/config/rv32gc/wally-config.vh | 3 +-- pipelined/config/rv32ic/wally-config.vh | 3 +-- pipelined/config/rv32tim/wally-config.vh | 3 +-- pipelined/config/rv64BP/wally-config.vh | 3 +-- pipelined/config/rv64gc/wally-config.vh | 3 +-- pipelined/config/rv64ic/wally-config.vh | 3 +-- pipelined/regression/sim-wally | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/mmu/mmu.sv | 2 +- pipelined/src/privileged/csrs.sv | 4 ++-- pipelined/src/privileged/csrsr.sv | 2 +- pipelined/testbench/testbench-fpga.sv | 8 ++++---- pipelined/testbench/testbench-tim.sv | 16 ++++++++-------- pipelined/testbench/testbench.sv | 20 ++++++++++---------- 17 files changed, 37 insertions(+), 46 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index cd28ec05..f879ce2a 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -50,7 +50,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE -`define MEM_VIRTMEM 1 +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -62,7 +62,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index d09d3b0b..58efd046 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -49,7 +49,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE -`define MEM_VIRTMEM 1 +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -61,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv32etim/wally-config.vh b/pipelined/config/rv32etim/wally-config.vh index d0a9c879..bbeccbe8 100644 --- a/pipelined/config/rv32etim/wally-config.vh +++ b/pipelined/config/rv32etim/wally-config.vh @@ -50,7 +50,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_BUS `define IMEM `MEM_BUS -`define MEM_VIRTMEM 0 +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 0 // TLB configuration. Entries should be a power of 2 @@ -62,7 +62,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 1baa3a8d..a3859740 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -49,7 +49,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE -`define MEM_VIRTMEM 1 +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -61,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 27af914b..d0b8adfb 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -49,7 +49,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_TIM `define IMEM `MEM_TIM -`define MEM_VIRTMEM 0 +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -61,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv32tim/wally-config.vh b/pipelined/config/rv32tim/wally-config.vh index 32f43da2..0fb1dafa 100644 --- a/pipelined/config/rv32tim/wally-config.vh +++ b/pipelined/config/rv32tim/wally-config.vh @@ -49,7 +49,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_TIM `define IMEM `MEM_TIM -`define MEM_VIRTMEM 0 +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -61,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 81786fbb..78230552 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -51,7 +51,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE -`define MEM_VIRTMEM 1 +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -63,7 +63,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 5b64ddae..f5bc8a29 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -50,7 +50,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE -`define MEM_VIRTMEM 1 +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -62,7 +62,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 466535da..00b9a87f 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -50,7 +50,7 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_TIM `define IMEM `MEM_TIM -`define MEM_VIRTMEM 0 +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -62,7 +62,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index ec21b653..3eb310ca 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv32tim arch32i" +vsim -do "do wally-pipelined.do rv32ic arch32i" diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f94d9265..d57aedd3 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -110,7 +110,7 @@ module lsu ( // MMU include PMP and is needed if any privileged supported ///////////////////////////////////////////////////////////////////////////////////////////// - if(`MEM_VIRTMEM) begin : MEM_VIRTMEM + if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, .ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index c9778c15..bb74f137 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -97,7 +97,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries logic TLBPageFault; // only instantiate TLB if Virtual Memory is supported - if (`MEM_VIRTMEM) begin:tlb + if (`VIRTMEM_SUPPORTED) begin:tlb logic ReadAccess, WriteAccess; assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages assign WriteAccess = WriteAccessM; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index 87cf7765..be8b3adc 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -96,7 +96,7 @@ module csrs #(parameter flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); - if (`MEM_VIRTMEM) + if (`VIRTMEM_SUPPORTED) flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); else assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported @@ -129,7 +129,7 @@ module csrs #(parameter SEPC: CSRSReadValM = SEPC_REGW; SCAUSE: CSRSReadValM = SCAUSE_REGW; STVAL: CSRSReadValM = STVAL_REGW; - SATP: if (`MEM_VIRTMEM & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; + SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin CSRSReadValM = 0; if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1; diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 53e3bf1c..1ccf6c8d 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -96,7 +96,7 @@ module csrsr ( // SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not assign STATUS_SXL = `S_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if supervisor mode supported assign STATUS_UXL = `U_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if user mode supported - assign STATUS_SUM = `S_SUPPORTED & `MEM_VIRTMEM & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported + assign STATUS_SUM = `S_SUPPORTED & `VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic diff --git a/pipelined/testbench/testbench-fpga.sv b/pipelined/testbench/testbench-fpga.sv index b1603783..9f9024b8 100644 --- a/pipelined/testbench/testbench-fpga.sv +++ b/pipelined/testbench/testbench-fpga.sv @@ -549,7 +549,7 @@ string tests32f[] = '{ if (`M_SUPPORTED) tests = {tests, tests64m}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; + if (`VIRTMEM_SUPPORTED) tests = {tests64mmu, tests}; if (`A_SUPPORTED) tests = {tests64a, tests}; end //tests = {tests64a, tests}; @@ -565,7 +565,7 @@ string tests32f[] = '{ else tests = {tests, tests32iNOc}; if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; if (`F_SUPPORTED) tests = {tests32f, tests}; - if (`MEM_VIRTMEM) tests = {tests32mmu, tests}; + if (`VIRTMEM_SUPPORTED) tests = {tests32mmu, tests}; if (`A_SUPPORTED) tests = {tests32a, tests}; end end @@ -782,10 +782,10 @@ module riscvassertions(); assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS) else $error("DCACHE_LINELENINBITS must be a power of 2"); diff --git a/pipelined/testbench/testbench-tim.sv b/pipelined/testbench/testbench-tim.sv index a5da301a..9ac4f84e 100644 --- a/pipelined/testbench/testbench-tim.sv +++ b/pipelined/testbench/testbench-tim.sv @@ -92,7 +92,7 @@ logic [3:0] dummy; "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; "imperas64p": tests = imperas64p; -// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu; +// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64m": if (`M_SUPPORTED) tests = imperas64m; @@ -115,7 +115,7 @@ logic [3:0] dummy; "arch32f": if (`F_SUPPORTED) tests = arch32f; "imperas32i": tests = imperas32i; "imperas32p": tests = imperas32p; -// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; +// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; "imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32m": if (`M_SUPPORTED) tests = imperas32m; "imperas32a": if (`A_SUPPORTED) tests = imperas32a; @@ -347,24 +347,24 @@ endmodule module riscvassertions; initial begin assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support"); + assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported."); + assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); end diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 2832370c..4e52a916 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -92,7 +92,7 @@ logic [3:0] dummy; "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; "imperas64p": tests = imperas64p; -// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu; +// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64m": if (`M_SUPPORTED) tests = imperas64m; @@ -116,7 +116,7 @@ logic [3:0] dummy; "arch32f": if (`F_SUPPORTED) tests = arch32f; "imperas32i": tests = imperas32i; "imperas32p": tests = imperas32p; -// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; +// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; "imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32m": if (`M_SUPPORTED) tests = imperas32m; "imperas32a": if (`A_SUPPORTED) tests = imperas32a; @@ -334,30 +334,30 @@ endmodule module riscvassertions; initial begin assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support"); + assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported."); + assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); - assert (`DMEM == `MEM_CACHE | `MEM_VIRTMEM ==0) else $error("Virtual memory needs dcache"); - assert (`IMEM == `MEM_CACHE | `MEM_VIRTMEM ==0) else $error("Virtual memory needs icache"); + assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); end endmodule