From 3867142f10bd279ffc949263148a1cebaa43d643 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 5 Apr 2023 11:36:02 -0700 Subject: [PATCH] change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe the byte write-enables were always tied high, so we can use RAM without byte-enable to increase coverage. --- src/cache/cacheway.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 8f5fe79a..e5df9456 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -107,8 +107,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), - .addr(CacheSet), .dout(ReadTag), .bwe('1), + ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), + .addr(CacheSet), .dout(ReadTag), .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); // AND portion of distributed tag multiplexer