From 64f15d48de1e04cf0de335299a8b2582cb3c99d0 Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Thu, 30 Mar 2023 19:44:55 -0500 Subject: [PATCH 1/3] Disable coverage for branches tested in fpu.s --- src/fpu/fctrl.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index ad900701..feb2034e 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -146,11 +146,13 @@ module fctrl ( ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) + // coverage off 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) - 7'b1101000: case(Rs2D) + // coverage on + 7'b1101000: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s 5'b00010: ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l l->s @@ -174,6 +176,7 @@ module fctrl ( 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase + // coverage off 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h @@ -197,7 +200,8 @@ module fctrl ( 5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu - endcase + endcase + // coverage on endcase endcase /* verilator lint_off CASEINCOMPLETE */ From d8bbb4286e64cba857ccef9e9d9a29931d9ebe9c Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Thu, 30 Mar 2023 20:01:11 -0500 Subject: [PATCH 2/3] Add comments to fpu.S indicating which lines of src/fpu/fctrl.sv are covered --- tests/coverage/fpu.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 1a2d5ce7..b93b7505 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -28,7 +28,7 @@ main: - bseti t0, zero, 14 # turn on FPU + #bseti t0, zero, 14 # turn on FPU csrs mstatus, t0 # Test legal instructions not covered elsewhere @@ -36,8 +36,12 @@ main: flh ft0, 8(a0) fsq ft0, 0(a0) fsh ft0, 8(a0) + + # Tests for fpu/fctrl.sv + ## The following cover lines 149 to 154 fcvt.h.s ft1, ft0 fcvt.q.s ft2, ft0 + ## The following cover lines 179 to 204 fcvt.h.w ft3, a0 fcvt.h.wu ft3, a0 fcvt.h.l ft3, a0 @@ -55,7 +59,6 @@ main: fcvt.l.q a0, ft3 fcvt.lu.q a0, ft3 - # Test illegal instructions are detected .word 0x00000007 // illegal floating-point load (bad Funct3) .word 0x00000027 // illegal floating-point store (bad Funct3) From 913cdecb65d5bb97fb5516e66e2eec428fc4b74d Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Fri, 31 Mar 2023 09:51:33 -0500 Subject: [PATCH 3/3] Address comments in openhwgroup/cvw#180 --- src/fpu/fctrl.sv | 2 ++ tests/coverage/fpu.S | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index feb2034e..9db3d670 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -147,6 +147,7 @@ module fctrl ( 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) // coverage off + // Not covered in testing because rv64gc does not support half or quad precision 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) @@ -177,6 +178,7 @@ module fctrl ( 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase // coverage off + // Not covered in testing because rv64gc does not support half or quad precision 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index b93b7505..3fdca6e8 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -38,10 +38,8 @@ main: fsh ft0, 8(a0) # Tests for fpu/fctrl.sv - ## The following cover lines 149 to 154 fcvt.h.s ft1, ft0 fcvt.q.s ft2, ft0 - ## The following cover lines 179 to 204 fcvt.h.w ft3, a0 fcvt.h.wu ft3, a0 fcvt.h.l ft3, a0