diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index ad58f44f..b3400107 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -146,10 +146,13 @@ module fctrl (
                                                 ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
                       7'b0100001: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b01)
                                                 ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
+                      // coverage off
+                      // Not covered in testing because rv64gc does not support half or quad precision
                       7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
                                                 ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q)
                       7'b0100011: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b11)
                                                 ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d)
+                      // coverage on
                       7'b1101000: case(Rs2D)
                                     5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w   w->s
                                     5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
@@ -174,6 +177,8 @@ module fctrl (
                                     5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d   d->l
                                     5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d  d->lu
                                   endcase
+                      // coverage off
+                      // Not covered in testing because rv64gc does not support half or quad precision
                       7'b1101010: case(Rs2D)
                                     5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w   w->h
                                     5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h
@@ -198,7 +203,7 @@ module fctrl (
                                     5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q   q->l
                                     5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q  q->lu
                                   endcase
-                                
+                      // coverage on
                     endcase
       endcase
     end
@@ -329,4 +334,4 @@ module fctrl (
           {FRegWriteM, FResSelM, FCvtIntM},
           {FRegWriteW, FResSelW, FCvtIntW});
  
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S
index 1a2d5ce7..3fdca6e8 100644
--- a/tests/coverage/fpu.S
+++ b/tests/coverage/fpu.S
@@ -28,7 +28,7 @@
 
 main:
 
-    bseti t0, zero, 14  # turn on FPU
+    #bseti t0, zero, 14  # turn on FPU
     csrs mstatus, t0
 
     # Test legal instructions not covered elsewhere
@@ -36,6 +36,8 @@ main:
     flh ft0, 8(a0)
     fsq ft0, 0(a0)
     fsh ft0, 8(a0)
+
+    # Tests for fpu/fctrl.sv
     fcvt.h.s ft1, ft0
     fcvt.q.s ft2, ft0
     fcvt.h.w ft3, a0
@@ -55,7 +57,6 @@ main:
     fcvt.l.q a0, ft3
     fcvt.lu.q a0, ft3
 
- 
     # Test illegal instructions are detected
     .word 0x00000007 // illegal floating-point load (bad Funct3)
     .word 0x00000027 // illegal floating-point store (bad Funct3)