From 378c40002f967b11b7ef869eb670aecb744c2dd7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Dec 2022 08:27:39 -0800 Subject: [PATCH] Clean up interrupt masking by Commit --- pipelined/src/privileged/trap.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 32306ef7..c5c749b8 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -53,7 +53,7 @@ module trap ( logic Committed; logic BothInstrAccessFaultM; - (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; + (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; /////////////////////////////////////////// // Determine pending enabled interrupts @@ -66,8 +66,9 @@ module trap ( assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; assign Committed = CommittedM | CommittedF; - assign ValidIntsM = {12{~Committed}} & ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); - assign InterruptM = (|ValidIntsM) && InstrValidM && ~Committed; // suppress interrupt if the memory system has partially processed a request. + assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); + assign ValidIntsM = {12{~Committed}} & EnabledIntsM; + assign InterruptM = (|ValidIntsM) && InstrValidM; // suppress interrupt if the memory system has partially processed a request. assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);