From 372b9890ef6f82c818ffd38f4c8c293418650d29 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 28 Oct 2022 13:31:16 -0500 Subject: [PATCH] Untested change to uart test for outline of how to handle rx fifo timeout. --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 7146e833..1293d23a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1073,9 +1073,16 @@ uart_data_wait: li a4, 0x61 uart_read_LSR_IIR: lb t4, 0(t3) // save IIR before reading LSR mgith clear it +// check if t4 is the rxfifotime out interrupt if it is then read the fifo then go back and repeat this. + li t7, 6 + beq t4, t7, uart_rxfifo_timout lb t5, 0(t2) // read LSR andi t6, t5, 0x61 // wait until all transmissions are done and data is ready bne a4, t6, uart_read_LSR_IIR +uart_rxfifo_timout: +//read the fifo until empty + j uart_read_LSR_IIR + uart_data_ready: li t2, 0