From 370931c1cd1efa07b7f4963605170899550f658f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Feb 2023 00:39:26 -0600 Subject: [PATCH] Fixed bug #49. FFLAGS was updated while the pipeline was stalled. Also I found serveral performance counters which had similar issues. --- pipelined/src/privileged/csrc.sv | 10 +++++----- pipelined/src/privileged/csru.sv | 8 +++++--- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 94dbcaf4..ad9475d3 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -85,7 +85,7 @@ module csrc #(parameter if(`QEMU) begin: cevent // No other performance counters in QEMU assign CounterEvent[`COUNTERS-1:3] = 0; end else begin: cevent // User-defined counters - assign CounterEvent[3] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. + assign CounterEvent[3] = LoadStallM & InstrValidNotFlushedM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target @@ -93,10 +93,10 @@ module csrc #(parameter assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong - assign CounterEvent[11] = DCacheAccess; // data cache access - assign CounterEvent[12] = DCacheMiss; // data cache miss - assign CounterEvent[13] = ICacheAccess; // instruction cache access - assign CounterEvent[14] = ICacheMiss; // instruction cache miss + assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM; // data cache access + assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM; // data cache miss + assign CounterEvent[13] = ICacheAccess & InstrValidNotFlushedM; // instruction cache access + assign CounterEvent[14] = ICacheMiss & InstrValidNotFlushedM; // instruction cache miss assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 08e2035d..94b0683d 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -48,19 +48,21 @@ module csru #(parameter logic [4:0] FFLAGS_REGW; logic [2:0] NextFRMM; logic [4:0] NextFFLAGSM; - + logic SetOrWriteFFLAGSM; + // Write enables //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM; - assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; + assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; // Write Values assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM; + assign SetOrWriteFFLAGSM = WriteFFLAGSM | (|SetFflagsM & InstrValidNotFlushedM); // CSRs flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW); - flopr #(5) FFLAGSreg(clk, reset, NextFFLAGSM, FFLAGS_REGW); + flopenr #(5) FFLAGSreg(clk, reset, SetOrWriteFFLAGSM, NextFFLAGSM, FFLAGS_REGW); // CSR Reads always_comb begin